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Page 1: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

Adiabatic Logic as Low-Power

Design TechniqueSimulations & Results

Adiabatic Logic as Low-Power

Design TechniqueSimulations & Results

Presented by:

Muaayad Al-Mosawy

Presented to:

Dr. Maitham Shams

April 27, 2005

Page 2: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 2

Summery - 1Summery - 1 Three different Adiabatic Logic families (ECRL, 2N-

2N2P and CPAL) were investigated A single inverter, a chain of four and eight inverters

from each family were built and simulated to investigate the power consumption and compare it with the similar ones built in the Conventional CMOS logic

The chains were connected to a load of 0.1pF to have them all driving a same load

An 8-Bit Brent Kung Adder was built in two logic styles; Conventional CMOS and Complementary Pass-Transistor Adiabatic Logic (CPAL)

Page 3: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 3

Summery - 2Summery - 2

The power consumption for each adder style was compared with the other

A voltage supply of 1.2 v was used for all of the simulations and one more voltage supply (2.5 v) was used to run a second simulation for the adders

Five different frequencies (15.625 MHz, 31.25 MHz, 62.5 MHz, 125 MHz and 250 MHz) were used for each simulation and the power consumption for each run was recorded and compared among the others

Page 4: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 4

Inverters - 1Inverters - 1

Page 5: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 5

Inverters - 2Inverters - 2

Page 6: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 6

Single Inverters Power Compression

Single Inverters Power Compression

Page 7: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 7

Chain of Four Inverters Power Compression

Chain of Four Inverters Power Compression

Page 8: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 8

Chain of Eight Inverters Power Compression

Chain of Eight Inverters Power Compression

The Chain of four inverters shown in previous slide is extended to be of eight inverters

The clocks of the 1st four inverters were fed to next four inverter in the same sequence (PHI1 to inverter 5, PHI2 to Inverter 6 and so on)

Page 9: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 9

8-bit Brent Kung AdderCMOS Style

8-bit Brent Kung AdderCMOS Style

All input bits including Cin were connected to clocks so that they all go high in the same time and then come low all together

Page 10: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 10

8-bit Brent Kung AdderAdiabatic Style (CPAL)8-bit Brent Kung AdderAdiabatic Style (CPAL)

The inputs and their complements (Bar) were used and so for Cin

The adder consists of six stages Four clocks were used (PHI1, PHI2,

PHI1Bar and PHI2Bar) and the PHI1 And PHI2 were used for stage five and six

The outputs come also in Out and OutBar

Page 11: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 11

The Power Consumption Comparison Between the Two Adders

The Power Consumption Comparison Between the Two Adders

As the frequency increases, the power consumption slightly increases for the CPAL B-K adder comparing with the the increasing of a similar Conv. CMOS B-K Adder

Page 12: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 12

Conclusion 1 – Power Saving and Consumption of Single Inverters

Conclusion 1 – Power Saving and Consumption of Single Inverters

Power Saving

Power

Consumption

Page 13: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 13

Conclusion 2 – Power Saving and Consumption of Chain of 4 Inv.

Conclusion 2 – Power Saving and Consumption of Chain of 4 Inv.

Power Saving

Power

Consumption

Page 14: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 14

Conclusion 3 – Power Saving and Consumption of Chain of 8 Inv.

Conclusion 3 – Power Saving and Consumption of Chain of 8 Inv.

Power

Consumption

Power Saving

Page 15: Adiabatic Logic as Low-Power Design Technique Simulations & Results Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams April 27, 2005.

April 27, 2005 M. Al-Mosawy 15

Conclusion 4 – Power Saving and Consumption of B-K Adder

Conclusion 4 – Power Saving and Consumption of B-K Adder

Power Saving

Power

Consumption