MIXED SIGNAL LETTER
A new flipped voltage follower with enhanced bandwidthand low output impedance
Maneesha Gupta • Urvashi Singh
Received: 18 October 2011 / Revised: 13 April 2012 / Accepted: 23 April 2012 / Published online: 9 May 2012
� Springer Science+Business Media, LLC 2012
Abstract The paper proposes a flipped voltage follower
(FVF) cell with wider bandwidth and lower output
impedance as compared to the conventional FVF. These
improvements are obtained by adding a resistance in the
feedback path of conventional FVF. A current mirror is
implemented by using proposed FVF cell to verify the
performance improvement. The circuits are designed in
TSMC 0.18-lm CMOS technology with 1.5 V supply
voltage. The simulation results show that bandwidth
extension ratio (BWER) of newly developed FVF is 1.4
without peaking and 1.7 with peaking. The BWERs of the
passive-compensated current mirror implemented by using
proposed FVF cell are 1.28 without peaking and 1.58 with
peaking in the frequency response.
Keywords Flipped voltage follower � Analog integrated
circuits � Bandwidth � Current mirror � Resistive
compensation technique � BWER
1 Introduction
On comparing with conventional voltage followers, the
flipped voltage follower (FVF) is more developed and
improved voltage follower, therefore it is widely used in
various analog integrated circuits these days [2, 3]. Some
of special features of conventional FVF are [1] that it has
almost unity voltage gain on neglecting short-channel
effects. It can operate at very low voltage with large current
sinking capability and provides low output impedance.
The increasing demand of wireless equipments and high
speed communication systems has motivated the designers
to design mixed-mode integrated circuits with low power
consumption and wider bandwidth. Till now, work has
mainly being focused on improving the voltage swing [5],
and reducing both the output impedance [5, 6] and power
supply requirement [7] of voltage follower. However, no
work has been done so far in the direction of speed and
bandwidth improvement of FVF.
In this paper an improved FVF with enhanced bandwidth
and low output impedance is developed. There are different
techniques for bandwidth extension in analog and mixed-
signals circuits such as, (i) resistive compensation, (ii)
negative-capacitance compensation, (iii) inductive peaking,
(iv) feedforward compensation etc. [8–11]. Out of these
techniques, resistive compensation is employed in this paper
to enhance the bandwidth of this cell. The addition of a
resistance in the feedback path of the FVF increases its
impedance, which in turn reduces the current flowing
through it. This will force the current to flow through least
resistance path which is output path. This increased flow of
current to the output node will reduce the charging time of
the capacitors loaded at this node, thereby making it to work
faster [12]. Simulation results show that the bandwidth of
FVF cell increases from 5.058 to 7.1180 GHz i.e. BWER is
1.4. The bandwidths of passive and active-compensated
current mirrors introduced in [13] have been improved by
replacing conventional one with proposed FVF cell.
The paper is organized as follows: In Sect. 2, the small-
signal analysis is performed to derive the transfer function
and -3 dB frequency of conventional FVF. The -3 dB
frequency and output impedance of proposed FVF cell
are obtained in Sect. 3. In the next section, the newly
M. Gupta (&) � U. Singh
Netaji Subhash Institute of Technology, Sector-3, Dwarka,
New Delhi 110078, India
e-mail: [email protected]
U. Singh
e-mail: [email protected]
123
Analog Integr Circ Sig Process (2012) 72:279–288
DOI 10.1007/s10470-012-9864-1
developed FVF cell is then used in the current mirrors
suggested in [13]. The simulation results of the conven-
tional and proposed circuits are given in Sect. V. Finally
comparisons are made between conventional circuits and
improved circuits on the basis of simulation results, and
some conclusions are drawn in the last section.
2 Analysis of flipped voltage follower
The circuit of FVF is shown in Fig. 1(a) [1]. The conven-
tional FVF is a cascode amplifier. It is a negative feedback
circuit with series-shunt topology [14] where the feedback
is provided by transistor M2. Due to shunt configuration on
output side of FVF, the output impedance of FVF is low,
leading to high current sinking capability which is limited
by bias current Ib. On neglecting both the short-channel
effect and body effect, it is observed that the output current
variations are absorbed by transistor M2 and current
through transistor M1 is essentially constant i.e. indepen-
dent of output current. This will force gate to source voltage
to be constant and thus ensuring the unity voltage gain.
The other attractive features of FVF include low supply
voltage (VDDmin = VGS2 ? VDSSat) [5] requirement, low
static power dissipation and low distortion even at high
frequencies.
The transfer function of FVF can be obtained from the
small signal model, shown in Fig. 1(b). During analytical
formulation of FVF, it has been assumed that source of
each transistor is connected to its substrate and simulations
are also performed on the basis of same assumption.
The notations used in the analysis are as follows: ro1 and
ro2 are the resistances due to channel length modulation
effect, Cgs1 and Cgs2 are the gate to source capacitances,
gm1 and gm2 are the transconductances of M1 and M2
respectively. Rb is the output impedance of the current
source and Vgs2 stands for gate to source voltage of M2.
On applying KCL at nodes (a) and (b) in small signal
model of conventional FVF (Fig. 1(b)), we get
sCgs1ðVout � VinÞ þ gm2Vgs2 � gm1ðVin � VoutÞ
þ ðVout � Vgs2Þro1
þ Vout
ro2
¼ 0 ð1Þ
ðVgs2 � VoutÞro1
þ sCgs2Vgs2 þVgs2
Rbþ gm1ðVin � VoutÞ ¼ 0
ð2Þ
Using Eqs. (1) and (2) the voltage gain Av(s) of FVF is
obtained as
M 2
VDD
RbIb
M 1
Vout
Vin
VSS
Cgs2
vgs2G2
vin
vout
gm2vgs2
gm1vgs1Cgs1
RbS1
D2
ro1
ro2
S2
G1 D1
(a)
(b)
(a) (b)Fig. 1 a Conventional FVF [1].
b Small-signal model of
conventional FVF
AvðsÞ ¼s2Cgs1Cgs2r2
o1ro2Rb þ sro1ro2 Cgs1ðRb þ ro1Þ þ Cgs2gm1ro1Rb
� �þ gm1gm2r2
o1ro2Rb þ gm1r2o1ro2
� �
s2Cgs1Cgs2r2o1ro2Rb þ sro1 Cgs1ro2ðRb þ ro1Þ þ Cgs2Rbðro1 þ ro2Þ þ Cgs2gm1ro1ro2Rb
� �þ gm1gm2r2
o1ro2Rb þ gm1r2o1ro2 þ gm2ro1ro2Rb þ ro1Rb þ ro1ðro1 þ ro2Þ
ð3Þ
280 Analog Integr Circ Sig Process (2012) 72:279–288
123
Assuming ro1 = ro2 = ro and Cgs1 = Cgs2 = Cgs in
Eq. (3) and after simplifying it, we get
Using the assumptions gmxRb � 1 and gmxro � 1 (where,
x = 1, 2) in Eq. (4) then, transfer function is reduced to
AvðsÞ ¼s2 þ s Rbþroð Þ
CgsroRbþ gm1
Cgs
� �n oþ gm1gm2
C2gs
� �
s2 þ s Rbþroð ÞCgsroRb
þ gm1
Cgs
� �n oþ gm1gm2
C2gs
� �þ Rbþ2ro
C2gsro
2Rb
� �
ð5Þ
Also,
Rb þ roð ÞCgsroRb
þ gm1
Cgs
� ¼ Rb þ ro þ gm1roRb
CgsroRbffi gm1
Cgs
� ð6Þ
Finally,
AvðsÞ ¼s2 þ s gm1
Cgs
� �þ gm1gm2
C2gs
� �
s2 þ s gm1
Cgs
� �þ gm1gm2
C2gs
� �þ Rbþ2ro
C2gsro
2Rb
� � ð7Þ
It can be expressed as
AvðsÞ ¼s2 þ a1sþ a2
s2 þ a1sþ ða2 þ Da2Þð8Þ
where a1 ¼ ðgm1=CgsÞ, a2 ¼ ðgm1gm2=C2gsÞ and Da2 ¼
ðRb þ 2roÞ=C2gsr
2oRb
n o
From Eq. (8) the zeros and poles of the conventional
FVF are found to be
Z1;2 ¼�a1
21�
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1� 4a2
a21
� s" #
ð9Þ
P1;2 ¼�a1
21�
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1� 4a2 þ Da2ð Þ
a21
� s" #
ð10Þ
From Eq. (7) the -3 dB frequency is given by
xo ¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2gm1gm2
C2gs
!
� gm1
Cgs
� 2
�2Rb þ 2ro
C2gsr
2oRb
!( )vuut ð11Þ
It is shown in [1] that the output impedance of
conventional FVF is
ZOUT ¼1
gm1gm2roð12Þ
In this work the FVF cell is modified to achieve
extremely large bandwidth and very low output impedance
by using a resistor in the feedback path, which is discussed
and analyzed in the next section.
3 Proposed flipped voltage follower
3.1 Circuit implementation
The circuit implementation of the proposed FVF is shown
in Fig. 2(a). The introduction of a resistor (R) in the
feedback path, between drain terminal of M1 and gate
terminal of M2, will increase the impedance of feedback
path which causes delaying of current flow in the feedback
path. This increased current initially charges the output
parasitic capacitance and hence the rise-time at the output
node will reduce. This method of reducing the delay time
and hence increasing the bandwidth with the help of a
resistance is called resistive compensation.
3.2 Analysis of transfer function
The small-signal model of proposed FVF is shown in
Fig. 2(b). In the analysis, R stands for the resistance which
is employed in the feedback path of the FVF and Vd1 is the
voltage at the drain terminal of M2. The transfer function
of new FVF is obtained by applying KCL at nodes a, b and
c in the small-signal model shown in Fig. 2(b). On
applying KCL at nodes a, b and c, we get
sCgs1ðVout � VinÞ þ gm2Vgs2 � gm1ðVin � VoutÞ
þ ðVout � Vd1Þro1
þ Vout
ro2
¼ 0 ð13Þ
ðVd1 � VoutÞro1
þ ðVd1 � Vgs2ÞR
þ Vd1
Rbþ gm1ðVin � VoutÞ ¼ 0
ð14Þ
AvðsÞ ¼s2 þ s Rbþroð Þ
CgsroRbþ gm1
Cgs
� �n oþ gm1gm2
C2gs
� �þ gm1
C2gsRb
� �
s2 þ s Rbþroð ÞCgsroRb
þ 2Cgsro
� �þ gm1
Cgs
� �n oþ gm1gm2
C2gs
� �þ gm2
C2gsro
� �þ gm1
C2gsRb
� �þ Rbþ2ro
C2gsr
2oRb
� � ð4Þ
Analog Integr Circ Sig Process (2012) 72:279–288 281
123
ðVgs2 � Vd1ÞR
þ sCgs2Vgs2 ¼ 0 ð15Þ
On solving the above equations, the voltage gain Av(s) is
found to be
By choosing ro1 = ro2 = ro and Cgs1 = Cgs2 = Cgs and
simplification of Eq. (16), on the basis of assumptions
taken in Eq. (5), will lead to
We can write Eq. (17) as
Vout
Vin
V
(a) (b)
DD
RbIb
VSS
R
M 1
M 2
(b) G2
Cgs2
vd1 D1
vin
vout
gm2vgs2
gm1vgs1 Cgs1
Rb S1
D2
ro1
ro2
S2
G1
R
vgs2
(a)
(c)
Fig. 2 a Proposed FVF.
b Small-signal model of
proposed FVF
AvðsÞ ¼s2Cgs1Cgs2ro1ro2 RðRb þ ro1Þ þ Rbro1f g þ sro1ro2 Cgs1ðRb þ ro1Þ þ Cgs2gm1ro1ðRb þ RÞ
� �þ gm1gm2r2
o1ro2Rb þ gm1r2o1ro2
� �
s2Cgs1Cgs2ro1ro2 RðRb þ ro1Þ þ Rbro1f g þ sro1 Cgs1ro2ðRb þ ro1Þ þ Cgs2gm1ro1ro2ðRb þ RÞ þ Cgs2RRb
� �þ gm1gm2r2
o1ro2Rb þ gm1r2o1ro2 þ gm2ro1ro2Rb
� �
ð16Þ
AvðsÞ ¼s2 RðRb þ roÞ þ Rbrof g þ s Rbþroð Þ
Cgsþ gm1roðRbþRÞ
Cgs
� �n oþ gm1gm2roRb
C2gs
� �
s2 RðRb þ roÞ þ Rbrof g þ s Rbþroð ÞCgsþ gm1roðRbþRÞ
Cgs
� �þ RRb
Cgsro
� �n oþ gm1gm2roRb
C2gs
� � ð17Þ
AvðsÞ ¼s2 þ 1
R Rbþroð ÞþRbrof g s Rbþroð ÞCgsþ gm1roðRbþRÞ
Cgs
� �n oþ gm1gm2roRb
C2gs
� �h i
s2 þ 1R Rbþroð ÞþRbrof g s Rbþroð Þ
Cgsþ gm1roðRbþRÞ
Cgs
� �þ RRb
Cgsro
� �n oþ gm1gm2roRb
C2gs
� �h i ð18Þ
282 Analog Integr Circ Sig Process (2012) 72:279–288
123
If we assume gm1R� 1 and gm1ro � 1 then,
ðRb þ roÞCgs
þ gm1roðRb þ RÞCgs
�
¼ 1
CgsRb þ ro þ gm1roðRb þ RÞ½ � ffi gm1roðRb þ RÞ
Cgs
�
ð19Þ
Using Eq. (19) in Eq. (18), we get
The transfer function can be expressed as
AvðsÞ ¼s2 þ b1sþ b2
s2 þ ðb1 þ Db1Þsþ b2
ð21Þ
where, b1 ¼ gm1roðRbþRÞCgs R Rbþroð ÞþRbrof g
� �, Db1 ¼ RRb
Cgsro R Rbþroð ÞþRbrof g
� �
and b2 ¼ gm1gm2roRb
C2gs R Rbþroð ÞþRbrof g
� �
The zeros and poles of the proposed FVF are given by
Z1;2 ¼�b1
21�
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1� 4b2
b21
� s" #
ð22Þ
P1;2 ¼ �b1 þ Db1
2
� 1�
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1� 4b2
ðb1 þ Db1Þ2
!vuut
2
4
3
5
ð23Þ
From Eq. (20) the -3 dB frequency of proposed FVF is
given by
On comparing Eqs. (10) and (23) it is obvious that in
case of modified FVF, the poles of transfer function have
moved apart as compared to the earlier case and this sep-
aration can be controlled by the feedback resistor R.
Equations (11) and (24) are justifying that there is an
increment in the -3 dB frequency of the conventional FVF
cell by using resistive compensation technique.
3.3 Analysis of output impedance
The output impedance of proposed FVF is calculated by
using conventional method that is connecting a test voltage
source at the output and measuring the current flowing into
the circuit, while the input source is grounded. The circuit
for output impedance calculation is shown in Fig. 3.
The output impedance of proposed FVF is found to be
ZOUT ¼ro2Rb
gm1ro1Rb þ gm1gm2ro1ro2ðRb þ RÞ ð25Þ
By using ro1 = ro2 = ro, and after simplification the
output impedance is modified as
ZOUT ¼Rb
gm1Rb þ gm1gm2roðRb þ RÞ ð26Þ
It can be observed from Eq. (26) that by increasing value
of feedback resistance R, the output impedance of the
improved FVF will decrease. But the value of R can not be
taken arbitrarily large as the decrement in output
impedance is limited by peaking in the frequency response.
4 Application of proposed fvf (in a current mirror)
Current mirrors are widely used building blocks in many
applications. As a building block in an analog signal
processing circuit the attributes of a current mirror are
that, it should have accurate current copy, wide input and
output current swings, high output impedance and high
linearity. The key issues in the design of a current mirror
are the improvement of high-frequency characteristic and
the realization of high-output impedance. Since conven-
tional current mirrors have high power dissipation and
AvðsÞ ¼s2 þ 1
R Rbþroð ÞþRbrof g s gm1roðRbþRÞCgs
� �þ gm1gm2roRb
C2gs
� �h i
s2 þ 1R Rbþroð ÞþRbrof g s gm1roðRbþRÞ
Cgs
� �þ RRb
Cgsro
� �n oþ gm1gm2roRb
C2gs
� �h i ð20Þ
xo ¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2gm1gm2roRb
C2gs R Rb þ roð Þ þ Rbrof g
!
� gm1roðRb þ RÞCgs R Rb þ roð Þ þ Rbrof g
� 2
þ RRb
Cgsro R Rb þ roð Þ þ Rbrof g
� 2
þ2gm1roðRb þ RÞ
Cgs R Rb þ roð Þ þ Rbrof g
� RRb
Cgsro R Rb þ roð Þ þ Rbrof g
� ( )vuut
ð24Þ
Analog Integr Circ Sig Process (2012) 72:279–288 283
123
low bandwidth, they are not reliable to be used in low-
voltage wideband circuit. Hence it is needed to design
new current mirrors to meet the requirements of low-
voltage wideband analog and mixed signal processing
circuits.
Gupta et al. [13] have enhanced the bandwidth of FVF
based current mirror [4] by introducing passive [8] and
active resistance [15] at the gate of primary transistor
pair of the current mirror in [13]. There was approxi-
mately 200 MHz improvement in the bandwidth of pas-
sively and actively compensated current mirrors. In this
paper the proposed FVF cell is used in place of con-
ventional one in the low voltage current mirrors sug-
gested in [13]. The conventional current mirror using
FVF [4], passive-compensated current mirror [13] and
modified current mirror using proposed FVF cell are
shown in Fig. 4(a–c) respectively. Figure 5(a) shows the
active-compensated current mirror suggested in [13] and
the modified version of Fig. 5(a) is shown in Fig. 5(b).
The simulation results of all the circuits are discussed in
the next section.
5 Simulation results
The proposed circuits are designed in TSMC 0.18-lm
CMOS technology and simulated with Spectre with supply
voltage of 1.5 V. The FVF cells are simulated by using
1 mA bias current and sizes of transistors M1 and M2 are
(36/1.2-um) and (24/1.2-um) respectively.
Figure 6 shows the frequency response of conventional
FVF and proposed FVF cell. The bandwidth of proposed
FVF cell increases from 5.058 to 7.1186 GHz when 1.8 K
resistance is used in the feedback path. The frequency
response depends on the value of feedback resistance R.
After a certain value of R, peaking is observed and
approximately 1.7 BWER is obtained at 6 K. The -3 dB
frequencies of conventional and proposed FVF are
numerically evaluated from Eqs. (11) and (23). For
iout
gm1vgs1 o1
Rb
R vgs2
G2 D1
vd1
± gm2vgs2
r
ro2
D2
S1
S2
vout
Fig. 3 Small-signal model of proposed FVF for output impedance
calculation
M8
VSS
M7
M4 M5
M6
M3
V(a)
(c)
(b)
DD
VBIAS
IIN IOUT
IOUT
M3
M6
M8
VDD
VBIAS
IIN
M1 M2
M1 M2
M5 M4
VSS
M7
RCOMP
VBIAS
IIN
M2 M3
VSS
VDD
IOUT
M1
M5 M6 M4
8M 7M
RCOMP
R
Fig. 4 a Current mirror using conventional FVF [4]. b Passive-
compensated current mirror [13]. c Modified current mirror with
proposed FVF cell (RCOMP and R are compensating and feedback
resistance respectively)
284 Analog Integr Circ Sig Process (2012) 72:279–288
123
conventional FVF and proposed FVF (with R = 1.8 K),
the errors between the simulated and theoretically evalu-
ated -3 dB frequencies are found to be 3.81 % and
-4.81 % respectively (Table 1).
An improvement of 1.2 GHz in bandwidth is achieved
by using proposed FVF in passive-compensated current
mirror [13]. However maximum BWER is 1.6 when
peaking is observed in the frequency response. These fre-
quency responses are shown in Fig. 7. The frequency
response of actively compensated current mirror by using
improved FVF cell is shown in Fig. 8. The BWER of
improved active-compensated current mirror is 1.2. The
simulation results are summarized in Table 2.
The variations of output impedance of conventional and
improved FVF cells with frequency are shown in Fig. 9. It
can be observed from Fig. 9 that output impedance of
proposed FVF is lower as compared to the conventional
FVF.
M6
IIN
M2 3M1M
(a)
(b)
VDD
M9
M10
IOUTItu
M4 M5
M7 MCOMP
VSS
Itu
VBIAS
VDD
11M8M7MMCOMP
VSS
Itu
M2 3M1MM9
M4 M5
M8 M11
M6 M10
IIN IOUT
Itu
VBIAS
R
Fig. 5 a Active-compensated current mirror [13]. b Modified active-
compensated current mirror with proposed FVF cell (MCOMP is the
transistor used for active-compensation)
Fig. 6 Frequency responses of
FVF cells
Table 1 Simulated and theoretical bandwidth comparison of con-
ventional and proposed FVF cells
Flipped voltage follower (FVF)
Simulated circuit Conventional Proposed FVF
(R = 1.8 K)
Bandwidth in GHz (simulation) 5.058 7.118
Bandwidth in GHz (theoretical) 5.259 6.787
Error (%) 3.82 -4.87
Basic transistor parameters are: (W/L) 1 = (36/1.2), (W/L) 2 = (24/
1.2) and Ib = 1 mA
Analog Integr Circ Sig Process (2012) 72:279–288 285
123
Fig. 8 Frequency responses of
active-compensated current
mirror
Fig. 7 Frequency responses of
passive-compensated current
mirror
Table 2 Bandwidth of various simulated circuits
Simulated
Circuits
Flipped voltage follower (FVF) Current mirror (CM)
Conventional Proposed
FVF
(without
peaking)
Proposed
FVF
(with
peaking)
Conventional Passively
compensated
CM
Passively
compensated CM
with proposed FVF
cell (without
peaking)
Passively
compensated CM
with proposed
FVF cell (with
peaking)
Actively
compensated
CM
Actively
compensated
CM with
proposed FVF
cell
Bandwidth
in GHz
5.058 7.11865 8.377 4.037 4.5 5.206 6.395 4.427 5.02
286 Analog Integr Circ Sig Process (2012) 72:279–288
123
6 Conclusion
In this paper, a high-speed FVF cell is developed by using
resistive compensation technique. The bandwidth of mod-
ified FVF increases from 5.05 to 7.1 GHz as compared to
conventional FVF. It has been shown by small-signal
analysis that -3 dB frequency of proposed FVF cell
increases and at the same time its output impedance
reduces. This improvement in bandwidth is dependent on
the value of resistor which is added in the feedback path.
The application of proposed FVF cell in the low voltage
current mirror has also been investigated.
References
1. Carvajal, R., Ramirez-Angulo, J., Lopez Martin, A., Torralba, A.,
Galan, J., Carlosena, A., et al. (2005). The flipped voltage fol-
lower: A useful cell for low voltage low power circuit design.
IEEE Transactions on Circuits and Systems I, 52(7), 1276–1279.
doi:10.1109/TCSI.2005.851387.
2. Sakul, C., & Dejhan, K. (2010). Squaring and square-root circuits
based on flipped voltage follower and applications. InternationalJournal of Information Systems and Telecommunication Engi-neering, 1, 19–24.
3. Ramirez-Angulo, J., Carvajal, R., Torralba, A., Galan, J., Vega-
Leal, A. P., et al. (2002). Low-power low-voltage analog
electronic circuits using the flipped voltage follower. IEEEIndustrial Electronics, 4, 1327–1330. doi:10.1109/ISIE.2002.10
25983.
4. Koliopoulos, C., & Psychalinos, C. (2007). A comparative study
of the performance of the flipped voltage follower based low
voltage current mirror. IEEE International Symposium on Sig-nals, Circuits and Systems, 1, 1–4. doi:10.1109/ISSCS.2007.
4292650.
5. Lai, S., Zhang, H., Chen, G., & Xu, J. (2008). An improved
source follower with wide swing and low output impedance. In
IEEE Asia Pacific conference on circuits and systems (pp.
814–818). doi:10.1109/APCCAS.2008.4746147.
6. Ramirez-Angulo, J., Gupta, S., Padilla, I., Carvajal, R. G.,
Torralba, A., Jimenez, M., et al. (2005). Comparison of con-
ventional and new flipped voltage structures with increased input/
output signal swing & current sourcing/sinking capabilities. In
48th IEEE midwest symposium on circuits and systems (Vol. 2,
pp. 1151-1154). doi:10.1109/MWSCAS.2005.1594310.
7. Haga, Y., & Kale, I. (2009). Bulk-driven flipped voltage follower.
IEEE International symposium on circuits and systems (pp.
2717–2720). doi:10.1109/ISCAS.2009.5118363.
8. Voo, T., & Toumazou, C. (1995). High-speed current mirror
resistive compensation technique. IEE Electronics Letters, 31(4),
248–250. doi:10.1049/el:19950207.
9. Comer, D. J., Comer, D. T., Perkins, J. B., Clark, K. D., & Genz,
A. P. C. (2006). Bandwidth extension of high-gain CMOS stages
using active negative capacitance. In:13th IEEE internationalconference on circuits and systems, electronics (pp. 628–631)
doi:10.1109/ICECS.2006.379867.
10. Shekhar, S., Walling, J. S., & Allstot, D. J. (2006). Bandwidth
extension techniques for CMOS amplifiers. IEEE Journal ofSolid-State Circuits, 41(11), 2424–2439. doi:10.1109/JSSC.
2006.883336.
11. Sansen, W., & Chang, Z. Y. (1990). Feedforward compensation
techniques for high-frequency CMOS amplifiers. IEEE Journal ofSolid-State Circuits, 25(6), 1590–1595. doi:10.1109/4.62197.
12. Thomas, H. Lee. (2004). The design of CMOS radio-frequencyintegrated circuits (2nd ed.). UK: Cambridge University Press.
13. Gupta, M., Aggarwal, P., Singh, P., & Jindal, N. K. (2009). Low
voltage current mirrors with enhanced bandwidth. Analog Inte-grated Circuits and Signal Processing, 59(1), 97–103. doi:
10.1007/s10470-008-9241-2.
14. Sedra, A. S., & Smith, K. C. (2005). Microelectronics circuits(5th ed.). New York: Oxford University Press.
15. Voo, T., & Toumazou, C. (1996). Precision temperature stabi-
lised tunable CMOS current-mirror for filter applications. IEEElectronics Letters, 32(2), 105–106. doi:10.1094/el:19960069.
Fig. 9 Variations of output
impedance with frequency of
conventional FVF and proposed
FVF
Analog Integr Circ Sig Process (2012) 72:279–288 287
123
Maneesha Gupta B.E. in
Electronics and Communication
Engineering from Government
Engineering College, Jabalpur
in 1981, M.E. in Electronics and
Communication Engineering
from Government Engineering
College, Jabalpur in 1983 and
Ph.D. in Electronics Engineer-
ing (Analysis, Synthesis and
Applications of Switched
Capacitor Circuits) from Indian
Institute of Technology, Delhi
in 1990. She is working as
Professor in the Division of
Electronics and Communication Engineering of the Netaji Subhas
Institute of Technology, New Delhi from 2008. She is working in the
areas of Switched Capacitors Circuits and low voltage design tech-
niques. She has co-authored over 30 research papers in the above
areas in various international/national journals and conferences.
Urvashi Singh received the
M.Sc. degree in electronics and
communication from CSJM
University and M.Tech. degree
in VLSI design from MITS
University, India in 2007 and
2009 respectively. During
2009–2010, she was a lecturer
in GLA University, Mathura,
India. She is currently working
toward the Ph.D. degree at
Netaji Subhas Institute of
Technology (NSIT), New Delhi,
India. Since August 2010, she
has been with NSIT, where her
research focuses on design of analog integrated circuits for broadband
applications. She is also working on analog circuit characterization at
both schematic and layout level. She has thorough experience on
working with various industry-standard VLSI design tools (Mentor
Graphics TC status; Cadence Virtuoso).
288 Analog Integr Circ Sig Process (2012) 72:279–288
123
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