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Order Number C14071
TinyRISCBDMR4103Evaluation Board
Users GuideJuly 2000
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2/100ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB15-000161-00, First Edition (July 2000). This document describes
revision A of the LSI Logic Corporation TinyRISC
BDMR4103 Evaluation BoardUsers Guide and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products
described herein at any time without notice. LSI Logic does not assume any
responsibility or liability arising out of the application or use of any product
described herein, except as expressly agreed to in writing by LSI Logic; nor does
the purchase or use of a product from LSI Logic convey a license under any
patent rights, copyrights, trademark rights, or any other of the intellectual
property rights of LSI Logic or third parties.
Copyright 2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, TinyRISC, and MiniRISC are registered trademarks
and SerialICE is a trademark of LSI Logic Corporation. All other brand and
product names may be trademarks of their respective companies.
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3/100Preface iii
Preface
This book is the primary reference and users guide for the TinyRISC
BDMR4103 Evaluation Board. This guide describes the basic features ofthe evaluation board, including hookup procedures and system
configuration. For additional information that relates to the board and itscomponents, refer to Related Publications, onpage iv.
Audience
This document assumes that you are familiar with microprocessors andrelated support devices. The people who benefit from this book are:
Engineers and managers who are evaluating the LR4103microprocessor for possible use in a system
Engineers who are designing the microprocessor into a system
Organization
This document has the following chapters:
Chapter 1,Introduction,gives an overview of the BDMR4103Evaluation Board and describes its features.
Chapter 2,Installation Procedures,explains how to connect powerto the BDMR4103 Evaluation Board, go through a quick board checkprocedure, and install jumpers.
Chapter 3,Board Design and Layout,describes the design andlayout of the BDMR4103 Evaluation Board.
Chapter 4,PAL Equations,provides the PAL equations for theBDMR4103 Evaluation Board.
Chapter 5,Schematics,contains the schematics for the BDMR4103Evaluation Board.
Chapter 6,Bill of Materials,lists the bill of materials for the
BDMR4103 Evaluation Board.
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Related Publications
TinyRISC EZ4103 EasyMACRO Microprocessor and FBusMacro
Technical Manual,LSI Logic Corporation, Order Number C14068.
TinyRISC
LR4103 Microprocessor Technical Manual,LSI LogicCorporation, Document Number DB14-000081-00.
TinyRISC BDMR4103 Evaluation Kit Getting Started, LSI Logic
Corporation, Document Number DB15-000095-00.
MIPS PROM Monitor and C Run-Time Library Users Guide, LSI Logic
Corporation, Order Number C14017.A.
The C Programming Language, 2nd edition 1988, by B Kerringhan and
D. Ritchie, Prentice Hall.
PC16550D Universal Asynchronous Receiver Transmitter with FIFOs,
National Semiconductor Corp.
Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
for PCI Local Bus Product,Advanced Micro Devices.
DS1307/DS1308 64 X 8 Serial Real Time Clock, DALLAS
Semiconductor.
Conventions Used in This Manual
The wordassertmeans to drive a signal true or active. The word
deassertmeans to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix 0xfor example,
0x32CF. Binary numbers are indicated by the prefix 0bfor example,
0b0011.0010.1100.1111.
All signals with names ending in N are active LOW; otherwise, signals
are active HIGH.
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Abbreviations
The following abbreviations are used in this manual. Note that
abbreviated signal names are not listed:
ASE Application Specific Extension
CPLD Complex Programmable Logic Device
DIMM Dual Inline Memory Module
DIN Deutsches Institut fr Normung
DIP Dual In-line Package
DMA Direct Memory Access
DRAM Dynamic Random Access Memory
EDO Extended Data Output
EEPROM Electronically Erasable Programmable Read Only Memory
EJTAG Enhanced Joint Test Action Group
EPROM Erasable Programmable Read Only Memory
FAPI FBus Advanced Peripheral Interface
FBM FBusMACRO
FET Field Effect Transistor
ICE In-Circuit Emulation
ISA Instruction Set Architecture
ISP In-System Programmable
JEDEC Joint Electrical Device Engineering Committee
JTAG Joint Test Action Group
k Kilo-ohm
Kbyte Kilobyte
LED Light Emitting Diode
M Megaohm
Mbyte Megabyte
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PAL Programmable Array Logic
PBGA Plastic Ball Grid Array
PCI Peripheral Component Interface
PLCC Plastic Leaded Chip Carrier
PLD Programmable Logic Device
PLL Phase-Locked Loop
PROM Programmable Read Only Memory
QSOP Quarter Size Outline Package
R/A Right Angle
RTC Real Time Clock
SDRAM Synchronous DRAM
SOIC Small Outline Integrated Circuit
SOJ Small Outline J-bend
SPST Single-Pole Single-throw
SRAM Static RAM
SSOP Shrink Small Outline Package
TAP Test Access Port
TP Test Point
TQFP Thin Quad Flat Package
TSOP Thin Small Outline Package
TSSOP Thin Shrink Small Outline Package
UART Universal Asynchronous Receiver Transmitter
UHS Ultra High Speed
F Microfarad
Ohm
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Contents
Chapter 1 Introduction
1.1 Product Summary 1-1
1.2 Product Features 1-2
1.3 Debug Environment Overview 1-3
1.3.1 PROM-Based Debug Environments 1-3
1.3.2 EJTAG Debug Environment 1-3
1.4 Block Diagram 1-4
Chapter 2 Installation Procedures
2.1 Quick Check 2-1
2.1.1 Checking the Board 2-2
2.1.2 Resolving Problems 2-4
2.2 Jumper Settings 2-5
2.2.1 Select PLLN (JP1) 2-9
2.2.2 Divide C1 (JP2) and Divide C0 (JP3) 2-9
2.2.3 Divide A1 (JP4) and Divide A0 (JP5) 2-10
2.2.4 Endian Selection (JP6) 2-11
2.2.5 PLL Range Select (JP7) 2-11
2.2.6 Alternate Boot Program Selection (JP8) 2-11
2.2.7 Boot Device Selection (JP9) 2-11
2.2.8 Connect 3.3 V Power (JP10) 2-12
2.2.9 Connect CPU I/O Ring Power (JP11) 2-12
2.2.10 Connect VDDCore Power (JP12) 2-12
2.2.11 Clock Source Selection (JP14) 2-13
2.2.12 SerialICE-1 Input Data Selection (JP15) 2-13
2.2.13 SerialICE-1 Clock Selection (JP16) 2-13
2.2.14 EDO/SDRAM Selection (JP17) 2-13
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Chapter 3 Board Design and Layout
3.1 Board Layout 3-2
3.2 External Interfaces 3-3
3.2.1 Expansion Connector (J2) 3-4
3.2.2 DIMM Connector (J3) 3-73.2.3 Serial Port Connector (J10) 3-9
3.2.4 RS-232 Serial Connector for SerialICE-1
Debug Interface(J9) 3-10
3.2.5 SerialICE-1 Connector (J8) 3-11
3.2.6 Ethernet Connector (J7) 3-12
3.2.7 EJTAG Connectors 3-13
Overview of EJTAG Functions 3-13
EJTAG Connector (J4) 3-13
EJTAG Connector (J5) 3-153.2.8 PAL Programming Connector (J11) 3-18
3.2.9 Power Supply Connector (J1) 3-19
3.3 Indicators 3-20
3.3.1 Power LED 3-20
3.3.2 Ethernet LEDs 3-21
3.3.3 Debug LED 3-21
3.3.4 7-Segment Display 3-22
3.4 System Memory 3-23
3.4.1 Synchronous DRAM Dual Inline MemoryModule (SDRAM DIMM) 3-23
3.4.2 Static RAM (SRAM) 3-23
3.4.3 Boot EPROMs 3-23
3.5 Memory Map 3-24
3.6 Two-Wire Serial Bus Peripheral Devices 3-26
3.6.1 Real-Time Clock (RTC) 3-26
3.6.2 EEPROM 3-28
3.6.3 Serial Presence Detect (SPD) 3-28
3.6.4 LR4103 Interrupts 3-293.7 Device Registers 3-29
3.7.1 PC16550D UART Registers 3-30
3.7.2 Am79C970A Ethernet Controller 3-31
Chapter 4 PAL Equations
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Chapter 5 Schematics
5.1 Microprocessor and Clock Circuitry 5-2
5.2 ROMs, SRAMs, and Address Latches 5-4
5.3 Ethernet and DRAM Circuitry 5-6
5.4 Miscellaneous Circuitry and Connectors 5-85.5 Expansion Connector and Boot Device Selection
Circuitry 5-10
5.6 Power and Reset Circuitry 5-12
5.7 EJTAG Connectors 5-14
Chapter 6 Bill of Materials
Customer Feedback
Figures
1.1 BDMR4103 Block Diagram 1-4
2.1 View of the BDMR4103 Quick Check Components 2-2
2.2 Jumper Positions 2-5
2.3 Jumper Locations on the BDMR4103 Evaluation Board 2-6
3.1 BDMR4103 Evaluation Board Layout 3-2
3.2 Expansion Connector 3-5
3.3 DIMM Connector Pin Numbers 3-73.4 Serial Port Connector 3-9
3.5 RS-232 SerialICE-1 Connector 3-10
3.6 SerialICE-1 Connector 3-11
3.7 Ethernet 10BASE-T Connector 3-12
3.8 EJTAG Connector J4 3-14
3.9 EJTAG Connector J5 3-15
3.10 PAL Programming Connector 3-18
3.11 Power Supply Connector 3-19
3.12 Indicator Positions 3-203.13 Ethernet Indicator Positions 3-21
3.14 7-Segment Display 3-22
5.1 Microprocessor and Clock Circuitry 5-3
5.2 ROMs, SRAMs, and Address Latches 5-5
5.3 Ethernet and DRAM Circuitry 5-7
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5.4 Miscellaneous Circuitry and Connectors 5-9
5.5 Expansion Connector and Boot Device Selection
Circuitry 5-11
5.6 Power and Reset Circuitry 5-13
5.7 EJTAG Connectors 5-15
Tables
2.1 Default Jumper Settings 2-7
2.2 JP2 and JP3 Jumper Settings 2-10
2.3 JP4 and JP5 Jumper Settings 2-10
2.4 JP9 Jumper Settings 2-12
3.1 Summary of LR4103 Interface Connector Functions 3-3
3.2 Expansion Connector Pin Designations 3-5
3.3 DIMM Connector Pin Assignments 3-8
3.4 Serial Port Connector Pin Assignments 3-9
3.5 RS-232 SerialICE-1 Connector Pin Assignments 3-10
3.6 SerialICE-1 Header Pin Assignments 3-11
3.7 Ethernet Connector Pin Assignments 3-12
3.8 EJTAG Connector J4 Pin Assignment 3-14
3.9 EJTAG Connector J5 Pin Assignments 3-15
3.10 PAL Programming Connector Pin Assignments 3-19
3.11 Ethernet Indicator Functions 3-21
3.12 7-Segment Display Settings 3-22
3.13 Boot EPROM Addressing 3-24
3.14 Physical Memory Map 3-25
3.15 Real-Time Clock Addressing 3-27
3.16 RTC Registers 3-27
3.17 EEPROM Addressing 3-28
3.18 SPD EEPROM Addressing 3-28
3.19 BDMR4103 Interrupts 3-29
3.20 UART Registers 3-30
3.21 Ethernet Controller User Registers 3-31
6.1 BDMR4103 Bill of Materials 6-2
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BDMR4103 Evaluation Board Users Guide 1-1
Chapter 1Introduction
This chapter gives an overview of the BDMR4103 Evaluation Board.
Topics covered in the chapter include:
Section 1.1, Product Summary
Section 1.2, Product Features
Section 1.3, Debug Environment Overview
Section 1.4, Block Diagram
1.1 Product Summary
The BDMR4103 Evaluation Board is designed for use with the LSI Logic
TinyRISC LR4103 reference device. You can use the evaluation board to
Develop application software before (or in parallel with) designing a
system on a chip Evaluate the memory system design price/performance trade-off by
running an actual benchmark program
Together with a PC or UNIX host, the evaluation board provides you with
a complete environment for hardware and software development and
debugging. Access to off-board logic through a 150-pin AMP expansion
connector and the capability to download software through
communication ports allows you to verify the functionality of your system
before protoyping the hardware.
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1.2 Product Features
The features of the BDMR4103 Evaluation Board are:
A TinyRISC LR4103 processor that provides a 120 MHz evaluation
target
128 Kbytes of on-board SRAM
A plug-in DRAM DIMM (dual inline memory module); the DIMM
connector accepts any standard 100-pin JEDEC (Joint Electrical
Device Engineering Committee) DIMM; a 16 Mbyte SDRAM DIMM is
supplied with board
1 Mbyte of FLASH EPROM; the EPROM contains a powerful monitor
and debugger for downloading and debugging user programs
A 1 Kbyte EEPROM for the configuration parameters
Real-Time Clock (RTC)
An on-board 16550 UART (universal asynchronous
receiver/transmitter) with one RS-232C serial port
SerialICE-1 on-chip debugging capabilities
EJTAG debugging capabilities
A 7-segment display for status display and debug use
An on-board AM79C970A PCnet Ethernet controller with a10BASE-T interface
A 150-pin AMP expansion connector that provides easy access to
the evaluation board
Support for 3.3 V devices
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1.3 Debug Environment Overview
The BDMR4103 evaluation board offers debug support through a PROM
monitor-based debug environment (PMON and SerialICE-1 debug
interface) and EJTAG, a nonintrusive on-chip MIPS standard debug
environment.
For more information on setting up the three debug environments, please
refer to theTinyRISC BDMR4103 Evaluation Kit Getting Started.
1.3.1 PROM-Based Debug Environments
PMON is a conventional assembly-level PROM-based debug monitor.
PMON supports stand-alone operation and operation as the backend for
a source-level debugger. The principal disadvantage of PMON is
memory usage. PMON takes up approximately 300 Kbytes of target
memory.
The BDMR4103 evaluation board is shipped with PMON stored in the
lower 512 Kbyte region of the FLASH memory at U12. Communication is
done through the RS-232 serial port and downloaded through the
RS-232 connector at J9 or the Ethernet connector at J7.
The BDMR4103 evaluation board also offers the SerialICE-1 debug
environment. The SerialICE-1 debug interface provides the same debug
features as PMON, but does it with less than 1 Kbyte of target memory.Use the SerialICE-1 debug interface with either an assembly-level or a
source-level debugger. Communication and download is provided
through the SerialICE-1 RS-232 serial port (J9) or the TTL-level 10-pin
header (J8).
1.3.2 EJTAG Debug Environment
EJTAG (Extended Joint Test Action Group) is a standard on-chip MIPS
debugging environment. EJTAG does not require target system memory.
To use EJTAG, the user needs to set up the memory map for the
BDMR4103 evaluation board since it has a programmable memory
controller. The user can either accomplish this in application code or use
the sample boot-up code provided in the upper 512 Kbyte region of the
FLASH EPROM memory. The user must run this boot-up code before
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downloading application programs to the evaluation board using an
assembly-level or source-level debugger. Communication and download
occurs through the EJTAG connector at J4.
1.4 Block DiagramFigure 1.1shows a high level block diagram of the BDMR4103 evaluation
board.
Figure 1.1 BDMR4103 Block Diagram
LR4103Microprocessor
Address Bus
Data Bus
SerialICE-1 Circuitry
EJTAGConnectorsfor Debug
128 Kbytes
SRAM
1 MbyteFLASH
1 Mbyte
EPROM
16 Mbytes
SDRAM
16550
UART
Ethernet
Control
150-Pin
10BASE-TEthernet Connector
SerialPort
7-SegmentDisplay
EPROM
ExpansionConnector
EEPROM
RTC
I2C Devices
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BDMR4103 Evaluation Board Users Guide 2-1
Chapter 2Installation Procedures
This chapter describes the installation procedure for the BDMR4103
Evaluation Board. Topics covered in the chapter include:
Section 2.1, Quick Check
Section 2.2, Jumper Settings
2.1 Quick Check
Figure 2.1shows a simplified view of the BDMR4103 board with the
components referenced in this section.Figure 3.1, onpage 3-2, shows a
more detailed view of the board. Major connectors and the LR4103
processor are shown inFigure 2.1to provide an orientation.
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Figure 2.1 View of the BDMR4103 Quick Check Components
2.1.1 Checking the Board
You can check the evaluation board by booting the PROM monitor
program. The BDMR4103 board is shipped with a monitor program
burned into the AM29F080 FLASH EPROM at location U12.
Use the following procedure to check the board:
J9 J10
SerialICE-1 RS232 Port Serial Port
LR4103 Reference Device
U1
Microprocessor
U16
U36
U12FLASHEPROM
U25EPROM
U5
U6
J2
J1
U13
C1B1A1
C50B50A50
PowerSupply
Connector
SI Oscillator
1 Mbyte
1 Mbyte
Power
LEDmprocOSC
mprocCrystal Core
Power
3.3 V
D5
1 Kbyte EEPROM
X1
100-Pin DIMM ConnectorJ3
ResetButton
PinsPins
1
51
50
100
JP9JP8JP7JP6JP5JP4JP3JP2JP1
Ethernet
(RJ45) PortJ7
SerialICE-1Header J8
150-Pin DIN Connector
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1. Using a standard RS-232C cable, connect the serial port (J10) to
one of the following:
A terminal console.
A workstation or PC running a terminal emulator program.
Standard VT100-type terminals and PC AT-compatible PCs
operating in VT100 emulation mode are suitable. To emulate a
VT100 terminal on a PC, use the Hyperterminal application in
Microsoft Windows.
Set the terminal software for the following:
9600 baud
8 data bits
no parity
1 stop bit
Section 3.2.3, Serial Port Connector (J10),onpage 3-9describes
the serial port connector.
2. Set the following jumpers: (Refer toFigure 2.3)
Remove JP9 to select the FLASH EPROM at location U12 as the
boot device.
Remove JP8 to select the correct boot program within the
FLASH EPROM.
Remove JP6 to select big-endian addressing mode.3. LSI Logic provides an AC adapter with the BDMR4103 board. Power
from the adapter is supplied to the board by means of the standard
DC power connector at location J1.Figure 2.1shows the position of
the DC connector on the evaluation board.Section 3.2.9, Power
Supply Connector (J1),onpage 3-19, describes the connector.
To apply power to the board, plug the DC power connector on the
AC adapter into the on-board power connector (J1) and plug the
three-pin AC connector on the adapter into main building power. The
power supply provided with the board will operate with AC power inthe range of 100 V240 V, at 50/60 Hz. When power is applied to the
board, the power LED at D5 lights up.
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4. The following events then occur:
The terminal screen displays a banner.
The monitor prompt appears on the screen.
The terminal displays the start-up message.
5. After the start-up message, the monitor displays the followingprompt:
PMON>
This prompt may vary slightly depending on the terminal display type
and settings. When you see the prompt, the system is ready for use.
2.1.2 Resolving Problems
If nothing appears on the screen when you power up the board, check
the following:
1. Is the power adapter plugged into the BDMR4103 board and into the
AC building supply?
2. Is the LED at D5 lit?
3. Is the RS-232C cable correctly installed at location J10?
4. Are the jumpers set for correct operation, as described in
Section 2.1.1, Checking the Board, step2.?
5. If you are using a PC, is it operating in standard VT100 terminal
emulation mode?
If problems persist, contact your LSI Logic sales representative for
further assistance.
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2.2 Jumper Settings
The BDMR4103 board has both 2- and 3-pin jumpers. As shown in
Figure 2.2, the 2-pin jumpers are described as being either in (installed)
or out (not installed), and the 3-pin jumpers are described as being in
positions 12, positions 23, or out.
Figure 2.2 Jumper Positions
All jumpers are identified by a number of the formJPnn(JP1, JP2, and
so forth) on the BDMR4103 board.Figure 2.3onpage 2-6shows the
locations of the jumpers on the evaluation board. Connectors are shown
inFigure 2.3onpage 2-6to provide the proper orientation.Table 2.1on
page 2-7summarizes the jumper functions and indicates the defaults
(factory settings). Sections2.2.1through2.2.14provide more detailed
information about jumper settings.
After performing the Quick Check in Section2.1,disconnect the power
connection from the board and set the jumpers.
1 1 13 3 3
Positions 12 Positions 23 OutOutIn
Two-Pin Jumpers Three-Pin Jumpers
1 2 1 2 2 2 2
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Figure 2.3 Jumper Locations on the BDMR4103 Evaluation Board
J7 J9 J10
U1
JP9JP8JP7JP6JP5JP4JP3JP2JP1
U24
JP17
JP 14
JP16
JP15
JP13JP12
JP11
JP10
J2
JP9 Boot Device Selection
JP4 Divide A1
JP3 Divide Clock 0
JP2 Divide Clock 1
JP1 PLLN Selection
JP8 Alternate Boot Program Selection
JP7 PLL Range Selector
JP6 Endian Selection
JP5 Divide A0
JP14 Clock Source Selection
JP13 VDD Core Voltage Selection
JP12 Connect/ Disconnect
JP11 Connect/Disconnect
JP10 Connect/Disconnect +3 V Power
JP17 Address Line Configuration for SDRAM and EDO DRAM
JP16 SerialICE-1 Clock Selection
JP15 SerialICE-1 Input Data Selection
When installed,these jumperstie the relatedinput to the
microprocessorlow.
LR4103
LR4103Microprocessor
J3
J8
J1
I/O Power
LR4103 Core Power
LR4103
Control PCLK Freq.
Control PBCLK Freq.
3 2 1
3
2
1
3 2 1
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Table 2.1 Default Jumper Settings
Jumper Jumper Name Setting Function Implemented Reference
JP1 Select PLLN In
(Default)Selects the PLL (phase-locked loop) circuitas the clock source for the LR4103.
Section2.2.1,page 2-9
Out Selects the input clock as the clock sourcefor the LR4103.
JP2 andJP3
Divide C[1:0] Default:JP2 InJP3 InSeeTable 2.2
Control the PBCLK frequency.
The default settings select a PBCLKfrequency equal to 1/3 PCLK.
Section2.2.2,page 2-9
JP4 andJP5
Divide A[1:0] Default:JP4 In
JP5 OutSeeTable 2.3
Control the PCLK frequency.
The default settings select a PCLKfrequency equal to 4 x the input clock.
Section2.2.3,
page 2-10
JP6 EndianSelection
Out(Default)
Selects big endian mode. Section2.2.4,page 2-11
In Selects little endian mode.
JP7 PLL RangeSelector
In(Default)
100250 MHz
200500 MHz
Section2.2.5,page 2-11
Out
JP8 Alternate BootProgramSelection
In Inverts the A19 input to the boot device toallow the selection of an alternate bootprogram.
Section2.2.6,page 2-11
Out(Default)
A19 input to the boot device is not inverted.
JP9 Boot DeviceSelection
In Selects the EPROM at U25 as the bootdevice.
Section2.2.7,page 2-11
Out(Default)
Selects the FLASH EPROM at U12 as theboot device.
JP10 Connect 3.3 V In
(Default)Connects 3.3 V power to the onboarddevices.
Section2.2.8,page 2-12
Out Disconnects 3.3 V power from the onboarddevices for test purposes.
(Sheet 1 of 2)
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JP11 Connect CPUPower
In(Default)
Connects the 3.3 V power to the LR4103VDDIO pins.
Section2.2.9,page 2-12
Out Disconnects 3.3 V power from the LR4103VDDIO pins for test purposes.
JP12 Connect VDDCore Power
In(Default)
Connects power to the LR4103 VDD_COREpins.
Section2.2.10,page 2-12
Out Disconnects power from the LR4103VDD_CORE pins for test purposes.
JP14 Oscillator/Crystal ClockSelection
Positions12
Enables the oscillator at U5 to provide theclock input to the LR4103 microprocessor.
Section2.2.11,page 2-13
Positions23
(Default)
Enables the X1 crystal to provide the clockinput to the LR4103 microprocessor.
JP15 SerialICE-1Input DataSelection
Positions12(Default)
The connector at J9 provides the data. Section2.2.12,page 2-13
Positions23
The connector at J8 provides the data.
J16 SerialICE-1Clock Selection
Positions12(Default)
The on-board oscillator (U6) supplies theSerialICE-1 clock.
Section2.2.13,page 2-13
Positions23
The connector at J8 provides theSerialICE-1 clock.
JP17 SDRAM/EDOSelectionControlsAddress Input toDRAM DIMMModule
Positions12(Default)
Address lines are configured for SDRAM. Section2.2.14,page 2-13
Positions23
Address lines are configured for EDO(extended data output) DRAM.
Table 2.1 Default Jumper Settings (Cont.)
Jumper Jumper Name Setting Function Implemented Reference
(Sheet 2 of 2)
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2.2.1 Select PLLN (JP1)
This jumper selects the clock source for the LR4103 microprocessor. The
default setting is installed.
When JP1 is installed, the SELECT_PLLN input to the clock circuitry in
the microprocessor is tied low. This means that on reset, the CLKSEL bitof the SCR2 register in the LR4103 is cleared, thus selecting the PLL
(phase-locked loop) circuit as the clock source for the LR4103.
When JP1 is not installed, the SELECT_PLLN input to the clock circuitry
in the microprocessor is tied high. This means that on reset, the CLKSEL
bit of the SCR2 register in the LR4103 chip is set, thus selecting the
input clock as the clock source for the LR4103.
You can use software at any time to overwrite the CLKSEL bit in the
SCR2 register originally set by this jumper.
2.2.2 Divide C1 (JP2) and Divide C0 (JP3)
These jumpers control the PBCLK frequency. The PBCLK is used as the
clock for the PCI devices connected to the LR4103 microprocessor.
When the jumpers are installed, they tie the inputs to the clock circuitry
in the microprocessor low. When they are not installed, the inputs are
high. On reset, the values set by these jumpers are loaded into the
CLKDC[1:0] bits in the LR4103 SCR2 register. See theTinyRISC
EZ4103 EasyMACRO Microprocessor and FBusMacro Technical Manualfor more information.
The frequency of PBCLK is derived by dividing PCLK by the value of
CLKDC[1:0].Table 2.2shows the CLKDC values provided by the jumper
settings and the clock frequencies derived from these values.
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25/100Jumper Settings 2-11
2.2.4 Endian Selection (JP6)
Jumper JP6 selects between big endian and little-endian addressing
mode. When the jumper is installed, the endian input to the board,
BIG_ENDIANP, is tied low, meaning the board is in little-endian mode.
When the jumper is not installed, BIG_ENDIANP is tied high, causing the
board to function in big-endian mode. The default is big-endian mode.
2.2.5 PLL Range Select (JP7)
When the JP7 jumper is in, the PLL range is 100250 MHz. When the
JP7 jumper is out, the PLL range is 200500 MHz. The PLL runs at twice
the chip clock. The LR4103 is rated for 120 MHz; thus, since
120 x 2 = 240, when the jumper JP7 is in, all valid input speeds are
acceptable.
2.2.6 Alternate Boot Program Selection (JP8)
When installed, JP8 inverts the most significant address bit (A19) input
to the boot device. When JP8 is not installed, A19 is not inverted. The
default is not installed.
This jumper is used to select between two boot programs installed in the
same 1 Mbyte EPROM. Each boot EPROM can accommodate two boot
programs, provided that neither program is larger than 512 Kbytes. The
alternate program should be programmed at address 0x80000 in the
boot EPROM memory. Setting the most significant address bit to the
EPROM HIGH (that is, installing JP8) allows the alternate program to be
selected.
2.2.7 Boot Device Selection (JP9)
The BDMR4103 Evaluation Board accommodates two boot devices: the
EPROM in the DIP socket at location U25, and the onboard FLASH
EPROM at location U12. Jumper JP9 selects between the system boot
devices. The default setting is not installed, causing the system to bootfrom the FLASH EPROM at location U12.
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26/1002-12 Installation Procedures
The PAL at U42 maps the address of the selected boot device to the
MIPS boot vector address (0x1FC0 0000).Table 2.4shows the address
spaces for each boot device.
2.2.8 Connect 3.3 V Power (JP10)
When jumper JP10 is installed, 3.3 V power is supplied to the on-board
devices. When the jumper is not installed, there is no 3.3 V power supply
to these devices. This jumper allows you to measure the current used by
3.3 V devices. To do this, remove the jumper and connect a current
meter between the terminals. The default setting is installed.
2.2.9 Connect CPU I/O Ring Power (JP11)
When jumper JP11 is installed, 3.3 V power is supplied to the LR4103
VDDIO pins. When the jumper is not installed, there is no 3.3 V powersupply to these pins. This jumper allows you to measure the current used
by the LR4103 I/O devices. To do this, remove the jumper and connect
a current meter between the terminals. The default setting is installed.
2.2.10 Connect VDDCore Power (JP12)
When jumper JP12 is installed, power is supplied to the LR4103
VDD_CORE pins. When the jumper is not installed, no power is supplied
to these pins. This jumper allows you to measure the current used by the
LR4103 internal logic. To do this, remove the jumper and connect acurrent meter between the terminals. The default setting is installed.
VDD_CORE provides power to everything on the LR4103 but the I/O
ring.
Table 2.4 JP9 Jumper Settings
JP9Setting
Boot Device(Board Location)
Boot DeviceAddress Space
Alternate Device(Board Location)
Alternate DeviceAddress Space
In EPROM (U25) 0x1FC00000 0x1FCFFFFF
FLASH EPROM(U12)
0x1FD000000X1FDFFFFF
Out(Default)
FLASH EPROM(U12)
0x1FC000000x1FCFFFFF
EPROM (U25) 0x1FD000000X1FDFFFFF
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27/100Jumper Settings 2-13
2.2.11 Clock Source Selection (JP14)
The three-position jumper, JP14, selects the clock input to the LR4103
microprocessor. When this jumper is installed in positions 12, the
oscillator at location U5 supplies the clock. When it is installed in
positions 23, the 25 MHz crystal X1 supplies the clock. The default is
positions 23.
2.2.12 SerialICE-1 Input Data Selection (JP15)
The three-position jumper, JP15, selects the source of the SerialICE-1
input data. When this jumper is installed in positions 12, the data input
comes from connector J9. When the jumper is in positions 23, the data
comes from connector J8. The default is positions 12.
2.2.13 SerialICE-1 Clock Selection (JP16)The three-position jumper, JP16, selects the source of the SerialICE-1
clock. When this jumper is installed in positions 12, the on-board
oscillator at location U6 supplies the clock. The clock supplied should be
16x the desired baud rate. When the jumper is installed in positions
23, the clock signal is supplied from pin 4 of the connector at location
J8. The default is positions 12.
2.2.14 EDO/SDRAM Selection (JP17)
Jumper JP17 enables you to configure the address lines so that you can
use either SDRAM or EDO DRAM devices on the DIMM installed in the
DIMM slot at location J3. This is accomplished by routing the correct
signal to pin 68 of the DIMM. For SDRAM devices, pin 68 is defined as
bank address 0 (BA0); for EDO DRAM devices, pin 68 is defined as
address 11 (A11).
To configure the BDMR4103 board for SDRAM, the jumper is installed in
positions 12, routing address FADDRP27 to pin 68 of the DIMM socket.
To configure the BDMR4103 board for EDO DRAM, the jumper isinstalled in positions 23, routing address FADDRP11 to pin 68. The
default is positions 12.
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30/1003-2 Board Design and Layout
3.1 Board Layout
Figure 3.1shows the placement of the major components on the
BDMR4103 Evaluation Board. Note that the board is not drawn to scale
and the figure should not be used as a manufacturing aid.
Figure 3.1 BDMR4103 Evaluation Board Layout
SeriaIICE-1 RS232 Port Serial PortEthernet 10BASE-T
U10
LR4103 Reference Device
Microprocessor
JP9JP8JP7JP6JP5JP4JP3JP2JP1
U16
U36
U357-Segment
Display
U5
U24
U14U6
U19
AM79C970A
J8
S1
U21
U4
U8
U7
U9
U3
U18
U32 U26 U27 U22 U29 U28
32 Kbytes x 8 SRAMs
PCnetTM
EthernetController
PowerSupply
Connector
ConnectorSerialICE-1
32 Kbytes x 8 SRAMs
EthernetStatus Lights
EthernetTransformer
PAL
SI Oscillator
16550
PowerLED
DebugLED D6
EJTAG
OSC mprocOSC
JP14procCrystal Core
Power
3.3 V
U30
U38 U2
JP13
JP11
Header
I KbyteEEPROM
U13
U30
U17
JP12
JP10
JP17
JP16
JP15
B1Batteryfor Real-Time
X3
J1
J4
J5
J6
DebugProbe
J7
J9 J10
UARTU42
U37
J11PAL
Prog.
J3 100-pinDIMM Connector
D5
1
51
50
100
X1
Real-TimeClock
FactoryUseOnly
Clock
J2
C1B1A1
C50B50A50
150-Pin DIN Connector
U1
U12FLASHEPROM
U25EPROM
1 Mbyte
1 Mbyte
VoltageRegulators
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3.2 External Interfaces
This section describes the external interfaces to the BDMR4103
Evaluation Board. The connectors that implement the interfaces let you
connect external logic, download software, connect to the Ethernet,
debug the board, program the PAL, and so forth. This section describes
the connectors listed inTable 3.1.Figure 3.1(page 3-2) shows the
positions of the connectors on the board.
Table 3.1 Summary of LR4103 Interface Connector Functions
BoardLocation Connector Name Description Application Main Ref.
J1 Power Supply Standard 5 V, 4.0 A,DC power connector
Connects board to ACpower supply.
Page3-19
J2 Expansion 150-pin DIN connector Connects externalmodules to board;expands design anddebug capabilities.
Page3-4
J3 DIMM 100-pin DIMM connector Allows a DIMM moduleto be installed on theboard, either SDRAM(Synchronous DRAM) orEDO (Extended Data
Output).
Page3-7
J4 EJTAG 16-pin connector Provides basic breakand run control. Allowsyou to downloadprograms and data tomemory. You can usethis connector orconnector J5 to debugthe board.
Page3-13
J5 EJTAG 52-pin connector Provides the samedebugging capabilitiesas J4, plus PC tracecapability.
Page3-15
J6 Debug Probe 20-pin connector Used only for factorytesting. Do not use thisconnector.
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3.2.1 Expansion Connector (J2)
A 150-pin DIN connector (J2) lets you expand your design anddebugging capability to include external logic.Figure 3.2onpage 3-5
shows the pin numbers for the expansion connector andTable 3.2on
page 3-5lists the pin assignments.
Note that the expansion connector signals are not buffered on the
BDMR4103 Evaluation Board. You should buffer these signals when
using them off the evaluation board.
J7 Ethernet 10BASE-T RJ45 connector Connects the board to
the Ethernet using astandard 10BASE-Tplug.
Page
3-12
J8 SerialICE-1 Interface 10-pin header Provides a logic levelSerialICE-1 interface.You need specialequipment to use thisinterface.
Page3-11
J9 SerialICE-1 RS232 DB-9 connector Provides a standardRS232 serial connectorfor SerialICE-1 Debug
Interface.
Page3-10
J10 Serial Port DB-9 connector Allows you to connect astandard terminal forRS232 serial I/Ocommunication.
Page3-9
J11 PAL Programming Port 8-pin header Allows you to programthe PAL (U42).
Page3-18
Table 3.1 Summary of LR4103 Interface Connector Functions (Cont.)
BoardLocation Connector Name Description Application Main Ref.
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Figure 3.2 Expansion Connector
Table 3.2 Expansion Connector Pin Designations
Pin Signal Name Pin Signal Name Pin Signal Name
A1 +5 V B1 Ground C1 Ground
A2 +5 V B2 Ground C2 Ground
A3 +5 V B3 FADDR12 C3 FADP00
A4 Ground B4 FADDR13 C4 FADP01
A5 Ground B5 FADDR14 C5 FADP02
A6 Ground B6 FADDR15 C6 FADP03
A7 INTP0 B7 FADDR16 C7 FADP04
A8 INTP1 B8 FADDR17 C8 FADP05
A9 INTP2 B9 FADDR18 C9 FADP06
A10 INTP3 B10 FADDR19 C10 FADP07
A11 INTP4 B11 Ground C11 FADP08
A12 INTP5 B12 FADDR20 C12 FADP09
A13 T0_OUTN B13 FADDR21 C13 FADP10
A14 T1_OUTN B14 FADDR22 C14 FADP11
A15 Ground B15 FADDR23 C15 FADP12
A16 NC1 B16 AFADDR24 C16 FADP13
A17 BOOTCFG0 B17 FADDR25 C17 FADP14
A18 BOOTCFG1 B18 FADDR26 C18 FADP15
Position #1
Row C
Row B
Row AA1 Indicator
Position #50
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A19 BOOTCFG2 B19 Ground C19 Ground
A20 NC
1
B20 SDCASN C20 SDWEN
A21 NC1 B21 SDDDMP0 C21 SDDMP1
A22 CWAITP B22 SDCSN0 C22 SDRASN
A23 RSTOUTN B23 FADDR01 C23 FADDRP00
A24 RESETN B24 FADDR03 C24 FADDRP02
A25 Ground B25 FADDR05 C25 FADDRP04
A26 NC1 B26 FADDR07 C26 FADDRP06
A27 GP0 B27 FADDR09 C27 FADDRP08
A28 GP1 B28 FADDR11 C28 FADDRP10
A29 GP2 B29 FADDR28 C29 FADDRP27
A30 GP3 B30 SDCSN1 C30 SDCLK0
A31 GP4 B31 SDDMP2 C31 Ground
A32 GP5 B32 SDDMP3 C32 FADP16
A33 Ground B33 Ground C33 FADP17
A34 GPWEN0 B34 FRAMEN C34 FADP18
A35 GPWEN1 B35 IRDYN C35 FADP19
A36 GPWEN2 B36 TRDYN C36 FADP20
A37 GPWEN3 B37 STOPN C37 FADP21
A38 GPRDN B38 DEVSELN C38 FADP22
A39 Ground B39 PBCLK C39 FADP23
A40 GPI00 B40 Ground C40 Ground
A41 GPI01 B41 CEBEN0 C41 FADP24
A42 GPI02 B42 CEBEN1 C42 FADP25
A43 GPI03 B43 CEBEN2 C43 FADP26
Table 3.2 Expansion Connector Pin Designations (Cont.)
Pin Signal Name Pin Signal Name Pin Signal Name
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3.2.2 DIMM Connector (J3)
A 100-pin DIMM connector (J3), allows you to install a DIMM (Dual Inline
Memory Module) on the board. The connector accommodates DIMMs
populated with SDRAM or EDO devices.Figure 3.3shows the pin
numbers for this connector andTable 3.3lists the pin assignments. In
Table 3.3onpage 3-8, NC in the Signal Name column signifies No
Connection on the listed pin.
Figure 3.3 DIMM Connector Pin Numbers
A44 NC1 B44 CEBEN3 C44 FADP27
A45 Ground B45 SDONEP C45 FADP28
A46 Ground B46 FALEP C46 FADP29
A47 Ground B47 EXP_GNTN C47 FADP30
A48 +3.3 V B48 EXP_REQN C48 FADP31
A49 +3.3 V B49 Ground C49 Ground
A50 +3.3 V B50 Ground C50 Ground
1. Not connected.
Table 3.2 Expansion Connector Pin Designations (Cont.)
Pin Signal Name Pin Signal Name Pin Signal Name
50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 08 06 04 02
49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 09 07 05 03 01
100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 5299 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51
PinsPins
1
51
50
100
Keys
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Table 3.3 DIMM Connector Pin Assignments
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
1 Ground 26 Ground 51 Ground 76 Ground
2 FADP00 27 +3.3 V 52 FADP08 77 +3.3 V
3 FADP01 28 SDWEN 53 FADP09 78 SDCASN
4 FADP02 29 SDCSN0 54 FADP10 79 SDCSN1
5 FADP03 30 SDCSN0 55 FADP11 80 SDCSN1
6 +3.3 V 31 +3.3 V 56 +3.3 V 81 +3.3 V
7 FADP04 32 NC2 57 FADP12 82 NC2
8 FADP05 33 NC2 58 FADP13 83 NC2
9 FADP06 34 NC2 59 FADP14 84 NC2
10 FADP07 35 NC2 60 FADP15 85 NC2
11 SDDMP0 36 Ground 61 SDDMP1 86 Ground
12 Ground 37 SDDMP2 62 Ground 87 SDDMP3
13 FADDRP00 38 FADP16 63 FADDRP01 88 FADP24
14 FADDRP02 39 FADP17 64 FADDRP03 89 FADP25
15 FADDRP04 40 FADP18 65 FADDRP05 90 FADP26
16 FADDRP06 41 FADP19 66 FADDRP07 91 FADP27
17 FADDRP08 42 +3.3 V 67 FADDRP09 92 +3.3 V
18 FADDRP10 43 FADP20 68 FADDRP27 (BA0)1
FADDRP11 (A11)93 FADP28
19 FADDRP28 44 FADP21 69 FADDRP11 94 FADP29
20 NC2 45 FADP22 70 NC2 95 FADP30
21 +3.3 V 46 FADP23 71 +3.3 V 96 FADP31
22 NC2 47 Ground 72 SDRASN 97 Ground
23 NC2 48 GPI01 73 SDCASN 98 Ground
24 NC2
49 GPI00 74 NC2
99 Ground25 SDCLK0 50 +3.3 V 75 SDCLK0 100 Ground
1. The signal on pin 68 depends upon the setting of JP17. Refer toSection 2.2.14, EDO/SDRAMSelection (JP17), page 2-13.
2. Not connected.
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3.2.3 Serial Port Connector (J10)
A 9-pin serial port connector (J10) provides connections for serial port
devices.Figure 3.4shows the pin numbers for this connector and
Table 3.4lists the pin assignments. The PROM Monitor initializes the
serial port to operate at 9600 baud with eight bits of data, no parity bit,
and one stop bit.
Figure 3.4 Serial Port Connector
RX
Ground
RTS CTS
1 2 3 4 5
9876
TX
DTR
Not connected
DCD Data Carrier Detect
Transmitted Data
Received Data
Request to Send Clear to Send
Data Terminal Ready
DSR Data Set Ready
Table 3.4 Serial Port Connector Pin Assignments
Pin Signal Name Description
1 DCD Data Carrier Detect (Not Connected)
2 RX Received Data
3 TX Transmitted Data
4 DTR Data Terminal Ready (Not Connected)
5 GND Ground
6 DSR Data Set Ready (Not Connected)
7 RTS Request to Send
8 CTS Clear to Send
9 Not Connected
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3.2.4 RS-232 Serial Connector for SerialICE-1 Debug Interface(J9)
A DB-9 connector (J9) allows you to debug the board using the
SerialICE-1 debug Interface through an RS-232 cable. Pins 1 and 2 of
jumper JP15 need to be shorted to route the RS-232 TX signal to the
ICERXP pin of the LR4103 ICEport.Figure 3.5shows the pin numbers
for this connector andTable 3.5lists the signal assignments.
Figure 3.5 RS-232 SerialICE-1 Connector
RX
Ground
RTS CTS
1 2 3 4 5
9876
TX
DTR
Not connected
DCD Data Carrier Detect
Transmitted Data
Received Data
Request to Send Clear to Send
Data Terminal Ready
DSR Data Set Ready
Table 3.5 RS-232 SerialICE-1 Connector Pin Assignments
Pin Signal Name Description
1 DCD Data Carrier Detect (Not Connected)
2 RX Received Data
3 TX Transmitted Data
4 DTR Data Terminal Ready (Not Connected)
5 GND Ground
6 DSR Data Set Ready (Not Connected)
7 RTS Request to Send (Not Connected)
8 CTS Clear to Send (Not Connected)
9 Not Connected
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3.2.5 SerialICE-1 Connector (J8)
A 10-pin header (J8) allows you to debug the board using SerialICE-1.
Pins 2 and 3 of jumper JP15 need to be shorted to route the CONN_RXP
signal to the ICERXP pin of the LR4103 ICEport.Figure 3.6shows the
pin numbers for this connector andTable 3.6lists the signal assignments.
Figure 3.6 SerialICE-1 Connector
Table 3.6 SerialICE-1 Header Pin Assignments
Pin Signal Name Description
1 CLK_OUT Supplies clock output from the oscillator (U6).
2 Ground.
3 Ground.
4 CLK_IN Provides clock source for the LR4103 ICEport
5 Ground
6 Ground
7 SI_RESET System Reset
8 CONN_RXP Received Serial Data
9 +5 V + 5 V
10 ICE_TXP Transmitted Serial Data
1 3 5 7 9
2 4 6 8 10
Input from Oscillator
Ground
Ground
SI_RESET
+5 V
Ground
ICECLKP
Ground
CONN_RXP
ICE_TXP Input
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3.2.6 Ethernet Connector (J7)
The Ethernet 10BASE-T connector (J7) is a standard RJ45 connector
that allows you to connect the board to Ethernet. Figure 3.7shows the
pin numbers for this connector andTable 3.7lists the pin assignments.
Figure 3.7 Ethernet 10BASE-T Connector
1 2 3 4 5 6
TDTransmitted Data Return
RDReceived Data Return
Not connected Not connected
7 8
Not connected
Not connected
RJ45
RD+ Received Data
TD+ Transmitted Data
Table 3.7 Ethernet Connector Pin Assignments
Pin Name Description
1 TD+ Transmitted Data
2 TD Transmitted Data Return
3 RD+ Received Data
4 NC Not Connected
5 NC Not Connected
6 RD Received Data Return
7 NC Not Connected
8 NC Not Connected
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3.2.7 EJTAG Connectors
The BDMR4103 has two EJTAG connectors used to debug the board.
The connectors are at locations J4 and J5. This section provides an
overview of EJTAG functions and describes the two EJTAG connectors.
3.2.7.1 Overview of EJTAG Functions
EJTAG is an on-chip debug solution from the MIPS licensees/partners.
EJTAG provides a nonintrusive leading-edge debug tool for the LSI Logic
MiniRISC and TinyRISC microprocessors in PC and workstation
environments. EJTAG is intended to establish a debug standard among
MIPS partners and simplify the development of systems based on MIPS
microprocessors.
EJTAG allows you to debug user code for the MIPS16 ASE (application
specific extension) and MIPS I/II/III ISA (instruction set architecture). The
revision of the EJTAG specification implemented by LSI Logic is EJTAG
Revision 1.5.3.
The EJTAG functions associated with the BDMR4103 evaluation board
are implemented as hardware. These functions include:
EJTAG interface and memory
Software breakpoints
Single stepping DMA support
Instruction, data, and processor breakpoints
PC trace (J5)
Profiling
3.2.7.2 EJTAG Connector (J4)
The 16-pin EJTAG connector (J4) allows you to use a subset of the
EJTAG functions, including downloading data and programs to memory
and run control. The connector does not support PC trace.Figure 3.8
shows the pin numbers for this EJTAG connector andTable 3.8lists the
pin assignments.
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42/1003-14 Board Design and Layout
Figure 3.8 EJTAG Connector J4
1 3 5 7 9
2 4 6 8 10 12 14 16
11 13 15
Table 3.8 EJTAG Connector J4 Pin Assignment
Pin Signal Name Input/Output Description
1 TDO O TDO (test data output) performs different functions,depending on whether or not PC trace mode is turnedon. Connector J4 does not support PC trace, so thefunctions of this signal are the same as those whenPC trace mode is turned off. That is, serial output datais shifted from the JTAG instruction of the data registerto pin 1 (TDO) on the falling edge of the test clock,
TCK. When no data is shifted out, this pin is in a3-state (high impedance) condition.
2, 5, 8, 10,11, 14, 15
Not connected.
3 TDI/DINT I TDI (test data input)/DINT(debug interrupt).
4 TRST I TRST (test reset) is an active-low, asynchronous,reset signal that resets the EJTAG moduleindependently of the processor logic.
6 3.3 V I 3.3 V power.
7 TCK I TCK (test clock) is the input clock used to shift datainto or out of the instruction register or data register.
9 TMS I TMS (test mode select) is decoded by the TAPcontroller to control test operation. The signal issampled on the rising edge of TCK.
12, 16 Ground
13 EJTAG_RESET I This signal is a board level reset signal.
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3.2.7.3 EJTAG Connector (J5)
The 52-pin EJTAG connector (J5) supports the same EJTAG functions
as the connector at J4. In addition, it supports PC trace.Figure 3.9
shows the pin numbers for the connector andTable 3.9lists the pin
assignments.
Figure 3.9 EJTAG Connector J5
Table 3.9 EJTAG Connector J5 Pin Assignments
Pin # Signal Name Input/Output Description
1 TRST I TRST (test reset) is an active-low, asynchronous, resetsignal that resets the EJTAG module independently ofthe processor logic.
3 TDI/DINT I PC trace mode off:Serial input data (TDI, test datainput) is shifted into the JTAG Instruction register orData register on the rising edge of the TCK clock,depending on the TAP (test access port) controllerstate.
PC trace mode on:An active-LOW level on this pin(DINT, debug interrupt) is used as an interrupt to switchoff PC trace mode. This signal is sampled at the TCKpositive edge or asynchronous to TCK.
5 TDO/TPC O PC trace mode off:Serial output data (TDO) is shiftedfrom the JTAG instruction of the data register to this pinon the falling edge of the test clock, TCK. When nodata is shifted out, this pin is in a 3-state (off) condition.
PC trace mode on:This pin provides a nonsequentialprogram counter (TPC) on each DCLK clock.
7 TMS I TMS (test mode select) is decoded by the TAPcontroller to control test operation. The signal issampled on the rising edge of TCK.
9 TCK I TCK (test clock) is the input clock used to shift data intoor out of the instruction register or data register.
2 4 6 8 10 12 14 16 18 20 44 46 48 50 52
43 45 47 49 511 3 5 7 9 11 13 15 17 19
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PCST3_[2:0] O During PC trace mode, the status of the CPU isencoded for every CPU cycle using this group of three
status bits. When N (as in DCLK is 1/N processorclock) is greater than 2, PCST3_[2:0] contains the thirdmost recent status bits.
31 PCST3_ 0 PC status trace set 3, bit 0.
33 PCST3_1 PC status trace set 3, bit 1.
35 PCST3_2 PC status trace set 3, bit 2.
37 TPC4 O PC trace out 4. This pin provides a nonsequentialprogram counter (TPC) on each DCLK, when M (whereM is the number of address bits output for each DCLK)
is greater than 2.
PCST4_[2:0] O During PC trace mode, the status of the CPU isencoded for every CPU cycle using this group of threestatus bits. When N (as in DCLK is 1/N processorclock) equals 4, PCST4_[2:0] contains the fourth mostrecent status bits.
39 PCST4_ 0 PC status trace set 4, bit 0.
41 PCST4_1 PC status trace set 4, bit 1.
43 PCST4_2 PC status trace set 4, bit 2.
45 TPC5 O PC trace out 5. This pin provides a nonsequentialprogram counter (TPC) on each DCLK, when M (whereM is the number of address bits output for each DCLK)equals 8.
47 TPC6 O PC trace out 6. This pin provides a nonsequentialprogram counter (TPC) on each DCLK, when M (whereM is the number of address bits output for each DCLK)equals 8.
49 TPC7 O PC trace out 7. This pin provides a nonsequentialprogram counter (TPC) on each DCLK, when M (where
M is the number of address bits output for each DCLK)equals 8.
Table 3.9 EJTAG Connector J5 Pin Assignments (Cont.)
Pin # Signal Name Input/Output Description
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3.2.9 Power Supply Connector (J1)
The BDMR4103 Evaluation Board has a standard 5 V, 4.0 A DC power
supply connector (Figure 3.11), at location J1.
Figure 3.11 Power Supply Connector
LSI Logic supplies a switching AC adapter with a standard power inlet
that lets you connect the board to AC power. The adapter takes inputs
from 100240 V AC, 5060 Hz, and outputs +5 V DC at 4.0 amps.
The red LED (D5) comes on when power is applied to the board.
Table 3.10 PAL Programming Connector Pin Assignments
Pins Signal Name Description
1 3.3 V 3.3 V Power Input
2 SDO Serial Data Out
3 SDI Serial Data In
4 ISP_EN Program Enable
5 Not Connected
6 ISP_MODE In-System Programmable Mode
7 Ground Ground
8 ISP_SCLK PAL Program Clock Input
5 V
Ground
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49/100Indicators 3-21
3.3.2 Ethernet LEDs
There are four LEDs on the edge of the evaluation board, to the left of
the Ethernet connector, as shown inFigure 3.13. These indicators come
on during Ethernet activity.Table 3.11summarizes the Ethernet indicator
functions
Figure 3.13 Ethernet Indicator Positions
3.3.3 Debug LED
The yellow LED (D6) indicates the board is in debug mode. The LED
lights when the DM bit in the CP0 debug register of the LR4103 is set.
The DM bit is part of the EJTAG debugging system. Refer toSection 3.2.7.1, Overview of EJTAG Functions,onpage 3-13.
Table 3.11 Ethernet Indicator Functions
Indicator Location Function
TX D1 Activated to indicate data is being transmitted.
RX D2 Activated to indicate data is being received.
LNK D3 Activated when Ethernet link integrity is good.
COL D4 Activated when a collision occurs; that is, whentwo Ethernet devices are trying to transmit at thesame time. (This is not the default function of thisLED2 output from the AM79C970. The Ethernetcontroller initialization code should enable thisfunction.)
D1 D2 D3 D4
Ethernet Indicators
TX RX COLLNK
Edge of
EvaluationBoard
Ethernet 10BASE-TConnector
Green
Green
Yellow
Red
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50/1003-22 Board Design and Layout
3.3.4 7-Segment Display
The 7-segment display (U35) shown inFigure 3.14is attached to a
memory-mapped latch (register), at location U34. A read operation to the
register returns the current value stored in the register and displayed on
the segment display. A write operation to the register changes the value
shown on the segment display.Table 3.12lists the data bit assignments
for each segment. When the related bit is cleared to 0, the segment
turns on, when the related bit is set to 1, the segment turns off. The
7-segment display is at address 0x1E00 0020 in the system memory
map and must be accessed with byte operations.
Figure 3.14 7-Segment Display
Table 3.12 7-Segment Display Settings
Data Bit Segment
D0 a
D1 b
D2 c
D3 d
D4 e
D5 f
D6 g
D7 Decimal point
a
b
c
d
e
f
Decimal Point
Example
D0 = 1
D1 = 1D2 = 0
D3 = 0
D4 = 0
D5 = 0
D6 = 0
D7 = 1
a (D0)
b (D1)
c (D2)
d (D3)
e (D4)
f (D5)g g (D6)
Segment offSegment on
No decimal (D7)DecimalPoint
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51/100System Memory 3-23
3.4 System Memory
The BDMR4103 Evaluation Board accommodates a variety of memory
devices, including SDRAM DIMM, SRAM (static RAM), and boot PROM.
This section describes the different memory types and usage.Figure 3.1
onpage 3-2shows the position of the different memory modules on the
board.
3.4.1 Synchronous DRAM Dual Inline Memory Module (SDRAM DIMM)
The BDMR4103 Evaluation Board uses the 16 Mbyte SDRAM DIMM
installed in the DIMM socket as the main system memory. The software
LSI Logic provides initializes the FBM (FbusMACRO) to address the
SDRAM DIMM at memory location 0x0000 0000. The FBM provides a
glueless interface to the SDRAM DIMM. The LR4103 microprocessor
supports other SDRAM DIMM configurations, as well as EDO DRAM. If
you use DRAM other than the 16 Mbyte SDRAM DIMM, you must modify
the FBM configuration code.
If an external PCI master needs access to the SDRAM, the SDRAM
clock must be set to 33 MHz. CPU to SDRAM accesses also occur at
33 MHz in this case.
3.4.2 Static RAM (SRAM)
The evaluation board also contains 128 Kbytes of SRAM. The softwareLSI Logic provides initializes the FBM to address the SRAM at memorylocation 0x0E00 0000. The Ethernet controller uses the SRAM devicesto hold its transmit and receive buffers.
This memory is used by an external PCI interface to store temporaryvalues without constraining the SDRAM clock to 33 MHz.
You can also use the SRAM to store programs or data.
3.4.3 Boot EPROMs
The BDMR4103 board is shipped with an AM29F080, 1 Mbyte, FLASHEPROM installed at location U12. The board also contains a DIP socket,
at location U25, in which an optional 32-pin UV EPROM may beinstalled. The socket accommodates EPROMs up to 1 Mbyte, and theEPROM installed in this socket sits over the top of the FLASH EPROMat location U12.
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52/1003-24 Board Design and Layout
The boot EPROMs are addressed at the MIPS boot vector address,
which is 0x1FC0 0000. The order in which the boot EPROMs are
addressed decides which EPROM acts as the boot EPROM. This is
determined by jumper JP9. If JP9 is not installed, the AM29F080 at U12
is selected as the boot device. If JP9 is installed, the UV EPROM at U25
is selected as the boot device. The PAL at U42 maps the addresses ofthe EPROMs to select the boot and alternate device.
Installing jumper JP8 inverts address bit 19 (A19), the most significant
address bit, to the boot EPROM. This allows you to install two boot
programs in the same 1 Mbyte boot EPROM. Each boot program must
be less than 512 Kbytes. The addressing of the nonboot EPROM is not
affected by jumper JP8. Table 3.13lists boot EPROM addresses with
JP8 installed and JP8 not installed.
3.5 Memory MapTable 3.14shows the BDMR4103 memory map. Note that the LR4103
microprocessor contains a programmable memory controller, known as
the FBusMACRO, and that all address mappings shown inTable 3.14
can be altered by software. However, the addresses shown inTable 3.14
are those that LSI Logic uses for any software delivered with the
BDMR4103 Evaluation Board.
All memory and peripheral devices on the BDMR4103 board can be
accessed in either user or kernel mode. In user mode, addresses inprograms (virtual addresses) must be inkuseg, that is, in the range
0x0000 0000 to 0x7FFF FFFF. Kernel-mode programs typically use
virtual addresses inkseg0(0x8000 0000 to 0x9FFF FFFF) for cacheable
locations, andkseg1(0xA000 0000 to 0xBFFF FFFF) for noncacheable
locations.
Table 3.13 Boot EPROM Addressing
LR4103 AddressBoot EPROM Addresswith JP8 Installed
Boot EPROM Addresswith JP8 Not Installed
0x1FC0 0000 0x80000 0x00000
0x1FC0 8000 0x00000 0x80000
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53/100Memory Map 3-25
Some device selects are partially decoded off chip, using a general
purpose chip select, gp[5:0], and an address offset. These selects are
noted as gpx + offset. This method of decoding chip selects was used
to leave some gp[x] selects free for expansion.
Table 3.14 Physical Memory Map
Address RangeControlling ChipSelect Device Name
0x1FE0 00200x1FE0 0000
FAPI AM79C970A Ethernet Controller
0x1FD0 00000x1FDF FFFF
gp0 + 0x10 0000 1 Mbyte EPROM (U25) or FLASH EPROM (U12)(EPROM type depends on setting of jumper JP9)
0x1FC0 00000x1FCF FFFF
gp0 1 Mbyte EPROM (U25) or FLASH EPROM (U12)(EPROM type depends on setting of jumper JP9)
Unused
0x1E00 003F0x1E00 0030
gp4 + 0x30 RTC Interrupt Clear
0x1E00 002F0x1E00 0020
gp4 + 0x20 7-Segment Display
0x1E00 001F0x1E00 0000
gp4 + 0x0 16550 UART
Unused
0x0E01 FFFF0x0E00 0000
gp3 128 Kbyte SRAM
Unused
0x00FF FFFF
0x0000 0000
gp2 16 Mbyte SDRAM
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54/1003-26 Board Design and Layout
3.6 Two-Wire Serial Bus Peripheral Devices
The BDMR4103 board contains three peripheral devices that use a
standard two-wire serial bus. They are
A real-time clock (U37)
A 1 Kbyte EEPROM (U13)
A serial presence detect (SPD), which is on the DRAM DIMM
The LR4103 microprocessor does not contain any dedicated two-wire
serial bus support hardware, but instead communicates with the two-wire
serial bus peripheral devices using the general purpose I/O pins,
gpIO[1:0], which are driven by software. This section describes each of
the peripheral devices.
The supported devices use a bidirectional two-wire bus and data
transmission protocol. Devices sending data onto the bus are described
as transmitters and the devices receiving data are the receivers. The
device that controls the message is the master and the devices
controlled by the master are slaves. The slave devices must be controlled
by a master device that generates a serial clock (SCL), controls bus
access, and generates start and stop conditions.
3.6.1 Real-Time Clock (RTC)
The BDMR4103 board is equipped with a DALLAS Semiconductor
DS 1307 real-time clock at U37. This RTC provides a battery-backed
clock and date function for the evaluation board. You can also program
the RTC to supply a periodic interrupt to the LR4103. The falling edge of
the SQW (Square Wave) output from the RTC is used to set a latch in
the PLD (programmable logic device), which then asserts an interrupt
(int5) to the LR4103 microprocessor. The interrupt is cleared by writing
to location gp4 + 0x30 (0x1E00 0030).
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55/100Two-Wire Serial Bus Peripheral Devices 3-27
Table 3.15shows the address space for the RTC.
Table 3.16shows the RTC registers.
Table 3.15 Real-Time Clock Addressing
Device ID Address Read/Write
1101 0b000 1 = Read0 = Write
Table 3.16 RTC Registers
RegisterName
Address
Register Bits
Range
7 6 5 4 3 2 1 0
Seconds 0x00 CH1 10 Seconds Seconds 0059
Minutes 0x01 10 Minutes Minutes 0059
Hours 0x02 12/24 10/AMor PM
10 Hour Hour 0112 +AM/PM0023
Day 0x03 Day 17
Date 0x04 10 Date Date 0128/2901300131
Month 0x05 10Month
Month 0112
Year 0x06 10 Year Year 0099
Control 0x07 OUT2 SQWE3 RS1 RS0
RAM 0x08 0x3F
56 8-bit registers
1. Clock Halt. When HIGH, the oscillator is disabled. When LOW, the oscillator is enabled.2. Output control. This bit controls the output level of the SQW/OUT pin when the oscillator is disabled.
If SQWE is LOW, the level on the SQW/OUT pin is HIGH if OUT is HIGH and LOW if OUT is LOW.3. Square Wave Enable. When HIGH, enables oscillator output. Frequency is controlled by the Rate
Select bits of the Control register (RS[1:0]). Available frequencies are 1 Hz (RS[1:0] = 00),4.096 KHz (RS[1:0] = 01), 8.192 KHz (RS[1:0] = 10), and 32.768 KHz (RS[1:0] = 11).
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56/1003-28 Board Design and Layout
For detailed information about the RTC, refer to the DALLAS
Semiconductor datasheet for theDS1307/DS1308 64 X 8 Serial Real
Time Clock.
3.6.2 EEPROM
The BDMR4103 Evaluation Board is equipped with an NM24C08 1 Kbyte
EEPROM that provides nonvolatile storage for board identification and
configuration information.Table 3.17shows the address of the EEPROM.
3.6.3 Serial Presence Detect (SPD)
The 100-pin DIMM installed in the DIMM socket (J3) is equipped with an
SPD EEPROM. The SPD EEPROM contains information about the types
and configuration of the memory devices installed on the DIMM. You can
use the information in the SPD EEPROM to configure the BDMR4103
board to operate with different types of DIMMs.Table 3.18shows the
address of the SPD EEPROM.0
Table 3.17 EEPROM Addressing
Device ID Address Read/Write
1010 0b1xx 1 = Read
0 = Write
Table 3.18 SPD EEPROM Addressing
Device ID Address Read/Write
1010 0b000 1 = Read0 = Write
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57/100Device Registers 3-29
3.6.4 LR4103 Interrupts
Table 3.19shows how the interrupts from the evaluation board are
connected to the LR4103 microprocessor.
3.7 Device Registers
This section describes the BDMR4103 Evaluation Board devices that
have registers. They are:
PC16550D UART (U24)
Am79C970A Ethernet Controller (U19)
The real-time clock (U37) also has registers, which are described in
Table 3.16, onpage 3-27.
Table 3.19 BDMR4103 Interrupts
InterruptNumber Source Cleared By
0 LR4103 DBE/FBDSTOP Writing to the DBE bit in SCR1 or theFBDSTOP bit in SCR2 of the LR4103.
1 LR4103 Timer 0 Writing to the bit in Timer 0.
2 SerialICE-1 Debugger Writing to the bit in S1.
3 16550 UART orLR4103 Timer 1
Clearing the source in the UART orwriting to the bit in Timer 1
4 Ethernet Controller Clearing the source in the EthernetController
5 Real-Time Clock Writing to gp4 + 0x30 (0x1E000030)
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58/1003-30 Board Design and Layout
3.7.1 PC16550D UART Registers
Table 3.20lists the registers in the National Semiconductor UART at
location U24. For detailed information about the UART, refer to the
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs
datasheet from National Semiconductor Corporation.
Table 3.20 UART Registers
Address Register Name Access1
1. RO = Read Only, R/W = Read/Write, WO = Write Only
0x1E00 0000 gp4 + 0 Receiver Buffer Register RO
0x1E00 0000 gp4 + 0 Transmitter Holding Register WO
0x1E00 0001 gp4 + 1 Interrupt Enable Register R/W
0x1E00 0002 gp4 + 2 Interrupt Identification Register R/W
0x1E00 0002 gp4 + 2 FIFO Control Register WO
0x1E00 0003 gp4 + 3 Line Control Register R/W
0x1E00 0004 gp4 + 4 Modem Control Register R/W
0x1E00 0005 gp4 + 5 Line Status Register R/W
0x1E00 0006 gp4 + 6 Modem Status Register R/W
0x1E00 0007 gp4 + 7 Scratchpad Register R/W0x1E00 0000 gp4 + 0 Divisor Latch Register (LS) R/W
0x1E00 0001 gp4 + 1 Divisor Latch Register (MS) R/W
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59/100Device Registers 3-31
3.7.2 Am79C970A Ethernet Controller
Table 3.21describes the user registers in the Am79C970A Ethernet
Controller. The PCI configuration registers are accessed with PCI
configuration cycles. The Am79C970A Ethernet Controller responds to a
configuration cycle with A16 = 1.
Table 3.21 Ethernet Controller User Registers
Address A[31:0] Access1 Register Name
PCI Configuration Registers
0x1FE9 0000 RO PCI Vendor ID
0x1FE9 0002 RO PCI Device ID
0x1FE9 0004 R/W PCI Command
0x1FE9 0006 R/W PCI Status
0x1FE9 0008 RO PCI Revision ID
0x1FE9 0009 RO PCI Programming Interface
0x1FE9 000A RO PCI Subclass
0x1FE9 000B RO PCI Base-Class
0x1FE9 000C RO PCI Latency Timer
0x1FE9 000E RO PCI Header Type
0x1FE9 0010 R/W PCI I/O Base Address
0x1FE9 0014 R/W PCI Memory Mapped I/O Base Address
0x1FE9 0030 RO PCI Expansion ROM Base Address
0x1FE9 003C R/W PCI Interrupt Line
0x1FE9 003D RO PCI Interrupt Pin
0x1FE9 003E RO PCI MIN_GNT
0x1FE9 003F RO PCI MAX_LAT
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60/1003-32 Board Design and Layout
Refer to theAM79C970A PCnet-PCI II Single-Chip Full Duplex Ethernet
Control for PCI Local Bus Productdatasheet from Advanced MicroDevices Inc., for more information about the Ethernet Controller
registers.
I/O Registers2
0x1FE0 0010 R/W Register Data Port
0x1FE0 0014 R/W Register Address Port
0x1FE0 0018 R/W Reset
0x1FE0 001C R/W BCR Data Port
1. RO = Read Only, R/W = Read/Write2. You should use PCI memory access from the FBM (FBusMACRO) to access the I/O registers. I/O
device addresses are determined by the values programmed in the PCI configuration registers.
Table 3.21 Ethernet Controller User Registers (Cont.)
Address A[31:0] Access1 Register Name
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61/100TinyRISC
BDMR4103 Evaluation Board Users Guide 4-1
Chapter 4PAL Equations
This chapter provides the code listing for the Programmable Array Logic
(PAL) at location U42 on the BDMR4103 Evaluation Board.
The pin numbers in the equations refer to the pins on the PAL package
shipped on the BDMR4103 Evaluation Board.
The PAL performs the following tasks:
Decodes and controls external addresses for ROM devices
Both EPROMs on the evaluation board (the EPROM at U25 and the
Flash EPROM at U12) connect to chip select GP0 and are selected
by signal A20. Jumper JP9 selects the boot device and the
addressing order of each EPROM. Additionally, jumper JP8 sets
which boot program (regular or alternate) the selected EPROM uses.
If JP8 is installed, A19 is inverted and the alternate boot program is
selected. The setting of JP8 does not affect the nonboot ROM. Refer
toSection 2.2, Jumper Settings,for more information.
Decodes external addresses for devices connected to chip select
GP4
Devices connected to GP4 include the UART, seven-segment
display, and the real-time clock interrupt register. An address offset
is required for these devices. Refer toSection 3.5, Memory Map,
for each devices offset value.
Combines reset signals
The PAL gathers reset signals from other sources and combines
them into a single board-level reset request.
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62/1004-2 PAL Equations
Sets interrupts from RTC
The PAL sets a latch using the falling edge of the RTCs square ware
output. The latch is used as an interrupt for the LR4103. Write to the
latch to clear it.
Arbitrates the PCI bus
The PAL allows multiple PCI bus masters to connect to the LR4103.
You can only connect one PCI bus master to the LR4103.
The code in this chapter was up to date at the time of publication. To
verify that you have the latest code, you should contact LSI Logic
Corporation.
module core_logic
title 'lr4103 core logic'
U42 device 'ispLSI';
PLSI PROPERTY 'PART ispLSI2032v-100LT44';
"define pins and nodes
pbclk pin 5; "CLK"
jmp0 pin 2;
jmp1 pin 3;
addr20 pin 37; "used to select between eprom/flash"
addr19 pin 36; "invert a19 to allow 2 boot"programs in 1 rom"
addr05 pin 35; "used to select between uart/display"
addr04 pin 31; "used to select between rtc_int/display"
gp4 pin 32; "uart/display select"
gp0 pin 33; "eprom/flash select"
rdn pin 42;
we0 pin 44;
resetn pin 4;
flash_sel pin 23;
dip_sel pin 22;
rom_a19 pin 21;
bd_sel pin 20; "buffered data select"
uart_sel pin 26;
read_display pin 12; "7-seg display rd
write_display pin 13; "7-seg display wr
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63/1004-3
"*** Arbiter signals ***"
enet_req pin 14 ;
enet_gnt pin 15 istype 'reg_D';
exp_req pin 9 ;
exp_gnt pin 10 istype 'reg_D';
req pin 25 istype 'reg_D';"system req"
gnt pin 24; "system gnt"
sqw_out pin 16; "square wave out from RTC
intp5 pin 34; "interrupt to uP
arb0 node istype 'buffer, reg_D';
arb1 node istype 'buffer, reg_D';
arb2 node istype 'buffer, reg_D';
si_reset pin 41;
ejtag_reset pin 38;
pb_reset pin 43;
rtc_sync1 node istype 'reg_D';
rtc_sync2 node istype 'reg_D';
rtc_sync3 node istype 'reg_D';
rtc_intff node istype 'reg_SR';
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64/1004-4 PAL Equations
PLSI PROPERTY 'OPENDRAIN pb_reset';
"**************************************************************************
**"
"constants and state definitions
h,l,x,ck,z = 1,0,.X.,.C.,.Z.;
ARBITER = [arb2,arb1,arb0];
IDLE_ENET = [0,0,0];
IDLE_EXP = [0,0,1];
REQ_ENET = [1,0,0];
REQ_EXP = [1,0,1];
GNT_ENET = [0,1,0];
GNT_EXP = [0,1,1];
RESET = !resetn;
equations
ARBITER.clk = pbclk;
req.clk = pbclk;
enet_gnt.clk= pbclk;
exp_gnt.clk= pbclk;
rtc_sync1.clk= pbclk;
rtc_sync2.clk= pbclk;
rtc_sync3.clk= pbclk;rtc_intff.clk= pbclk;
!flash_sel = !gp0 & (( jp9 & !addr20 ) # (!jp9 & addr20));
!dip_sel = !gp0 & (( jp9 & addr20 ) # (!jp9 & !addr20));
rom_a19 = ((jp8 # addr20) & addr19) # ((!jp8 & !addr20) & !addr19);
!bd_sel = ( !gp0 # !gp4);
!uart_sel = (!gp4 & !addr05);
!read_display = (!gp4 & addr05 & !addr04 & !rdn );
!write_display = (!gp4 & addr05 & !addr04 & !we0) # (RESET);
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!pb_reset = !si_reset # !ejtag_reset;
pb_reset.en = !si_reset # !ejtag_reset;
rtc_sync1 := sqw_out;
rtc_sync2 := rtc_sync1;
rtc_sync3 := rtc_sync2;
rtc_intff.s = ( !rtc_sync2 & rtc_sync3);"set ff on falling edgertc_intff.r = ( !gp4 & addr05 & addr04 ) # (RESET);
intp5 = rtc_intff;
STATE_DIAGRAM ARBITER
state IDLE_ENET:
if (!enet_req) then REQ_ENET with
req := 0;
enet_gnt :=1; exp_gnt :=1;
endwith;
else if (!exp_req) then REQ_EXP with
req := 0;
enet_gnt :=1;
exp_gnt :=1;
endwith;
else IDLE_ENET with
req := 1;
enet_gnt :=1; exp_gnt :=1;
endwith;
state IDLE_EXP:
if (!exp_req) then REQ_EXP with
req := 0;
enet_gnt :=1;
exp_gnt :=1;
endwith;
else if (!enet_req) then REQ_ENET with
req := 0;
enet_gnt :=1;
exp_gnt :=1;
endwith;
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66/1004-6 PAL Equations
else IDLE_EXP with
req := 1;
enet_gnt :=1;
exp_gnt :=1;
endwith;
state REQ_ENET:
if ( !gnt & !enet_req) then GNT_ENET with
req := 0;
enet_gnt :=0;
exp_gnt :=1;
endwith;
else if ( !enet_req )then REQ_ENET with
req := 0;
enet_gnt :=1;
exp_gnt :=1;
endwith;
else IDLE_EXP with
req := 1;
enet_gnt :=1;
exp_gnt :=1;
endwith;
state REQ_EXP:
if ( !gnt & !exp_req) then GNT_EXP with
req := 0; enet_gnt :=1;
exp_gnt :=0;
endwith;
else if ( !exp_req )then REQ_ENET with
req := 0;
enet_gnt :=1;
exp_gnt :=1;
endwith;
else IDLE_ENET with
req := 1;
enet_gnt :=1;
exp_gnt :=1;
endwith;
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67/1004-7
else if ( !exp_req )then REQ_ENET with
req := 0;
enet_gnt :=1;
exp_gnt :=1;
endwith;
else IDLE_ENET with req := 1;
enet_gnt :=1;
exp_gnt :=1;
endwith;
state GNT_ENET:
if (!gnt & !enet_req) then GNT_ENET with
req := 0;
enet_gnt :=0; exp_gnt :=1;
endwith;
else IDLE_EXP with
req := 1;
enet_gnt :=1;
exp_gnt :=1;
endwith;
state GNT_EXP:
if (!gnt & !exp_req) then GNT_EXP with req := 0;
enet_gnt :=1;
exp_gnt :=0;
endwith;
else IDLE_EXP with
req := 1;
enet_gnt :=1;
exp_gnt :=1;
endwith;
end
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70/1005-2 Schematics
5.1 Microprocessor and Clock Circuitry
The microprocessor and clock circuitry shown inFigure 5.1performs the
following functions:
The LR4103 microprocessor (U1) provides a full-speed evaluationtarget.
A crystal (X1) provides the main clock for the LR4103
microprocessor.
The oscillator (U5) provides an alternate clock for the
microprocessor. This clock is used when an input frequency other
than 25 MHz is needed.
Jumpers JP16, and JP14 control various LR4103 functions. Refer
toSection 2.2, Jumper Settingsfor further information about thesejumpers.
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72/1005-4 Schematics
5.2 ROMs, SRAMs, and Address Latches
The ROMSs, SRAMs and address buffers shown inFigure 5.2perform
the following functions:
Four 32 Kbyte SRAM devices (U26, U27, U28, and U29) provide theBDMR4103 board with 128 Kbytes of SRAM, organized as 32 Kbytes
x 32 bits of memory.
A 1 Mbyte Flash EPROM (U12) is used as the boot device for the
board. This device is shipped with the board. Jumper J9 determines
whether this device or the EPROM at location U25 is the boot device.
When JP9 is not installed, U12 is the boot PROM.
You can store two boot programs in this EPROM, provided that
neither program is larger than 512 Kbytes. Jumper J8 selects
between any two programs installed.
Refer toSection 2.2.7, Boot Device Selection (JP9),for more
information about JP9, and toSection 2.2.6, Alternate Boot Program
Selection (JP8),for more information about JP8. Refer to
Section 3.4.3, Boot EPROMs,for more information on this subject.
A socket (U25) houses an optional 1 Mbyte of EPROM. When
installed, the EPROM sits over the top of Flash EPROM (U12). You
can use U25 as an alternate boot device for the board by installing
jumper JP9.
You can store two boot programs in this EPROM, provided that
neither program is larger than 512 Kbytes. Jumper J8 selects
between any two programs installed.
The SN74LCX16244 buffer (U22) buffers the lower order address
bits FADDRP[11:0] for all devices except the DRAM DIMM. This
buffering is provided to reduce the loading and trace length of these
high-speed signals.
The LCX245 buffer (U30) buffers the data to and from the EPROMs,
the 7-segment display, and the UART. This buffering is provided toreduce the loading and trace length of these high-speed signals.
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ROMs,SRAMs,andAddressLatches
5-5
Figure 5.2 ROMs, SRAMs, and Address Latches
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5.3 Ethernet and DRAM Circuitry
The Ethernet and DRAM circuitry shown inFigure 5.3performs the
following functions:
Ethernet circuitry:
The Ethernet transformer (U10), in conjunction with the Ethernet
controller, connects the evaluation board to an Ethernet LAN
(local area network).
The AM79C970A Ethernet Controller (U19). The controller, in
conjunction with the transformer, connects the evaluation board
to an Ethernet LAN.
Refer toSection 3.7.2, Am79C970A Ethernet Controller,for
more information about the controller. The RJ45 connector (J7) provides the Ethernet hardware
connection.
The 100-pin socket (J3) accommodates any standard 100-pin
JEDEC DIMM. A 16 Mbytes SDRAM DIMM is supplied with the
board. However, the socket will also accommodate EDO DRAM.
Jumper JP17 is used to select between SDRAM and EDO devices.
The memory installed in the socket at J3 provides the main system
memory for the board.
Refer toSection 3.2.2, DIMM Connector (J3),for further informationabout the connector, and toSection 3.4.1, Synchronous DRAM Dual
Inline Memory Module (SDRAM DIMM),for further information about
the DIMM. Refer toSection 2.2.14, EDO/SDRAM Selection (JP17),
for information about the jumper settings.
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EthernetandDRAM
Circu
itry
5-7
Figure 5.3 Ethernet and DRAM Circuitry
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76/1005-8 Schematics
5.4 Miscellaneous Circuitry and Connectors
Figure 5.4shows the following miscellaneous circuitry and connectors:
Lattice ISPLSI2032 PLD (U42) (programmable logic device).
DS1307 real-time clock (U37). Refer toSection 3.6.1, Real-TimeClock (RTC),for further information.
An NM24C08 1 Kbyte EEPROM (U13). Refer toSection 3.6.2,EEPROM,for further information.
7-segment display (U35) and the associated data buffer (U34). RefertoSection 3.3.4, 7-Segment Display,for further information.
The PC16550 UART (universal asynchronous receiver transmitter)(U24) performs serial-to-parallel and parallel-to-serial dataconversions on data received by and transferred from the board. For
additional information about the UART, refer to the NationalSemiconductor datasheet,PC16550D Universal AsynchronousReceiver/Transmitter with FIFOs.
The MAX3245 (U14) RS232 transceiver provides signal voltage leveltranslation.
The SerialICE-1 header (J8) allows you to debug the board usingSerialICE-1 inputs. Refer toSection 3.2.5, SerialICE-1 Connector(J8),for further information.
The RS232 SerialICE-1 port (J9) allows you to debug the board
using SerialICE-1 inputs. Refer toSection 3.2.4, RS-232 SerialConnector for SerialICE-1 Debug Interface(J9),for furtherinformation.
The RS232 serial port (J10) allows you to connect serial devices tothe board. Refer toSection 3.2.3, Serial Port Connector (J10),forfurther information.
The header (J11) is used to program the PAL (U42). Refer toSection 3.2.8, PAL Programming Connector (J11),for further
information.
Jumpers JP8 (boot program selection), JP9 (bo
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