1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-1
Chapter Four
Arithmetic for Computers
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-2
Arithmetic
• Where we've been:
– Performance (seconds, cycles, instructions)
– Abstractions: Instruction Set Architecture Assembly Language and Machine Language
• What's up ahead:
– Implementing the Architecture
32
32
32
operation
result
a
b
ALU
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-3
• Bits are just bits (no inherent meaning)— conventions define relationship between bits and numbers
• Binary numbers (base 2)0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...decimal: 0...2n-1
• Of course it gets more complicated:numbers are finite (overflow)fractions and real numbersnegative numberse.g., no MIPS subi instruction; addi can add a negative number)
• How do we represent negative numbers?i.e., which bit patterns will represent which numbers?
Numbers
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-4
• Sign Magnitude: One's Complement Two's Complement
000 = +0 000 = +0 000 = +0001 = +1 001 = +1 001 = +1010 = +2 010 = +2 010 = +2011 = +3 011 = +3 011 = +3100 = -0 100 = -3 100 = -4101 = -1 101 = -2 101 = -3110 = -2 110 = -1 110 = -2111 = -3 111 = -0 111 = -1
• Issues: balance, number of zeros, ease of operations
• Which one is best? Why?
Possible Representations
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-5
• 32 bit signed numbers:
0000 0000 0000 0000 0000 0000 0000 0000two = 0ten
0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten
0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten
...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten
0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten
1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten
...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten
1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten
1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten
maxint
minint
MIPS
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-6
• Negating a two's complement number: invert all bits and add 1
– remember: “negate” and “invert” are quite different!
• Converting n bit numbers into numbers with more than n bits:
– MIPS 16 bit immediate gets converted to 32 bits for arithmetic
– copy the most significant bit (the sign bit) into the other bits
0010 -> 0000 0010
1010 -> 1111 1010
– "sign extension" (lbu vs. lb)
Two's Complement Operations
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-7
Novas instruções
• instruções “unsigned”: (exemplo de aplicação, cálculo de memória)
• sltu $t1, $t2, $t3 # diferença é “sem sinal”
• slti e sltiu # envolve imediato, com ou sem sinal
• Exemplo pag 215: supor $s0 = FF FF FF FF e $s1 = 00 00 00 01
slt $t0, $s0, $s1como $s0 < 0 e $s1 > 0 $s0<$s1 $t0 = 1
sltu $t0, $s0, $s1como $s0 e $s1 não tem sinal $s0>$s1 $t0 = 0
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-8
Cuidados com extensão 16 bits
• beq $s0, $s1, nnn # salta para PC + nnn se teste OK
• nnn tem 16 bits e PC tem 32 bits
– estender de 16 para 32 bits antes daoperação aritmética
• se nnn > 0
– preencher com zeros à esquerda
• se nnn < 0 CUIDADO
– preencher com 1´s à esquerda
– verificar
• por este motivo operação é chamada de
– EXTENSÃO DE SINAL
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-9
• Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101
• Two's complement operations easy
– subtraction using addition of negative numbers 0111+ 1010
• Overflow (result too large for finite computer word):
– e.g., adding two n-bit numbers does not yield an n-bit number 0111+ 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”
Addition & Subtraction
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-10
• No overflow when adding a positive and a negative number
• No overflow when signs are the same for subtraction
• CONDIÇÕES DE OVERFLOW
Detecting Overflow
op A B resultado
A+B + + -
A+B - - +
A-B + - -
A-B - + +
Em hardware, comparar o “vai-um” e o “vem-um” com relação ao bit de sinal
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-11
• An exception (interrupt) occurs
– Control jumps to predefined address for exception (EPC — EXCEPTION PROGRAM COUNTER)
– Interrupted address is saved for possible resumption
• mfc0 (move from system control): copia endereço do EPC para qualquer registrador
• Don't always want to detect overflow— new MIPS instructions: addu, addiu, subu
note: addiu still sign-extends!note: sltu, sltiu for unsigned comparisons
Effects of Overflow
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-12
Instruções (fig 4.52 - pag 309) add add R multiply mult Radd immediate addi I multiply unsigned multu Radd unsigned addu R divide div Radd immediate unsigned addiu I divide unsigned divu Rsubtract sub R move from Hi mfhi Rsubtract unsigned subu R move from Lo mflo Rand and R move from system control (EPC) mfc0 Rand immediate andi I fp add single add.s Ror or R fp add doublr add.d Ror immediate ori I fp subtract single sub.s Rshift left logical sll R fp subtract double sub.d Rshift right logical srl R fp multiply single mul.s Rload upper immediate lui I fp multiply double mul.d Rload word lw I fp divide single div.s Rstore word sw I fp divide double div.d Rload byte unsigned lbu I load word to fp single lwc1 Istore byte sb I store word to fp single swc1 Ibranch on equal beq I branch on fp true bclt Ibranch on not equal bne I branch on fp false bclf Ijump j J fp compare single c.x.s Rjump and link jal J (x= eq,neq,lt,le,gt,ge)jump register jr R fp compare double c.x.d Rset less than slt R (x= eq,neq,lt,le,gt,ge)set less than immediate slti Iset less than unsigned sltu Rset less than immediate unsigned sltiu I
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-13
• Problem: Consider a logic function with three inputs: A, B, and C.
Output D is true if at least one input is trueOutput E is true if exactly two inputs are trueOutput F is true only if all three inputs are true
• Show the truth table for these three functions.
• Show the Boolean equations for these three functions.
• Show an implementation consisting of inverters, AND, and OR gates.
Review: Boolean Algebra & Gates
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-14
• Let's build an ALU to support the andi and ori instructions
– we'll just build a 1 bit ALU, and use 32 of them
• Possible Implementation (sum-of-products):
b
a
operation
result
op a b res
An ALU (arithmetic logic unit)
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-15
• Selects one of the inputs to be the output, based on a control input
• Lets build our ALU using a MUX:
S
CA
B0
1
Review: The Multiplexor
note: we call this a 2-input mux even though it has 3 inputs!
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-16
• Not easy to decide the “best” way to build something– Don't want too many inputs to a single gate– Dont want to have to go through too many gates– for our purposes, ease of comprehension is important
• Let's look at a 1-bit ALU for addition:
• How could we build a 1-bit ALU for add, and, and or?
• How could we build a 32-bit ALU?
Different Implementations
cout = a b + a cin + b cin
sum = a xor b xor cin
Sum
CarryIn
CarryOut
a
b
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-17
Building a 32 bit ALU
b
0
2
Result
Operation
a
1
CarryIn
CarryOut
Result31a31
b31
Result0
CarryIn
a0
b0
Result1a1
b1
Result2a2
b2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-18
• Two's complement approch: just negate b and add.
a - b = a + (- b)
• How do we negate?
(- a) = comp2(a) = comp1(a) + 1
• A very clever solution:
What about subtraction (a – b) ?
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-19
Subtrator
01
Binv
B
~Bequivalente à
B
Binv
Binv
+
+
+
+
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-20
• Need to support the set-on-less-than instruction (slt)
– remember: slt is an arithmetic instruction
– produces a 1 if rs < rt and 0 otherwise
– use subtraction: (a-b) < 0 implies a < b
• Need to support test for equality (beq $t5, $t6, $t7)
– use subtraction: (a-b) = 0 implies a = b
Tailoring the ALU to the MIPS
Supporting slt
• Can we figure out the idea?0
3
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b 2
Less
0
3
Result
Operation
a
1
CarryIn
0
1
Binvert
b 2
Less
Set
Overflowdetection
Overflow
a.
b.
0Rs
RtRd
bit de sinal
subtração
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-22
Seta31
0
ALU0 Result0
CarryIn
a0
Result1a1
0
Result2a2
0
Operation
b31
b0
b1
b2
Result31
Overflow
Binvert
CarryIn
Less
CarryIn
CarryOut
ALU1Less
CarryIn
CarryOut
ALU2Less
CarryIn
CarryOut
ALU31Less
CarryIn
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-23
Test for equality
• Notice control lines:
000 = and001 = or010 = add110 = subtract111 = slt
•Note: zero is a 1 when the result is zero!
Seta31
0
Result0a0
Result1a1
0
Result2a2
0
Operation
b31
b0
b1
b2
Result31
Overflow
Bnegate
Zero
ALU0Less
CarryIn
CarryOut
ALU1Less
CarryIn
CarryOut
ALU2Less
CarryIn
CarryOut
ALU31Less
CarryIn
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-24
ALU
Overflow
ALUop
A
B
Zero
Result
32 bits: A, B, result
1 bit: Zero, Overflow
3 bits: ALUop
ALUop
Binv-OPInstrução
0 00 and
0 01 or
0 10 add
1 10 sub
1 11 slt
1 10 beq
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-25
Conclusion
• We can build an ALU to support the MIPS instruction set
– key idea: use multiplexor to select the output we want
– we can efficiently perform subtraction using two’s complement
– we can replicate a 1-bit ALU to produce a 32-bit ALU
• Important points about hardware
– all of the gates are always working
– the speed of a gate is affected by the number of inputs to the gate
– the speed of a circuit is affected by the number of gates in series(on the “critical path” or the “deepest level of logic”)
• Our primary focus: comprehension, however,– Clever changes to organization can improve performance
(similar to using better algorithms in software)– we’ll look at two examples for addition and multiplication
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-26
• Is a 32-bit ALU as fast as a 1-bit ALU?atraso (ent soma ou carry = 2G)n estágios 2nG
• Is there more than one way to do addition?– two extremes:
ripple carry (2nG) sum-of-products (2G)
Can you see the ripple? How could you get rid of it?
c1 = b0c0 + a0c0 + a0b0
c2 = b1c1 + a1c1 + a1b1 c2 =
c3 = b2c2 + a2c2 + a2b2 c3 =
c4 = b3c3 + a3c3 + a3b3 c4 =
Not feasible! Why?
Problem: ripple carry adder is slow
Result31a31
b31
Result0
CarryIn
a0
b0
Result1a1
b1
Result2a2
b2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-27
• An approach in-between our two extremes
• Motivation:
– If we didn't know the value of carry-in, what could we do?
– When would we always generate a carry? gi = ai bi
– When would we propagate the carry? pi = ai + bi
• Did we get rid of the ripple?
c1 = g0 + p0c0
c2 = g1 + p1c1 c2 =
c3 = g2 + p2c2 c3 =
c4 = g3 + p3c3 c4 =
Feasible! Why?
• atraso: ent gi pi (1G) gi pi carry (2G)carry saídas (2G)
Carry-lookahead adder
total: 5G independente de n
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-28
• Can’t build a 16 bit adder this way... (too big)• Could use ripple carry of 4-bit CLA adders• Better: use the CLA principle again!
– super propagate (ver pag 243)– super generate (ver pag 245) – ver exercícios 4.44, 45 e 46 (não será cobrado)
Use principle to build bigger adders
CarryIn
Result0--3
ALU0
CarryIn
Result4--7
ALU1
CarryIn
Result8--11
ALU2
CarryIn
CarryOut
Result12--15
ALU3
CarryIn
C1
C2
C3
C4
P0G0
P1G1
P2G2
P3G3
pigi
pi + 1gi + 1
ci + 1
ci + 2
ci + 3
ci + 4
pi + 2gi + 2
pi + 3gi + 3
a0b0a1b1a2b2a3b3
a4b4a5b5a6b6a7b7
a8b8a9b9
a10b10a11b11
a12b12a13b13a14b14a15b15
Carry-lookahead unit
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-29
• More complicated than addition– accomplished via shifting and addition
• More time and more area• Let's look at 3 versions based on gradeschool algorithm
• Negative numbers: convert and multiply– there are better techniques, we won’t look at them
Multiplication
810
910
1000 1001
multiplicandomultiplicador
1000 0000 00001000
produtos parciais
7210 1001000 max= (24–1) *(24–1) = 225
225 > 128 8 bits
32 * 32 bits 64 bits
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-30
Multiplication: Implementation
Done
1. TestMultiplier0
1a. Add multiplicand to product andplace the result in Product register
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
64-bit ALU
Control test
MultiplierShift right
ProductWrite
MultiplicandShift left
64 bits
64 bits
32 bits
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-31
Second Version
MultiplierShift right
Write
32 bits
64 bits
32 bits
Shift right
Multiplicand
32-bit ALU
Product Control test
Done
1. TestMultiplier0
1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register
2. Shift the Product register right 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-32
Final Version
ControltestWrite
32 bits
64 bits
Shift rightProduct
Multiplicand
32-bit ALU
Done
1. TestProduct0
1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register
2. Shift the Product register right 1 bit
32nd repetition?
Start
Product0 = 0Product0 = 1
No: < 32 repetitions
Yes: 32 repetitions
• No MIPS:• dois novos registradores de uso dedicado para multiplicação: Hi e Lo (32 bits cada)• mult $t1, $t2 # Hi Lo $t1 * $t2 • mfhi $t1 # $t1 Hi • mflo $t1 # $t1 Lo
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-33
Algoritmo de Booth (visão geral)
• Idéia: “acelerar” multiplicação no caso de cadeia de “1´s” no multiplicador: 0 1 1 1 0 * (multiplicando) = + 1 0 0 0 0 * (multiplicando) - 0 0 0 1 0 * (multiplicando)
• Olhando bits do multiplicador 2 a 2– 00 nada– 01 soma (final)– 10 subtrai (começo)– 11 nada (meio da cadeia de uns)
• Funciona também para números negativos• Para o curso: só os conceitos básicos• Algoritmo de Booth estendido
– varre os bits do multiplicador de 2 em 2• Vantagens:
– (pensava-se: shift é mais rápido do que soma)– gera metade dos produtos parciais: metade dos ciclos
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-34
Geração rápida dos produtos parciais
Y0 Y1 Y2
X0 X1 X2
X2 Y0 X2 Y1 X2 Y2
X1 Y0 X1 Y1 X1 Y2
X0 Y0 X0 Y1 X0Y2
Y0 Y1 Y2X2
X1
X0
X2 Y0 X2 Y1 X2 Y2
X1 Y2X1 Y1X1 Y0
X0 Y0 X0 Y1 X0 Y2
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-35
Carry Save Adders (soma de produtos parciais)
s4 s3 s2 s1 s0
f0e0b0f1e1b1f2e2b2f3e3b3
a0a1a2a3
s5
c'3 s'3s'4 c'2 s'2 c'1 s'1 c'0 s'0
Carry save adder
E FBA
Carry save adder
Traditional adder
S
C' S'
s5 s0
b0a0
e0
f0
s1
b1a1
e1
f1
s2
b2a2
e2
f2
s3
b3a3
e3
f3
s4
E F
S
BA
Traditional adder
Traditional adder
Traditional adder
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-36
Divisão
29 3 29 = 3 * Q + R = 3 * 9 + 2 dividendo
divisor
quociente
resto
2910 = 011101 310 = 11
0 1 1 1 0 1 1 11 1 0 1 0 0 1
0 0 1 0 11 11 0
Q = 9 R = 2
Como implementar em hardware?
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-37
Alternativa 1: divisão com restauração
29 – 3 * 24 = -19 q4 = 1
-19 + 3 * 24 = 29 q4 = 0 Restauração
29 – 3 * 23 = 5 q3 = 1
5 – 3 * 22 = -7 q2 = 1
-7 + 3 * 22 = 5 q2 = 0 Restauração
5 – 3 * 21 = -1 q1 = 1
-1 + 3 * 21 = 5 q1 = 0 Restauração
5 – 3 * 20 = 2 q0 = 1
q4q3q2q1q0 = 01001 = 9R = 11 = 2
• hardware não sabe se “vai caber ou não”• registrador para guardar resto parcial• verificação do sinal do resto parcial• caso negativo restauração
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-38
Alternativa 2: divisão sem restauração
29 – 3 * 24 = -19 < 0 próx = SOMA q4 = 1
-19 + 3 * 23 = 5 > 0 próx = SUB q3 = 1
5 – 3 * 22 = -7 < 0 próx = SOMA q2 = 1
-7 + 3 * 21 = -1 < 0 próx = SOMA q1 = 1
-1 + 3 * 20 = 2 q0 = 1
Resto = 2 Quociente = 11111 ??
se resto parcial > 0 próxima operação soma
se resto parcial < 0 próxima operação subtraçãoobjetivoR 0
se operação corrente + qi = 1
se operação corrente - qi = 1
Regras
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-39
Alternativa 2: conversão do resultado
)22222(11111 01234
16 - 8 + 4 - 2 - 1
)1()1()1( 2)12(222...11... nnnn
111111101010
• Nº de somas: 3
• Nº de subtrações:2
• Total: 5
• OBS: se resto < 0 deve haver correção de um divisor para que resto > 0
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-40
Comparação das alternativas
29
-19
29
-15
2
29
-19
55 5
-7
2
-1
-7
com
sem
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-41
Hardware para divisão: terceira alternativa
Write
32 bits
64 bits
Shift leftShift right
Remainder
32-bit ALU
Divisor
Controltest
Done. Shift left half of Remainder right 1 bit
Test Remainder
3a. Shift the Remainder register to the left, setting the new rightmost bit to 1
32nd repetition?
Start
Remainder < 0
No: < 32 repetitions
Yes: 32 repetitions
3b. Restore the original value by addingthe Divisor register to the left half of theRemainder register and place the sum
in the left half of the Remainder register.Also shift the Remainder register to theleft, setting the new rightmost bit to 0
2. Subtract the Divisor register from theleft half of the Remainder register andplace the result in the left half of the
Remainder register
Remainder 0
1. Shift the Remainder register left 1 bit
–>
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-42
Instruções
• No MIPS:• dois novos registradores de uso dedicado para multiplicação: Hi e Lo (32 bits cada)• mult $t1, $t2 # Hi Lo $t1 * $t2 • mfhi $t1 # $t1 Hi • mflo $t1 # $t1 Lo
• Para divisão:• div $s2, $s3 # Lo $s3 / $s3 Hi $s3 mod $s3
• divu $s2, $s3 # idem para “unsigned”
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-43
Ponto Flutuante
• Objetivos: – representação de números não inteiros– aumentar a capacidade de representação (maiores ou menores)
• Formato padronizado
1.XXXXXXXXX ..... * 2yyy (no caso geral Byyy)
• No MIPS:
S exp mantissa ou significando
8 23
sinal-magnitude (-1)S F * 2E
exp mantissa
faixa
precisão
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-44
Ponto Flutuante e padrão IEEE 754
S exp mantissa ou significando
8 23
expoente [-128 , 127] se 210 103
128 = 8 + 10 * 12;
2128 = 2(8 + 10 * 12) = 28 * 2(10 * 12) 2 * 1038
overflow Nº > 1038
underflow Nº < 10-38
PADRÃO IEEE 7541.XXXXXXXXXXX
um implícito
mantissa: precisão simples: 23 bits (+1) precisão dupla: 52 bits (+1)
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-45
Padrão IEEE754: bias
Nº = (-1)S (1 + Mantissa) * 2E
Para simplificar a ordenação (sorting): BIAS
0 127 255
exp Bias exp
No padrão: 2 (nE - 1) - 1 = 127
EXP = CAMPOEXP - BIAS
Exemplo: representar - 0,7510 = - (1/2 + 1/4)
- 0,7510 = - 0,112 = -1,11 * 2-1
mantissa = 1000000 ...... (23 bits)
campo expoente: - 1 + 127 = 12610 = 0111 11102
1 0111 1110 1000 0000 0000 0000 0000 000
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-46
Tabela de faixas de representação do IEEE 754
Precisão simples Precisão dupla
Expoente Mantissa Expoente MantissaSignificado
0 0 0 0 0
0 0 0 0 Número não normalizado
1 – 254 qquer 1 – 2046 qquer Número normalizado
255 0 2047 0 infinito
255 0 2047 0 NaN (not a number)
8bits 23(+1) 11 52(+1)
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-47
Soma em ponto flutuante
Done
2. Add the significands
4. Round the significand to the appropriatenumber of bits
Still normalized?
Start
Yes
No
No
YesOverflow orunderflow?
Exception
3. Normalize the sum, either shifting right andincrementing the exponent or shifting left
and decrementing the exponent
1. Compare the exponents of the two numbers.Shift the smaller number to the right until itsexponent would match the larger exponent
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-48
ULA para soma em ponto flutuante
0 10 1 0 1
Control
Small ALU
Big ALU
Sign Exponent Significand Sign Exponent Significand
Exponentdifference
Shift right
Shift left or right
Rounding hardware
Sign Exponent Significand
Increment ordecrement
0 10 1
Shift smallernumber right
Compareexponents
Add
Normalize
Round
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-49
Multiplicação em ponto flutuante
2. Multiply the significands
4. Round the significand to the appropriatenumber of bits
Still normalized?
Start
Yes
No
No
YesOverflow orunderflow?
Exception
3. Normalize the product if necessary, shiftingit right and incrementing the exponent
1. Add the biased exponents of the twonumbers, subtracting the bias from the sum
to get the new biased exponent
Done
5. Set the sign of the product to positive if thesigns of the original operands are the same;
if they differ make the sign negative
1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch4-50
Conjunto de instruções do MIPS para fp
Fig 4.47 Pag 291
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