7/28/2019 10bit Cs DAC
1/35
Sankalp Semiconductor Confidential 1
10 BIT CURRENT STEERING
DAC
Mano Chitra
AshishCharan
7/28/2019 10bit Cs DAC
2/35
Sankalp Semiconductor Confidential 2
SPECIFICATIONS:
No. of I/P bits: 10
Clock frequency:500 MHz
O/P current : ~20mA
Technology: tsmc65nm_8LM
No. of metals used:8
Area of block:131252um2(X=314um,Y=418um)
Vref_18: 1.71-1.89V
avdd: 3-3.6V
7/28/2019 10bit Cs DAC
3/35
Sankalp Semiconductor Confidential 3
CASCODE ARRAY
BIAS
SWITCH + LATCH + DFF
CURRENTSOURCE ARRAY
DECODERCLK DRIVER
LEVEL
SHIFTER
outp
outn
CLOCKTREE
DECODER
inclk pd
res
iref
vref
avss avdd
dvdddvss
FLOORPLAN:
7/28/2019 10bit Cs DAC
4/35
Sankalp Semiconductor Confidential 4
POWER ROUTING:
avdd
avss
dvdddvss
7/28/2019 10bit Cs DAC
5/35
Sankalp Semiconductor Confidential 5
MAJOR BLOCKS:
Digital Logic:
10 I/P bits
o 3 Binary I/Ps
o 7 I/Ps thermometrically decoded into 127 bits
Thermometric decoder has a 3to7 and 4to15
decoder which gives I/Ps to an array of 127
decoders Total 130 I/Ps given to DFF followed by latch to
give 260 control signals(complementary)
7/28/2019 10bit Cs DAC
6/35
Sankalp Semiconductor Confidential 6
Switch block:
130 pair of complementary switches controlled
by input signals from latch
Here switches are 16u width pmos
Currents from the 130 current sources are given
to respective pair of switches
These differential switches give the final O/Pcurrent corresponding to the digital I/P
7/28/2019 10bit Cs DAC
7/35
Sankalp Semiconductor Confidential 7
Current source:
This is the most critical block of CS DAC
There are 130 current sources each with a
source transistor and a cascode transistor
Out of 130, 3 are binary sources with 1x,2x and
4x multipliers
Rest 127 have 8x multiplier each
So it amounts to total 1023 individualsources[(127x8)+4+2+1=1023]
7/28/2019 10bit Cs DAC
8/35
Sankalp Semiconductor Confidential 8
Continued...
Both current source and cascode have sameno. of multipliers
The 130 drain currents of these cascode are
given to the O/P switches
Bias Block:
This block generates the gate signals for
Current source and Cascode
It has a five pack opamp and a folded cascode
amplifier
7/28/2019 10bit Cs DAC
9/35
Sankalp Semiconductor Confidential 9
Tie Vss:
It is a low signal which is connected to all the
switches to activate them instead of avss so as
to avoid Antenna Effect which can be present if
avss is routed to all the gates of switches.
Level Shifter:
To generate enable signal
7/28/2019 10bit Cs DAC
10/35
Sankalp Semiconductor Confidential 10
Clock driver:
Clock frequency:500 Mhz
It is driven through 5 stages of increasing load
It is given as clkp and clkn to 130 DFF and clkp
to 130 latches
Routing Cap on clkp and clkn should not
exceed 120fF each
7/28/2019 10bit Cs DAC
11/35
Sankalp Semiconductor Confidential 11
GENERAL GUIDELINES:
Follow EM rule for Average or rms current as
the customer specifies
Follow DFM rules for routing also in case of
DFM transistors
A layer called R_rule_analog has to cover all
the DFM transistors for tool understanding
7/28/2019 10bit Cs DAC
12/35
Sankalp Semiconductor Confidential 12
CURRENT SOURCE MATCHING:
Q2 Random pair algorithm is followed to form a
matching pattern for the 130 current sources.
As mentioned 1023 multipliers is rounded off to
1024 with one dummy
This 1024 is distributed into a 32x32 matrix
Here a 8x16=128 forms a unit cell that is flipped
and repeated 8 times to form 1024 Out of this 128 in each unit cell,127 belong to
the unary 127 sources
7/28/2019 10bit Cs DAC
13/35
Sankalp Semiconductor Confidential 13
Continued:
So this 127 repeated in 8 unit cells form 127*8x
multipliers
The binary sources 1x,2x and 4x and the 1
dummy are distributed one in each of the 8x16unit cell
The same pattern is followed for cascode array
also Each individual source of 1024 carries 20uA
Total O/P current is ~20mA
7/28/2019 10bit Cs DAC
14/35
Sankalp Semiconductor Confidential 14
CASCODE vs CS
W/L of cascode is only more than half of CS
transistors
The length of Current source transistor is more
to increase the Rds Value which can beachieved by increasing the length
7/28/2019 10bit Cs DAC
15/35
Sankalp Semiconductor Confidential 15
CONSTRAINTS IN CS BLOCK:
Matching of Current source transistors is very
critical
So CS and cascode transistors are placed in
separate arrays because their sizes aredifferent
Cap on drain line of CS should be minimum
As the total output Current coming from CS-DAC is drawn from VDD itself ,this connection
needs to be strong.
7/28/2019 10bit Cs DAC
16/35
Sankalp Semiconductor Confidential 16
Continued...
This VDD has to be routed in Highest metal in a
mesh type because it will be having lowest
resistivity so that all Vgs drop will be same to all
transistors and tapped to each transistor In each column of 32 transistors 16 are
repeated twice.So only 16 drain lines are routed
over the transistors
M4 and M6 are alternately used for this
Now there is straight one to one connection
from CS drain to cascode source line
7/28/2019 10bit Cs DAC
17/35
Sankalp Semiconductor Confidential 17
Continued...
Cascode transistor orientation is changed to
match with the aspect ratio of CS array
In cascode 16 Source and 16 Drain lines are
running alternately over the device in each of 32column
M6 is used for the drain connection
There are 130 horizontal M5 lines below thecascode and all drains are tapped respectively
All the M6 drain lines are extended for equal
length to match the cap
7/28/2019 10bit Cs DAC
18/35
Sankalp Semiconductor Confidential 18
Continued...
Cap between Drain of CS and VDD needs to be
reduced.So atleast 2 metal difference is needed
VDD rou t ing:
Opt ion 1: Take VDD at centre and form tree like
structure.Here R variation will be same but R will
be more
Option 2:If VDD is on both sides R is less butvariations are not same.Here this is fine
7/28/2019 10bit Cs DAC
19/35
Sankalp Semiconductor Confidential 19
Continued...
A 4 contact wide P strap has to be run between
CS array and cascode array and between
cascode and switch
Guard ring inside CS and Cascode array is 2contact wide
Dummies are placed on all the 4 sides of both
CS and cascode array
7/28/2019 10bit Cs DAC
20/35
Sankalp Semiconductor Confidential 20
SWATCH BLOCK:
Switch,switchbar,latch and DFF form a unit cell
This is done so that there is one to one
connection from DFF to latch and to switch and
there is less crossing of CLK and data
All the 130 swatch units are placed in 1*130
fashion and currents tapped from horizontal
lines
O/P current lines are taken in highest metal
The binary switches have additional pass
transistors tied to tie-vss and are always on
7/28/2019 10bit Cs DAC
21/35
Sankalp Semiconductor Confidential 21
Screenshot of Swatch placement
7/28/2019 10bit Cs DAC
22/35
Sankalp Semiconductor Confidential 22
Continued...
They are placed on the top corner of this switch
array
Its advisable not to stretch the 130 horizontal
lines over these binary devices as it wouldinduce cap mismatch among the 130 lines
Bulk of switch is Vref
16u switch is divided into 4 row of 4u fingereach
P strap has to be run in between each row of 4u
wide switch
7/28/2019 10bit Cs DAC
23/35
Sankalp Semiconductor Confidential 23
CLOCK:
Clock routing cap should not exceed 120fF
Clock is routed in M7 (one less than top metal)
with sufficient width to minimise RC(here width
is 0.12u) Clock driver is placed in bottom corner and a
channel is provided for clock in between the
decoder so that it data crossing is less
From that point it is routed as a tree structure
for 130 DFF
7/28/2019 10bit Cs DAC
24/35
Sankalp Semiconductor Confidential 24
BIAS BLOCK:
Vref and Iref do not need shielding but channel
has to be made for them between the blocks
Since res is going to pad a 200ohm resistor is
included in the design and normal layoutpractice is enough and a Nwell guard ring for
this resistor
If resistor is not there then snap back style has
to be used
7/28/2019 10bit Cs DAC
25/35
Sankalp Semiconductor Confidential 25
DECAPS:
Decaps are used to stabilise the power lines
from fluctuations and mainly in digital circuits
(High switching will be there) which means
device requires power immediately ,so if VDDpin is so far from the device then it takes much
time and more IR drop also will be there before
reaching Device itself .
Therefore these DECAPS will be helpful in
supplying immediate power to the Devices
instead from main VDD .
7/28/2019 10bit Cs DAC
26/35
Sankalp Semiconductor Confidential 26
Continued...
So always place DECAPS near to the Devices
instead of keeping all Decaps at a place in
Layout.
UNITCELL of Decap has to be made in afashion such that if we give i/p to one unit cell
all Decaps will get the i/p and Resistance Drop
has to be made very less
Here decap of 50pF between avdd and avss
and decap of 20pF between dvdd and dvss is
needed in this design
7/28/2019 10bit Cs DAC
27/35
Sankalp Semiconductor Confidential 27
POWER PLOT:AVDD
7/28/2019 10bit Cs DAC
28/35
Sankalp Semiconductor Confidential 28
POWER PLOT:AVSS
7/28/2019 10bit Cs DAC
29/35
Sankalp Semiconductor Confidential 29
POWER PLOT:DVDD
7/28/2019 10bit Cs DAC
30/35
Sankalp Semiconductor Confidential 30
POWER PLOT:DVSS
7/28/2019 10bit Cs DAC
31/35
Sankalp Semiconductor Confidential 31
LESSONS LEARNT:
Pins in schematic should not be named as mere
numbers that will create extraction error
For all analog signals maintain twice or thrice of
minimum width although minimum widthsatisfies more than EM
Special characters other than _ should not be
there in layout name even if it is there in
schematic name
7/28/2019 10bit Cs DAC
32/35
Sankalp Semiconductor Confidential 32
Continued...
If view name is "layout_..." instead of "layout" then
RC extraction tool cannot take this view
while exporting gds it will have extra binary
information due to this view name change
complicated for others to understand which is
the final layout
7/28/2019 10bit Cs DAC
33/35
Sankalp Semiconductor Confidential 33
REVIEW INPUTS AND CHANGES:
There was lot of coupling between the 130 out lineswhen they were all in same metal
So we made it alternate M3 and M5
But in this case symmetry wont be there in cap So every line is made half M3 and half M5 and this
is used alternately which reduced the coupling from
50fF to 2fF
M5M3
M5 M3
7/28/2019 10bit Cs DAC
34/35
Sankalp Semiconductor Confidential 34
Continued:
Also the vertical drain lines from cascode arechanged to M6 and M7 alternately
Since anyway the pattern is flipped and repeated 8
times symmetry will be maintained in the drain
routing even when we use 2 alternate metals
7/28/2019 10bit Cs DAC
35/35
Sankalp Semiconductor Confidential 35
Some good Layout practices...
Create unit cell wherever possible so that future
changes will be in only one place
Make cell (instances) wherever possible even
for routing lines so that top level changes willnot affect these
Minimise top level connections as much as
possible
Top Related