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Worst-case Delay Analysis Considering the Variability of Transistors and Interconnects
Takayuki Fukuoka, Tsuchiya Akira and Hidetoshi Onodera
Kyoto University
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Outline Motivation Worst-delay Analysis Classification of the Worst-delay
Direction Conclusions
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Motivation Technology scaling
Increasing significance of variation Transistor and Interconnect variations affect
delay variation Gate length, width etc. Metal width, ILD (inter layer dielectric) etc.
Worst-delay corner depends on many parameters (Drive strength, Interconnect length etc.)
Where is the worst-delay corner?How the corner changes?
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Outline Motivation Worst-delay Analysis
Interconnect Model Delay Model Worst-delay Corner Case Study
Classification of the Worst-delay Direction
Conclusions
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Interconnect Model
Interconnect structure variation (W, T and H) Pitch (S+W) is constant
R, C and RC variations Not statistically
independent of R and C variations As R increases,
C decreases Cross section model for interconnects
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R and C variations
C variation[%]
R v
aria
tion[
%]
C max
R max RC max
ITRS2005 80nm IntermediateW, T, H 3σ=20%
C max Interconnect becomes thick (W+, T+, H-)
R and RC max Interconnect becomes thin (W-, T-, H-)
Wider Spacing C variation decreases R variation does not
change
C variation[%]R
var
iatio
n[%
]
C max
R max RC max
S=W S=3W
Opposite direction
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Delay Model
trR
)(7.04.0 LLtrtr RCCRCRRCD
[S.Sakurai, IEEE trans. ’93]Delay formula of a RC distributed line
Transistor variation Rtr variation Interconnect variation W, T, H variations
CR
LC
Every part of the interconnect is uniformly fluctuated
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Delay Variation Model
Delay is linear combination of parameters
W, T, H and Rtr are normally distributed
Delay is normally distributed Statistical worst-delay is
)()()()( 00000 trtr RRR
DHH
H
DTT
T
DWW
W
DDD
DD 30
: nominal value : standard deviation0D D
0D DD 30 DD 30
9%203
width%203 %203
%203 thickness
...,30
TW
DWW
D
WW
Normalization
Worst-delay corner( )
Worse-delay Corner
)71.0,71.0(
,
T
D
W
D
D
T
D
W
relative values of sensitivity coefficientstr
tr
R
trtr
trD
R
HD
H
TD
T
DD
W
D
RR
R
DHH
H
DTT
T
DWW
W
DDD
00000
DD 30
0D DD 30 DD 30
(W-14%, T-14%)
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Case Study
ITRS2005 80nm High performance model: Intermediate Interconnect:
W, T, H and Rtr variations: Realistic Drive strength and Interconnect
length Optimally-buffered interconnect length: 94um Optimal drive strength: 32X
buffer
Optimum length
3900trR fF42.0LC/um8.1 R fF/um19.0C
%203
120trR fF13LC
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Experimental Results(drive strength)
Drive strength: 1X Drive strength: 32X
width
thickness
10%
7%
-2%
-8%
Opposite direction
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Experimental Results (Spacing)
Spacing: S=3WDrive strength: 1X
Wider spacing
W and T effects (C effect) become small
Worst-delay corner depends on many parameters (drive strength, spacing, etc.)
Spacing: S=WDrive strength: 1X
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Outline Motivation Worst-delay Analysis Classification of the Worst-delay
Direction Conclusions
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Idea of Classification Worst-delay Direction
Interconnect becomes thick (W+, T+) or thin (W-, T-)
Dominant factor C: interconnect thick delay increases R, RC: interconnect thin delay
increases)(7.04.0 LLtrtr RCCRCRRCD
We compare the proportion of each term
The largest term is the dominant factor
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Example of C-dominant case
)(7.04.0 LLtrtr RCCRCRRCD
C dominant Second term (RtrC) > Forth term
(RCL) Drive strength is small. As interconnect becomes thick
(C increases), delay increases. Rtr also affects delay
RC dominant Long interconnect As Interconnect becomes thin (R
increases), delay increases.
Drive strength:1 X Spacing: S=WC dominant
RC dominant
1
1 42
2
3
3
4
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Example of R-and RC-dominant case
large drive strength
Rtr decreases and CL increases(RtrC decreases and RCL increases)
As interconnect becomes thin, delay increases.
Drive strength:32X Spacing: S=W
Optimum drive strength
RC dominantR dominant )(7.04.0 LLtrtr RCCRCRRCD
Ltr RCCR
1
2
2
31 4
3
4
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Intermediate vs. Global
Intermediate (thin) Global (thick)
Global: R is smallR and RC dominant regions become smaller.
The boundary of each dominant region changes depending on layer
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Minimum Spacing vs. Wider Spacing
Spacing: S=W Spacing: S=3W
Wider spacingC variation becomes smaller.C dominant regions become smaller.
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Conclusions We propose a criterion for classifying the
worst-delay direction Worst-delay corner is context-dependent
Small drive strength: Thicker interconnect worst-delay
Large drive strength or long interconnect: Thinner interconnect worst-delay
This criterion is used as a guideline for the selection of interconnect parasitic values used for the worst-delay calculation.
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