1
COMP541
Datapath &Single-Cycle MIPS
Montek Singh
Mar 25, 2015
Topics Complete the datapath Add control to it Create a full single-cycle MIPS!
ReadingChapter 7Review MIPS assembly language
Chapter 6 of course textbookOr, Patterson Hennessy (inside front flap)
A MIPS CPU
3
MIPS CPUInstr
MemoryData
Memory
pc
instr
memwrite
dataaddr
readdata
writedata
clk clkreset
Top-Level: MIPS CPU + memories
4
MIPS CPUInstr
MemoryData
Memory
pc
instr
memwrite
dataaddr
readdata
writedata
clk clkreset
clkreset
We will add I/O devices (display, keyboard, etc.) later
Top-level module
One level down: Inside MIPS Datapath: components that store or process data
registers, ALU, multiplexors, sign-extension, etc. we will regard memories as outside the CPU, so not part of the core
datapath
Control: components that tell datapath what to do and when control logic (FSMs or combinational look-up tables)
MIPS CPU
Control
ALUFN,regwrite,regdst…
opcode,func, flagZ …
MIPS Datapath
InstrMemory
DataMemory
pc
instr
memwrite
dataadr
readdata
writedata
clk
reset
clk
Review: MIPS instruction types
Three instruction formats:R-Type: register operands I-Type: immediate operand J-Type: for jumps
6
Review: Instruction Formats
op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Type
op rs rt imm6 bits 5 bits 5 bits 16 bits
I-Type
op addr6 bits 26 bits
J-Type
R-Type instructions Register-type
3 register operands:rs, rt: source registersrd: destination register
Other fields:op: the operation code or opcode (0 for R-type
instructions)funct: the function
– together, op and funct tell the computer which operation to perform
shamt: the shift amount for shift instructions, otherwise it is 0
op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Type
R-Type Examples
add $s0, $s1, $s2
sub $t0, $t3, $t5
Assembly Code
0 17 18 16 0 32
Field Values
0 11 13 8 0 34
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
000000 10001 10010 10000 00000 100000
op rs rt rd shamt funct
000000 01011 01101 01000 00000 100010
Machine Code
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
(0x02328020)
(0x016D4022)
Note the order of registers in the assembly code:
add rd, rs, rt
I-Type instructions Immediate-type
3 operands:op: the opcoders, rt: register operands imm: 16-bit two’s complement immediate
op rs rt imm6 bits 5 bits 5 bits 16 bits
I-Type
I-Type Examples
Assembly Code
8 17 16 5
Field Valuesop rs rt imm
6 bits 5 bits 5 bits 16 bits
addi $s0, $s1, 5
addi $t0, $s3, -12
lw $t2, 32($0)
sw $s1, 4($t1)
8 19 8 -12
35 0 10 32
43 9 17 4
(0x22300005)
(0x2268FFF4)
(0x8C0A0020)
(0xAD310004)
001000 10001 10000 0000 0000 0000 0101
op rs rt imm
Machine Code
6 bits 5 bits 5 bits 16 bits
001000 10011 01000 1111 1111 1111 0100
100011 00000 01010 0000 0000 0010 0000
101011 01001 10001 0000 0000 0000 0100
Note the differing order of registers in the assembly and machine codes:
addi rt, rs, imm
lw rt, imm(rs)
sw rt, imm(rs)
J-Type instructions Jump-type
26-bit address operand (addr)Used for jump instructions (j)
op addr6 bits 26 bits
J-Type
Summary: Instruction Formats
op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Type
op rs rt imm6 bits 5 bits 5 bits 16 bits
I-Type
op addr6 bits 26 bits
J-Type
MIPS State Elements
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CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
CLK
32 3232 32
32
32
32 32
32
32
5
5
5
We will fill out the datapath and control logic for basic single cycle MIPS• first the datapath• then the control logic
MIPS Design from Comp411
We will not be implementing the textbook version of MIPS in our labs.
Instead, we will implement the MIPS design from Comp411, which has more features.
15
Design Approach“Incremental Featurism”
We will implement circuits for each type of instruction individually, and merge them (using MUXes, etc).
Our Bag of Components:
Registers
0 1 Muxes
ALUA B ALU & adders
DataMemory
WD
A
RD
R/W
RegisterFile
(3-port)
RA1 RA2
WA
WE
WD
RD1 RD2
InstructionMemory
A
D
Memories
+
Steps: 1. 3-Operand ALU instrs 2. ALU w/immediate instrs 2. Loads & Stores 3. Jumps & Branches 4. Exceptions (briefly)
Review: The MIPS ISA
Instruction classesdistinguished by types:1) 3-operand ALU2) ALU w/immediate3) Loads/Stores4) Branches5) Jumps
Instruction classesdistinguished by types:1) 3-operand ALU2) ALU w/immediate3) Loads/Stores4) Branches5) Jumps
The MIPS instruction set as seen from a Hardware Perspective
OP
6 5 5 5 5 616
26
000000 rs rt rd funcshamt
R-type: ALU with Register operands Reg[rd] Reg[rs] op Reg[rt]
001XXX rs rtimmediate
I-type: ALU with constant operandReg[rt] Reg[rs] op SEXT(immediate)
10X011 rs rtimmediate
I-type: Load and StoreReg[rt] Mem[Reg[rs] + SEXT(immediate)]Mem[Reg[rs] + SEXT(immediate)] Reg[rt]
I-type: Branch Instructionsif (Reg[rs] == Reg[rt]) PC PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC PC + 4 + 4*SEXT(immediate)
10X011immediate
rs rt
00001X 26-bit constant J-type: jump
PC (PC & 0xf0000000) | 4*(immediate)
Fetching Sequential Instructions
P
C
4
We will talk about branches and jumps later.
register
+
32
32
Read
AddressInstruction
Instruction
Memory
32
32
Instruction Fetch/Decode Use a counter to FETCH
the next instruction: PROGRAM COUNTER (PC)
use PC as memory address
add 4 to PC, load new value at end of cycle
fetch instruction from memory
use some instruction fields directly (register numbers, 16-bit constant)
decode rest of the instruction
use bits <31:26> and <5:0> to generate controls
INSTRUCTIONWORDFIELDS
PC
+4
InstructionMemory
A
D
Control Logic
CONTROL SIGNALS
00
OP[31:26], FUNC[5:0]
32
32
32
3-Operand ALU Data Path
RegisterFile
RA1 RA2
RD1 RD2
WA WD
WE
Rd: <15:11>
PC
+4
InstructionMemory
A
D
Rt: <20:16>
ALUA B
ALUFN
Control Logic
WERF
ALUFN
WERF
00
32 32
32
Rs: <25:21>
000000 rs rt rd 100XXX00000
R-type: ALU with Register operands Reg[rd] Reg[rs] op Reg[rt]
WERF!
Shift Instructions
RegisterFile
RA1 RA2
RD1 RD2
WA WD
WE
Rd: <15:11>
PC
+4
InstructionMemory
A
D
Rt: <20:16>
ALUA B
ALUFN
Control Logic
WERF
ALUFN
WERF
00
32
000000 rs rt rd 000XXXshamt
R-type: ALU with Register operands sll: Reg[rd] Reg[rt] (shift) shamtsllv: Reg[rd] Reg[rt] (shift) Reg[rs]
ASEL
Rs: <25:21>
ASEL10
shamt:<10:6>
ASEL!
ALU with Immediate
WA
PC
+4
InstructionMemory
A
D
Rt: <20:16>
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
ALUFN
BSEL01
imm: <15:0>
BSEL
WERF
WERF
00
BSEL!
001XXX rs rtimmediat
e
I-type: ALU with constant operandReg[rt] Reg[rs] op SEXT(immediate)
Rd:<15:11>
Rt:<20:16>0
1
SEXTSEXT
SEXT
ASEL
BSEL
Rs: <25:21>
ASEL10
shamt:<10:6>
How do you build SEXT?• 1 pad with sign• 0 pad with 0s
Load Instruction
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Imm: <15:0>
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
WERF
WERF
00
32
32
Rd:<15:11>
Rt:<20:16>0
1
BSEL
SEXT
100011 rs rtimmediat
e
I-type: LoadReg[rt] Mem[Reg[rs] + SEXT(immediate)]
ASEL
Rt: <20:16>Rs: <25:21>
SEXT
BSEL01
SEXT
ASEL10
shamt:<10:6>
Store Instruction
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Imm: <15:0>
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
WERF
WERF
00
32
Rd:<15:11>
Rt:<20:16>0
1
SEXT
ASEL
10X011 rs rtimmediat
e
I-type: StoreMem[Reg[rs] + SEXT(immediate)] Reg[rt]
Rt: <20:16>
BSEL
No WERF!
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
JMP Instructions
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
00001X 26-bit constant
J-type: j: PC (PC & 0xf0000000) | 4*(immediate) jal: PC (PC & 0xf0000000) | 4*(immediate);
Reg[31] PC + 4
PC<31:28>:J<25:0>:00
WASEL
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
PCSEL 0123
WASEL
Rd:<15:11>Rt:<20:16> 0
1231
BEQ/BNE Instructions
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
10X011immediat
ers rt
R-type: Branch Instructionsif (Reg[rs] == Reg[rt]) PC PC + 4 + 4*SEXT(immediate)if (Reg[rs] != Reg[rt]) PC PC + 4 + 4*SEXT(immediate)
+x4
BT
Z
Z
BT
PC<31:28>:J<25:0>:00
Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction.
That “x4” unit is trivial. I’ll just wire the input shifted over 2–bit positions.
WASEL
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
WASEL
Rd:<15:11>Rt:<20:16>
31
012
PCSEL 0123
Jump Indirect Instructions
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
R-type: Jump Indirect, Jump and Link Indirectjr: PC Reg[rs]jalr: PC Reg[rs], Reg[rd] PC + 4
Z
Z
BT
WASEL
PC<31:28>:J<25:0>:00
000000 rs rt rd 00100X00000
JT
JT
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
WASEL
Rd:<15:11>Rt:<20:16>
31
012
BT
+x4
PCSEL 0123
Comparisons
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < SEXT(imm)) Reg[rt] 1; else Reg[rt] 0 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt] 1; else Reg[rt] 0
Z
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
001XXXimmediat
ers rt
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
Rd:<15:11>Rt:<20:16>
WASEL
31
012
BT
+x4
PCSEL 0123
More comparisons
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd] 1; else Reg[rd] 0 sltu: if (Reg[rs] < Reg[rt]) Reg[rd] 1; else Reg[rd] 0
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
000000 rs rt rd 10101X00000
Z
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
Rd:<15:11>Rt:<20:16>
BT
+x4
WASEL
31
012
PCSEL 0123
LUI
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
I-type: Load upper immediate lui: Reg[rt] Immediate << 16
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
Z
001XXXimmediat
e00000
rt
Rs: <25:21>
SEXT
BSEL01
SEXT
Rd:<15:11>Rt:<20:16>
ASEL20
shamt:<10:6>
“16”
1
WASEL
31
012
BT
+x4
PCSEL 0123
Reset, Interrupts, and Exceptions Upon reset/reboot:
Need to set PC to where boot code resides in memory Interrupts/Exceptions:
any event that causes interruption in program flow FAULTS: e.g., nonexistent opcode, divide-by-zero TRAPS & system calls: e.g., read-a-character I/O events: e.g., key pressed
How to handle? interrupt current running program invoke exception handler return to program to continue execution
Registers $k0, $k1 ($26, $27) reserved for operating system (kernel), interrupt handlers any others used must be saved/restored
Exceptions
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data Memory
RD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
Z
Rs: <25:21>
SEXT
BSEL01
SEXT
PCSEL 0123456
IRQ
0x800000800x800000400x80000000
RESET
IRQ: Reg[27] PC+4; PC 0x80000080Bad Opcode: Reg[27] PC+4; PC 0x80000040Reset: PC 0x80000000
ASEL20
shamt:<10:6>
“16”
1
WASEL
Rd:<15:11>Rt:<20:16>
0123
3127
BT
+x4
Exceptions: Our Lab Version We will not implement exceptions
But: hardwire a “Reset” input which sets PC to 0, so it starts over
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
Z
Rs: <25:21>
SEXT
BSEL01
SEXT
PCSEL 0123
RESET
Reset: PC 0
ASEL20
shamt:<10:6>
“16”
1
WASEL
Rd:<15:11>Rt:<20:16> 0
1231
BT
+x4
MIPS: Our Final VersionThis is a complete 32-bit processor.Although designed in “one” class lecture,it executes the majority of theMIPS R2000 instruction set.
Executes one instruction per clock
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WD
WE
ALUFN
Control Logic
Data Memory
RD
WD R/W
Adr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32
(PC+4)
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
Z
Rs: <25:21>
SEXT
BSEL01
SEXT
Rd:<15:11>Rt:<20:16>
ASEL20
shamt:<10:6>
“16”
1
WASEL
31
012
BT
+<<2
PCSEL 0123
RESET
pc instr
mem_addr
mem_wr
mem_readdata
mem_writedata
ReadData1
alu_result
reg
_wri
tead
dr
signImm
aluA
ReadData2
reg_writedata
aluB
Wr
pcPlus4
pcPlus4
newPC
MIPS Control The control unit can be built as a large look-up
table/ROM or, a case statement in Verilog!
Instruction
PCSEL
SEXT
WASEL
WDSEL
ALUFN
Sub Bool Shift Math
WR
WERF
ASEL
BSEL
add 0 x 0 1 0 xx
0 1 0 1 0 0
sll
andi
lw
sw
beq
…
Review: Our “full feature” ALU Our ALU from Lab 3 (with support for
comparisons)
Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B 1 X0 1 1 A LT B 1 X1 1 1 A LTU B X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B
5-bit ALUFN
A B
Result
BidirectionalShifter
BooleanAdd/SubSub
Bool
Shft
Math
1 0
1 0
ZFlag
FlagsN,V,C
Bool0
0 1
<?
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Summary We learned about a complete MIPS CPU NOTE: Many details in textbook are different…
… from what you will implement in the labour lab MIPS has more features
Next class:We will look at performance of single-cycle MIPSWe will look at multi-cycle MIPS to improve
performance
Next lab: Implement single-cycle CPU!
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