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AVRAVR
Session 2Session 2
Master : Dr.jafariMaster : Dr.jafariAuthors: Authors:
M.H EdrisiM.H Edrisi, , [email protected] [email protected]
Last Session Summary
What Is AVR?What Is AVR?
What is microcontrollerWhat is microcontroller
Microcontroller vs Microcontroller vs MicroprocessorMicroprocessor
Some of the benefits of µCSome of the benefits of µC
MicrocontrollerMicrocontroller
AVR Powered ProductsAVR Powered Products
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The History of AVRThe History of AVRAVR was developed in the year 1996 by Atmel Corporation
The architecture of AVR was developed byAlf-Egil Bogen and Vegard Wollan
Alf-Egil Bogen Vegard Wollan RISC microcontroller
The AT90S8515 was the first microcontroller which was based on AVR architecture
first microcontroller was AT90S1200AT90S1200 in the year 1997.
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AVRs are generally classified into six broad groups:
tinyAVR — the ATtiny series
megaAVR — the ATmega seriesCheap
XMEGA — the ATxmega series
Application-specific AVR
FPSLIC (AVR with FPGA)
32-bit AVRs
Basic Families
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TinyAVR – Less memory, small size, suitable only for simpler application
6–32-pin package
0.5–8 kB program memory
Limited peripheral set
Basic Families(tinyAVR)
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MegaAVR – These are the most popular ones having good amount of memory (upto 256 KB), higher number of inbuilt peripherals and suitable for moderate to complex applications.
4–256 kB program memory
28–100-pin package
Extended instruction set (Multiply instructions and instructions for handling larger program memories)
Extensive peripheral set
Basic Families(megaAVR)
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XmegaAVR – Used commercially for complex applications, which require large program memory and high speed.4–256 kB program memory
16–384 kB program memory
44–64–100-pin package (A4, A3, A1)
Extended performance features, such as DMA, "Event System", and cryptography support.
Extensive peripheral set with DACs
Basic Families(XMEGA)
Other FamiliesOther FamiliesApplication-specific AVR
megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN etc.
FPSLIC (AVR with FPGA) FPGA 5K to 40K gates SRAM for the AVR program code, unlike all other AVRs AVR core can run at up to 50 MHz
32-bit AVRs
In 2006 Atmel released microcontrollers based on the new, 32-In 2006 Atmel released microcontrollers based on the new, 32-bit, bit, AVR32 architecture. They include architecture. They include SIMD and and DSP instructions, along instructions, along with other audio and video processing features. This 32-bit family of devices with other audio and video processing features. This 32-bit family of devices is intended to compete with the is intended to compete with the ARM based processors. The instruction set based processors. The instruction set is similar to other RISC cores, but is not compatible with the original AVR or is similar to other RISC cores, but is not compatible with the original AVR or any of the various ARM cores.any of the various ARM cores.
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InformationSeries NameSeries Name PinsPins Flash MemoryFlash Memory Special FeatureSpecial Feature
TinyAVRTinyAVR 6-326-32 0.5-8 KB0.5-8 KB Small in sizeSmall in sizeMegaAVRMegaAVR 28-10028-100 4-256KB4-256KB Extended Extended
peripheralsperipherals
XmegaAVRXmegaAVR 44-10044-100 16-384KB16-384KB DMA , Event DMA , Event System includedSystem included
8051 PIC AVRSPEED Slow Moderate FastMEMORY Small Large LargeARCHITECTURE CISC RISC RISC
ADC Not Present Inbuilt InbuiltTimers Inbuilt Inbuilt InbuiltPWM Channels Not Present Inbuilt Inbuilt
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ATmega32
ATmega32
ATmelATmel
32KB Flash Programming Memory32KB Flash Programming Memory
megaAVRmegaAVR
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FeaturesFeatures1.1. High-performance, Low-power AVR® 8-bit High-performance, Low-power AVR® 8-bit
MicrocontrollerMicrocontroller
2.2. Advanced RISC ArchitectureAdvanced RISC Architecture
3.3. High Endurance Non-volatile Memory segmentsHigh Endurance Non-volatile Memory segments
4.4. JTAG (IEEE std. 1149.1 Compliant) InterfaceJTAG (IEEE std. 1149.1 Compliant) Interface
5.5. Peripheral FeaturesPeripheral Features
6.6. Special Microcontroller FeaturesSpecial Microcontroller Features
7.7. I/O and PackagesI/O and Packages
8.8. Operating Voltages Operating Voltages
9.9. Speed GradesSpeed Grades
10.10. Power Consumption at 1 MHz, 3V, 25Power Consumption at 1 MHz, 3V, 25°°C for C for ATmega32LATmega32L
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AVR ArchitectureAVR Architecture
Advanced RISC ArchitecturAdvanced RISC Architectur
131 Powerful Instructions – Most Single-clock 131 Powerful Instructions – Most Single-clock Cycle ExecutionCycle Execution
32 x 8 General Purpose Working Registers32 x 8 General Purpose Working Registers
Fully Static OperationFully Static Operation
Up to 16 MIPS Throughput at 16 MHzUp to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle MultiplierOn-chip 2-cycle Multiplier
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High Endurance Non-volatile Memory segmentsHigh Endurance Non-volatile Memory segments
Boundary-scan Capabilities According to the JTAG Boundary-scan Capabilities According to the JTAG StandardStandard
Extensive On-chip Debug SupportExtensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG InterfaceBits through the JTAG Interface
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JTAG (IEEE std. 1149.1 Compliant) InterfaceJTAG (IEEE std. 1149.1 Compliant) Interface
131 Powerful Instructions – Most Single-clock 131 Powerful Instructions – Most Single-clock Cycle ExecutionCycle Execution
32 x 8 General Purpose Working Registers32 x 8 General Purpose Working Registers
Fully Static OperationFully Static Operation
Up to 16 MIPS Throughput at 16 MHzUp to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle MultiplierOn-chip 2-cycle Multiplier
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Peripheral FeaturesPeripheral Features
Two 8-bit Timer/Counters with Separate Prescalers Two 8-bit Timer/Counters with Separate Prescalers and Compare Modesand Compare Modes
One 16-bit Timer/Counter with Separate Prescaler, One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and CaptureModeCompare Mode, and CaptureMode
Real Time Counter with Separate OscillatorReal Time Counter with Separate Oscillator
Four PWM ChannelsFour PWM Channels
8-channel, 10-bit ADC8-channel, 10-bit ADC
8 Single-ended Channels8 Single-ended Channels
7 Differential Channels in TQFP Package Only7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x1x, 10x, or 200x
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Peripheral Features(2)Peripheral Features(2)
Byte-oriented Two-wire Serial InterfaceByte-oriented Two-wire Serial Interface
Programmable Serial USARTProgrammable Serial USART
Master/Slave SPI Serial InterfaceMaster/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-Programmable Watchdog Timer with Separate On-chip Oscillatorchip Oscillator
On-chip Analog ComparatorOn-chip Analog Comparator
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Special Microcontroller FeaturesSpecial Microcontroller Features
Power-on Reset and Programmable Brown-out Power-on Reset and Programmable Brown-out DetectionDetection
Internal Calibrated RC OscillatorInternal Calibrated RC Oscillator
External and Internal Interrupt SourcesExternal and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, StandbyPower-save, Power-down, Standby
and Extended Standbyand Extended Standby
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AVR ArchitectureAVR Architecture
I/O and PackagesI/O and Packages
32 Programmable I/O Lines32 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, and 44-pad 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLFQFN/MLF
Operating VoltagesOperating Voltages
2.7 - 5.5V for ATmega32L2.7 - 5.5V for ATmega32L
– – 4.5 - 5.5V for ATmega324.5 - 5.5V for ATmega32
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AVR ArchitectureAVR Architecture
Speed GradesSpeed Grades
0 - 8 MHz for ATmega32L0 - 8 MHz for ATmega32L
0 - 16 MHz for ATmega320 - 16 MHz for ATmega32
Power Consumption at 1 MHz, 3V, 25°C for Power Consumption at 1 MHz, 3V, 25°C for ATmega32LATmega32L
Active: 1.1 mAActive: 1.1 mA
Idle Mode: 0.35 mAIdle Mode: 0.35 mA
Power-down Mode: < 1 Power-down Mode: < 1 μμAA
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