CMOS Inverter
A THOUGHT EXPERIMENT
CMOS Inverter
5. COMPLEMENTARY MOS INVERTER
ID
VGSD2
VGSD1
VDS
VGSD3
VGSD4
VGSL1
VGSL2
VGSL3
VGSL4
ID
VGSD2
VGSD1
VDS
VGSD3
VGSD4
VGSL1
VGSL2
VGSL3
VGSL4
S
D
Iovin
vout
+
-
5.1. PMOS transistor as a LOAD
The 3-terminal PMOS pull-up device provides a family of non-linear load lines
-
+
V DD - ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
5.2. CMOS Inverter IDD = IDL NMOS DEVICE
VGSD = VIN
VDSD = VOUT
PMOS DEVICE
VGSL = VIN - VDD
VDSL = VOUT -VDD
CMOS Inverter
IMPACT ON INVERTER VOLTAGE TRANSFER CHARACTERISTICS
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Vout
VDD
CV
out
0
Vin
VDD
VDD
A B
DE
Vtn
VDD
/2 VDD
+Vtp
Vin0
Vin1
Vin2
Vin3
Vin4 V
in5A B
C
D
E
CMOS Inverter
CMOS Inverter
5.3. CMOS DC ANALYSIS
VDDGND
n
+np
Vout
Vin
+p+n +p +n
ViN 0
Vin VGSD 0 VGSD VTD Driver Off
VGSL Vin VDD VDD VGSL VTL Load on
But TD OFF IDD 0 IDL 0
VGSL VTL VDSL 0
TL LIN/OFF
vout VDD VDSL VDD
VOH VDDVOH VDDNotice that as with the depletion load inverter CMOS enables to reach
-
+
V DD - ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CMOS Inverter
CMOS: A Ratioless Logic
VGSD Vin VTD TD ON
VGSL 0 TL OFF
I DL 0 IDD 0
I DD 0
TD ON
VDSD vout 0
TD LIN/OFF
VOL 0
r VOL is independent of r .
ViN 0 or ViN VDD
Note that unlike previous inverter types
CMOS inverter enables VOL to reach GROUND level. CMOS is called RATIOLESS because the logic swing does not depend on
For either
=> ID= 0 => SPD=0
iN DDV V
-
+
V DD - ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CMOS Inverter
TD SAT -TL LINEAR
I DD IDL
2
2
2
2
Din TD
out DD
L in DD TL out DD
kV V
v Vk V V V v V
vout VDD
2 2 vout VDD Vin VDD VTL R Vin VTD
2 0
4 Vin VDD VTL 2 4r Vin VTD
2
Vin**
r Vin**
VTD 2
Vin**
VDD VTL 2
Square root argument > 0 => TL LIN --> SAT transition occurs for
satisfying
-
+
V DD - ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CMOS Inverter
TD SAT, TL SAT
kD
2Vin VTD
2
k L
2
Vin VDD VTL 2
As in the case of depletion mode inverter the output voltage is undefined for this input
Vin*
is given by
Vin*
VDD VTL VTD r
1 r
Therefore, around the transfer characteristic has infinite slope.
Vin*
-
+
V DD - ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CMOS Inverter
TD LIN - TL SAT
kD Vin VTD Vout Vout
2
2
k L
2Vin VDD VTL
2
Vout2 2Vout Vin VTD
1
rVin VDD VTL
2 0
Vin VTD 1
r
Vin VDD VTL 2
1
r
Vin***
VDD VTL 2
Vin***
VTD 2
Vin*
Vin**
Vin***
Note that = =
Therefore both load and driver device mode transitions occur for
-
+
V DD - ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CMOS Inverter
CMOS TRANSFER CHARACTERISTICS
VDD
Vout
Vin*
VTD VDD-VTL Vin
VDD
Vout
VT Vin VDD VDD-VT VDDVDD
2TD
TL
OFF
LIN/OFF
SAT
LIN
LIN
SAT
LIN/OFF
OFF
SYMMETRIC
CURRENT
NON-SYMMETRIC
VDD2
Vin* = Vinv =(VDD/ 2)
2
* DDin
DL
TDTL
VV
kk
VV
Symmetric CMOS inverter
Under the following conditions the CMOS VTC will be symmetrical
CMOS Inverter
ASSYMETRIC OR SKEWED CMOS INVERTER
Vout
0
Vin
VDD
VDD
0.5
12
10p
n
0.1p
n
If =kp/kn 1, switching point will move from VDD/2 Called skewed gate
CMOS Inverter
Noise Margins
How much noise can a gate input see before it does
not recognize the input?
Indeterminate
Region
NML
NMH
Input CharacteristicsOutput Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
CMOS Inverter
CMOS NOISE MARGINS
TD SAT, TL LIN
in
out
*
in
*
OH
*
iL
22
22
dV
dV
Vfor that
ynumericall V V
11
1
in
TDinrTLDDin
DDTDrTLinr
in
out
TDinrTLDDinTLinout
VNote
Find
VVVVV
VVVV
dV
dV
VVVVVVVV
CMOS Inverter
5.4. CMOS TIME RESPONSE
DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes
Requires solving differential equations
Input is usually considered to be a step or ramp
From 0 to VDD or vice versa
Vin(t)
Vout
(t)C
load
Idsn
(t)
CMOS Inverter
DELAY DEFINITIONS
tpdr: rising propagation delay
From input to rising output crossing VDD/2
tpdf: falling propagation delay
From input to falling output crossing VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2
tr: rise time
From output crossing 0.2 VDD to 0.8 VDD
tf: fall time
From output crossing 0.8 VDD to 0.2 VDD
CMOS Inverter
INVERTER DELAY CALCULATION
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write, may hide insight
We will use simple equations that are inaccurate but
provide insight
(V)
0.0
0.5
1.0
1.5
2.0
t(s)0.0 200p 400p 600p 800p 1n
tpdf
= 66ps tpdr
= 83psVin
Vout
CMOS Inverter
Simple Case Example: Resistive Pull-Up Inverter
Transient Response
CMOS Inverter
INVERTER CAPACITANCES
Vss=Vs=0VG
Field Oxide
VDDPoly Load
Output
Ci
CGB
n
CGSp CDS
n
Example: Resistive load inverter
List of Parasistic MOS Inverter Capacitances 1. Drain Junction Capacitance of driver 2. Interconnect Capacitance 3. Capacitance Associated with load 4. Load Inverter Capacitance F=Fan Out
CDS CodCi
Col
FCin
The inverter must therefore drive a capacitance CL Cod Col Ci FCin
CMOS Inverter
INPUT CAPACITANCE
Vss=Vs=0VG
Field Oxide
VDDPoly Load
Output
Ci
CGB
n
CGSp CDS
n
Cin CGS CGB CGD WLoxtox
C in C L
V DD
The input capacitance Cin of the MOS inverter is the gate capacitance of the driver
Capacitance at the output of a Resistive load MOS inverter
CL Cod Col Ci FCin
CMOS Inverter
RISE AND FALL TIMES
VOL to VOH
VOH to VOL
Rise (toff or tr) and Fall Time (ton or tf)
Rise time (Turn-off Time ) is approximately the time
that the output voltage of the inverter
takes to increase from
The Fall time (Turn-on -time ) is approximately the
time that the output voltage
takes to settle down from
These transient times are governed by the capacitances and resistances in the circuit and
by the currents charging and discharging them to the desired voltage levels.
t = C(V)/
where < I > denotes average current
CMOS Inverter
CMOS Inverter
RISE TIME OF RESISTIVE PULL-UP INVERTER
I coff 1
VDD
vout
R0
VDD
dvout
1
VDD
vout2
2R
0
vDD
vDD
2R
Then,
tr CLVDDVDD /2R
2RCL t r 2RCL
In general the rise time is given by
tr = 2.3 RC
tr is essentially governed by the pull-up conductance and by the load capacitance CL
MOSFET OFF
CMOS Inverter
FALL TIME OF A RESISTIVE LOAD INVERTER
Icon k VDD VT 2 2
6
VT
6VDD
VDD
2R
t f 6CLVDD
kD2
VT
VDD
VDD VT
2
3VDD
B
1
Fall Time
Fall time is affected by all 3 devices including the pull-down
The non linear behavior of the MOSFET requires piecewise linear calculation of the solution by solving the relevant differential equation with appropriate boundary conditions. Instead Shockley model uses average current and plugs it into
t = C(V)/
CMOS Inverter
CMOS INVERTER INPUT AND OUTPUT CAPACITANCES
. .3 3L DS NMOS i in NMOSC C C FC
.
.
oxin n GSn GBn GDn n
ox
oxin p GSp GBp GDp p
ox
C C C C W Lt
C C C C W Lt
Input and output capacitance of a CMOS inverter
VDDGND
n
+np
Vout
Vin
+p+n +p +n
CGSn CGSp
CGBn CGBp
CDSn CDSp
But Wp~2Wn
. . . 3ox
in CMOS in p in n n
ox
C C C W Lt
CMOS Inverter
Fall time
VDD
VinL=0
VDD
Rise time
CMOS Inverter
CMOS FALL TIME
In CMOS the turn-off time is totally governed by the load, whereas the turn-on time is totally governed by the driver. Using Shockleys approach
DD TD
TD DD TD
02
DD oDD TD O DD TD O
2D DD0c(on)
DD TD TD
DDO
V Vk 2 dV
2V V V
3
V
kV V dV V V V
2VkI V V VVdV
resulting in
VVVVkCV
tTDDDTDDDD
DD
on
2
32
2
VDD t = C(V)/Icon
CMOS Inverter
CMOS RISE TIME
DD
2L
LDD TL O DD TL DD OO0
Vc(r)
O
0
2L DD
DD TL TL
DD
- k - - ) 2
- +3
k (VV V dV V V V dVI
dV
2VkV V V
V
DD T L DD
DD T L
V V V
V V
2
DD
2
L DD TL DD TL- -
3CVt
V V 2V Vkr
VinL=0
VDD
One obtains an identical equation form for toff by replacing kD by kL and VTD by VTL
CMOS Inverter
Note that when VDD>>VT than ton = toff= C/kVDD If kL = kD (symmetric inverter) then ton = toff and the time response of CMOS inverter will be symmetric as well The inverter propagation delay is than
tp= (ton+toff)/2= C/kVDD
IMPORTANT SIMPLIFICATIONS
CMOS Inverter
CMOS FANOUT and CMOS LOGIC GATE RESPONSE
CMOS FANOUT limited by maximum propagation delay tpmax that is allowed
tpmax= Cmax/kVDD Cmax= tpmax kVDD
If input capacitance of load inverter is Cin than
Fmax=Cmax/Cin = tpmax kVDD / Cin
2
DD
2f
D DD TD DD TD
=- -
3 Vt
V V 2Vk
C
n V
CMOS LOGIC GATE DYNAMIC RESPONSE
2
DD
2
L DD TL DD TL- -
3 Vt
V V 2V Vk
C
mr
Where nkD and mkL are the effective transconductance parameters of the NMOS path and PMOS paths. The capacitance C must include the effective Drain capacitances of NMOS and PMOS transistors
CMOS Inverter
5.5. POWER DISSIPATION SOURCES
Ptotal = Pdynamic + Pstatic
Dynamic power: Pdynamic = Pswitching + Pshortcircuit Switching load capacitances
Short-circuit current
Static power: Pstatic = (Isub + Igate + Ijunct )VDD Subthreshold leakage
Gate leakage
Junction leakage
[Contention current (two terminal pull-ups)]
CMOS Inverter
POWER IN CIRCUIT ELEMENTS
VDD DD DDP t I t V
2
2R
R R
V tP t I t R
R
0 0
212
0
C
C
V
C
dVE I t V t dt C V t dt
dt
C V t dV CV
CMOS Inverter
CHARGING A CAPACITOR
When the gate output rises
Energy stored in capacitor is
But energy drawn from the supply is
Half the energy from VDD is dissipated in the pMOS transistor
as heat, other half stored in capacitor
When the gate output falls
Energy in capacitor is dumped to GND
Dissipated as heat in the nMOS transistor
212C L DD
E C V
0 0
2
0
DD
VDD DD L DD
V
L DD L DD
dVE I t V dt C V dt
dt
C V dV C V
CMOS Inverter
SWITCHING POWER & ACTIVITY FACTOR
C
fswi
DD(t)
VDD
Suppose the system clock frequency = f
Let fsw = af, where a = activity factor
If the signal is a clock, a = 1
If the signal switches once per cycle, a =
Dynamic power:
2
switching DDP CV fa
CMOS Inverter
Short Circuit Current
When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
Leads to a blip of short circuit current.
< 10% of dynamic power if rise/fall times are
comparable for input and output
Edp=VDD (Ipeak.ton)/2+ VDD (Ipeak.toff)/2=> Pdp= VDD Ipeak f tp
CMOS Inverter
POWER DISSIPATION
STATIC POWER :
Due to Leakage: Ps VDD.ILeakage
DYNAMIC POWER DISSIPATION: Due to load capacitance Each half cycle the energy stored on the C is with f = frequency
fCVf
EP
CVE DD
DDc
2
c
2
P 2
1 and ;
2
Due to Direct path transition currents
Edp=VDD (Ipeak.ton)/2+ VDD (Ipeak.toff)/2=> Pdp= VDD Ipeak f tp
CMOS Inverter
LATCHUP
Latchup results from parasitic bipolar transistors that when turned on can short VDD to ground via the substrate. When one of the two BJTs gets forward biased it feeds the base of the other BJT increasing the current until the circuit burns out.To minimize risk of latch-up the resistances Rnwell and Rpsubs must be minimized. This can be achieved by placing many contacts (guard rings) around large current handling devices.
(a) Origin of latchup (b) Equivalent circuit
VDD
Rpsubs
Rnwell p-source
n-source
n+ n+p+ p+ p+ n+
p-substrateRpsubs
Rnwell
VDD
n-well
-
+
V DD- ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CX
-
+
V DD- ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CX
CMOS Inverter
CMOS WITH LEAKY GATES
We represent the leaky gate with a resistor
For Vin =0 PMOS Linear NMOS off
X
vVvVvVVVk outDDoutDDoutDTLDDinL
2
2
Therefore Vout is not VDD For Vin= VDD PMOS OFF, NMOS LIN OFF
Therefore VoutL = 0V
-
+
V DD- ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CX
-
+
V DD- ViN
+
ViN
VDD
+
- VDDVOUT
-
VOUT
-
+
-
PMOS
NMOS
G
S
S
D
D
CX
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