Zynq-Based Reconfigurable System for Real-Time Edge Detection ...

Research ArticleZynq-Based Reconfigurable System for Real-Time EdgeDetection of Noisy Video Sequences

Iljung Yoon Heewon Joung and Jooheung Lee

Department of Electronics and Computer Engineering Hongik University Seoul 04066 Republic of Korea

Correspondence should be addressed to Jooheung Lee jooleehongikackr

Received 25 December 2015 Accepted 10 July 2016

Academic Editor Valerio Bellandi

Copyright copy 2016 Iljung Yoon et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

We implement Zynq-based self-reconfigurable system to perform real-time edge detection of 1080p video sequences While objectedge detection is a fundamental tool in computer vision noises in the video frames negatively affect edge detection resultssignificantly Moreover due to the high computational complexity of 1080p video filtering operations hardware implementationon reconfigurable hardware fabric is necessary Here the proposed embedded system utilizes dynamic reconfiguration capability ofZynq SoC so that partial reconfiguration of different filter bitstreams is performed during run-time according to the detected noisedensity level in the incoming video frames Prattrsquos Figure of Merit (PFOM) to evaluate the accuracy of edge detection is analyzedfor various noise density levels and we demonstrate that adaptive run-time reconfiguration of the proposed filter bitstreamssignificantly increases the accuracy of edge detection results while efficiently providing computing power to support real-timeprocessing of 1080p video frames Performance results on configuration time CPU usage and hardware resource utilization arealso compared

1 Introduction

Heterogeneous embedded systems have proliferated in theInternet of Things era and stream-based applications formultimedia services are widely used in various types ofportable devices These applications are data-intensive andneed high computing capability to meet the requiredthroughput and stringent real-time constraints On the otherhand low power consumption is also as important asthroughput for these portable embedded systems since theyoperate often in the energy constrained environments [1]

Recently Zynq SoC (System on Chip) platform includingARM dual-core Cortex-A9 processor with FPGA fabrichas been used in the embedded systems (eg AdvancedDriver Assistance System) to implement computationallycomplex signal processing algorithms by utilizing both ofSW flexibility of ARM processor and parallel processingcapability of reconfigurable hardware fabric [2] For sensorprocessing and tracking object classification and assess-ment edge detection is a fundamental tool in computer visionapplications However 1080p-resolution video processing for

object edge extraction in real-time is highly time consumingand becomes computational bottleneck for ARM processorsTherefore algorithm migration onto the FPGA fabric hasbeen preferred to meet the performance requirements Theprevious studies [3 4] had designed drawback such asinflexibility of the implemented hardware architecture andlack of adaptation capability for time-varying incoming videosignals while partial reconfiguration technique on FPGA canbe highly desirable to solve these problems In particularas shown in the previous studies [5] corrupted images withunwanted salt-and-pepper noises caused by faulty memorycells sensing error in the analog-to-digital conversion orbit error in transmission degrade the performance of edgedetection filters significantly

In this paper we implement the adaptive partial recon-figurable system to maximize the output performance ofthe implemented edge detection filter By detection ofnoise density levels in the incoming video adaptive self-reconfiguration of hardware bitstream is performed in real-time in order to remove unwanted noises before edge extrac-tion process For efficient utilization of hardware resources

Hindawi Publishing CorporationJournal of SensorsVolume 2016 Article ID 2654059 9 pageshttpdxdoiorg10115520162654059

2 Journal of Sensors

IO Peripherals

I2C 0I2C 1

UART 1GPIOSD0

USB 0 Enet 0

GICDMA8channel

Centralinterconnect

AXImasterports

AXIslaveports

Bank 0MIO(150)

IOMUX(MIO)

Bank 1MIO

(5316) Flash memoryinterfaces Memory interfaces

Clockgeneration

0 1 2 3

General settings ResetSWDTTTC

Systemlevel

controlregs cache

MMU

Application processor unit (APU)

cache

MMUCortex-A9MPCore

CPU

Cortex-A9MPCore

CPU

NEONFPU engineNEONFPU engine

Snoop control unit

Boot ROMOCM

interconnect

AXIACPslaveports

Programmablelogic to memory

interconnect

CoreSightcomponents

DAP

DEVC

High performance

Ports

XADCConfigAESSHA

GTX

12 13 14 154 5 6 70 1 2 3

DMAchannels

IRQPS to PLclock ports

Extended MIO(EMIO)

SMC timingcalculation

Input clockand freq

PCleGen2

SelectIO

Programmable logic (PL)

Processing system (PS)

(125Gbps)

32b GP32b GP

32b

AXI 32b64b slave

32kb Icache32kb I 32kb D

cache32kb D

512kb L2 cache and controller256kb OCM

Figure 1 Zynq SoC architecture

bitstream of Median filter with the following Sobel edgedetection is also mapped to the same hardware region onFPGA

The rest of this paper is organized as follows Section 2introduces Zynq SoC platform and adaptive reconfigurationapproach is proposed in Section 3 In Section 4 experimentalresults are discussed and we conclude this paper in Section 5

2 Zynq SoC Platform

Zynq-7000 AP SoC platform is hybrid FPGA platformcombining high-performance ARM processor with FPGAfabric Figure 1 shows Zynq internal architecture It consistsof Processing System (PS) and Programmable Logic (PL)The PS consists of ARM dual-core Cortex-A9 MP coreCaches DMA controller and various built-in peripheralssuch as USB UART SPI CAN and I2C The PL attachedto the PS through AMBA AXI ports possesses a numberof hardware resources Configurable Logic Blocks (CLB)Digital Signal Processing (DSP) Blocks two 12-bit analog-to-digital converters and serial transceivers [6]

Advanced Microcontroller Bus Architecture (AMBA) isused for the connection of functional blocks in a System onChip (SoC) [7] Particularly Advanced eXtensible Interface(AXI) high-performance slave ports with configurable 32-bitor 64-bit data width and AXI general-purpose masterslaveports with 32-bit data width are available for PS-PL interfaceTherefore it ensures that user-defined functional blocks onprogrammable logic region can easily exchange data with oneanother and data can be transferred across the system [8]

Partial Reconfiguration (PR) plays a critical role forenhancing FPGA adaptability by allowing specific region

of the FPGA to be reconfigured dynamically with a newbitstream while the remainder of the FPGA continues torun Specific regions called Partially Reconfigurable Regions(PRRs) are used to implement the bitstreams of PartialReconfigurable Modules (PRMs) Throughout the designapproach using partial reconfiguration many advantagesover traditional full configuration can be provided such asreduction of hardware resource utilization and reconfigu-ration time overhead increased scalability reduced systemdowntime and less storage size required Additionally reduc-ing the size of the FPGA can lead to reduction of cost andpower consumption [9] Therefore partial reconfigurationtechniques have been widely studied in different domains toprovide benefits such as enhanced quality performance andreliability of the systems [10ndash12]

In order to access FPGArsquos configuration memory forpartial reconfiguration different types of interfaces suchas JTAG SelectMAP and ICAP (Internal ConfigurationAccess Port) have been offered by Xilinx FPGAs Whileexternal reconfiguration controller outside the FPGA isneeded for JTAG and SelectMAP ICAP enables internalaccess within the FPGA supporting self-reconfigurationapproaches Therefore ICAP interface has been widely usedtogether with soft-IP processor (Xilinx Micro Blaze) orhard-IP processor (IBM PowerPC) and many studies onnew interface for ICAP have been performed to enhancereconfiguration speed [13 14] or reduce hardware resourcesrequired [15] For Zynq SoC additional interface calledProcessor Configuration Access Port (PCAP) is provided toenable PS to configure PL region [16]

In this paper partial reconfiguration of the proposedfilter bitstreams is performed through 32-bit PCAP interfacewhich is clocked at 100MHz and can support up to 400MBs

Journal of Sensors 3

PL PS

Static logic

Reconfiglogic

On-chipRAM

ExternalSD card

DDRmemory

DevC

PCAP

PS boot

Partial BIT file

Full BIT file

Figure 2 PR interface using PCAP

0 0 0

1 2 1

minus1minus1 minus2

(a) Vertical operator1198781(119896 119897)

0 1

0 2

0 1

minus1

minus2

minus1

(b) Horizontal operator1198782(119896 119897)

Figure 3 Sobel operator

download throughput PR interface using PCAP is shownin Figure 2 First Stage Boot Loader (FSBL) read fromexternal SD card boots up PS and configures the PL withthe full bitstream via the PCAP and user application loadsthe partial bitstream into DDR memory later on Fromthis moment software-controlled partial reconfiguration isenabled to dynamically reconfigure part of the PL with thebitstream of preimplemented IP core [17]

3 Proposed Approach

For real-time object edge extraction of 1080p-resolutionvideo frames Sobel filter has been implemented onPL regionAs an orthogonal gradient operator Sobel operators shown inFigure 3 are used to perform 2-dimensional convolution inevery pixel of the incoming video frame 119891(119909 119910) is the pixelvalue at location (119909 119910) [18]

1198661 (119909 119910) =1

sum119896=minus1

1

sum119897=minus1

1198781 (119896 119897) 119891 (119909 + 119896 119910 + 119897)

1198662 (119909 119910) =

1

sum119896=minus1

1

sum119897=minus1

1198782 (119896 119897) 119891 (119909 + 119896 119910 + 119897)

(1)

The gradient vector magnitude and direction are given by

119866 (119909 119910) = radic11986621(119909 119910) + 1198662

2(119909 119910)

120579119866(119909 119910) = tanminus1

1198662(119909 119910)

1198661(119909 119910)

(2)

Typically salt-and-pepper noise is caused by defectivesensors faulty memory cells and bit error in transmissionand it degrades the performance of edge detection filtersignificantly In this paper we implement the noise detectionalgorithm proposed in [19] and briefly describe it as follows

119901(119909 119910) is a pixel value to be processed and 3 times 3 windowwith 119901(119909 119910) as the center location is considered 119901min and119901max are minimum and maximum pixel values of 3 times 3window Then thresholds 119879min and 119879max are defined as

119879min =

2119901min minus 255 2119901min gt 255

0 otherwise

119879max =

2119901max 2119901max lt 255

255 otherwise

(3)

Equation (4) is used as a criterion to determine whether119901(119909 119910) is a corrupted noise pixel or not

noisedet =

1 119901 (119909 119910) le 119879min or 119901 (119909 119910) ge 119879max

0 otherwise(4)

Then the noise density is measured as the total numberof detected noise pixels divided by the total number of pixelsin a given video frame

Since the edge detection performance decreases signifi-cantly in the corrupted image by the salt-and-pepper noiseMedian filter is implemented for denoising as in

(119909 119910) = Median 11987211990910158401199101015840 (1199091015840 1199101015840) isin 119882(119909 119910) (5)

Here Median value of neighboring pixels in window 119882is selected as output [20]

The proposed self-reconfiguration method replacesPRMs to the Sobel edge detection after preprocessingMedian operator (hereafter referred to as the Median +Sobel filter) which is effective for noise reduction when thesalt-and-pepper noise is added to the video frame

Prattrsquos Figure of Merit (FOM) to evaluate the accuracyof detected edge in noisy image is used to determine corre-sponding threshold of noise density level As performance ofedge detection accuracy is deteriorated partial reconfigura-tion process is triggered to reduce noise before edge filteringPrattrsquos FOM is defined by

119877 =1

119868119873

119868119863

sum119894=1

1

1 + 1205721198892 (6)

Here 119868119873 = max(119868119868 119868119863) 119868119868is the number of edge points

in the ideal edge 119868119863 is the number of edge points in thedetected edge 120572 is a calibration constant and 119889 is the distancebetween the detected and the ideal edges [21] The distanceldquo119889rdquo is important factor in the evaluation of edge detectionusing PFOM The factor ldquo119889rdquo is inversely proportional to thefactor 119877 For a stained edge the distance ldquo119889rdquo between idealand detected edge increases and factor 119877 is reduced


Frame buffer

Noise density level detection

Filterprocessing

DisplayD

DR

mem

ory

Vide

o m

emor

y

CPUHDMI in

HDMI out

Figure 4 Video pipeline and noise detection task

Figure 4 shows video pipeline architecture and noisedetection task The 1080p video frames from HDMI-INare stored in DDR memory The implemented filter mainlyconsists of three subfunctions that are filtering process edgedetection process and bus interface to control input andoutput of video Video DMA (VDMA) reads video framesfrom DDR memory and sends them to the filter engine TheAXI4-Stream interfaces are connected through VDMA andAXI interconnect block to the high-performance slave port ofthe PS [22] The output frame from the filter engine is storedback into DDR memory and then stored frame is sent to thedisplay controller for HDMI-OUT Synthesized results showthat pipelined edge detection process has 9 clock cycles oflatency and total processing time requires 2059 clock cycles

Noise density level detection is performed to triggerpartial reconfiguration of Median + Sobel filter Partialbitstreams for filter operations are loaded from SD card intoDDR memory by the user application running on the PS Itimproves the reconfiguration time and also takes advantageof caching Then the application can use partial bitstreamsto modify the partially reconfigurable region in PL withoutinterrupting the rest of the PL area Partial reconfigurationof Sobel or Median + Sobel bitstreams from DDR memoryto the predefined PL region is performed through the PCAPinterface If the measured noise density becomes higher thanthe threshold then Median + Sobel bitstream is configuredto the partially reconfigurable region (PRR) to replace Sobelbitstream

For Zynq SoC an AXI-PCAP bridge consisting of ldquotrans-mitrdquo and ldquoreceiverdquo FIFO buffers between the AXI and thePCAP interface is implemented in the Device Configurationinterface (DevC) of the PS This bridge converts 32-bit AXIformatted data to 32-bit PCAP protocol and a DMA engine

FMC-imageon

HDMI in

HDMI out

UART

Video in

BuildU-boot

Build linuxkernel

CreateRamDisk

SDK SD card

Vivado

Booting and running linux ontarget platform

U-boot uImage uRamdisk

Full bit file Partial bit file

BOOTbin

UARTterminalemulator

Monitor 1080 p

Figure 5 Experimental environment

transfers data between the FIFOs and the DDR memory forpartial reconfiguration A DevC driver function built on topof sysfs is called to move data across the PCAP interfacethrough initiating the DMA transaction and then waits foran interrupt signaling that the transfer is completed Whenboth AXI and PCAP transfers are finished then the functioncall returns The application does not need to know aboutphysical location of partially reconfigurable region becausepartial bitstream has the configuration frame addressinginformationThefilter in PL region is reset before transferringa partial bitstream via DevCPCAP When the bitstreamtransfer is completed the reset is released and the configuredfilter is restarted with VDMA Our measurements show thatup to 5 frames of incoming video can be dropped during thepartial reconfiguration process

4 Experimental Results

Devices used in the experiment are ZC702 evaluation boardwith XC7Z020 AP SoC FMC module equipped with HDMIinputoutput based on ADV7611ADV7511 and 1920 times 1080resolutionmonitor ZC702 board is controlled throughUARTTerminal Emulator running on PC [23] Figure 5 showsexperimental setup for implementation of the proposed


HDL designdescription

HLS

C code

IP cores

Synthesis

Static logic PR modules

Implementationand bitstream generation

Fullbitstream Partial

bitstreamsPartial

Bitstreams

Figure 6 The procedure of bitstream generation

reconfigurable edge detection system The Boot binary filebooting the ZynqSoC consists of Zynq FSBL created in theSDK tool full bit file generated in the Vivado and U-boot called second stage boot loader The compressed kernelimage that is uImage supports linux operating systemon thetarget board [24]The partial bit files are initially stored in SDcard and read to DDRmemory for PS to perform PR throughthe PCAP interface The target board utilizes uramdisk asthe root file system The Software Development Kit (SDK)tool is used to create linux application on the processor toperform the operation of the proposed method and partialreconfiguration

In this paper the proposed Sobel and Median + Sobelfilter blocks are implemented by High-Level Synthesis (HLS)Tool [25 26] The HLS tool transforms C language C++and SystemC into a RTL implementation and also offers thepipelining of the function through GUI interface

Vivado Integrated Design Environment (IDE) is a devel-opment tool to provide Xilinx Integrated Synthesis Environ-ment (ISE) and Xilinx Platform Studio (XPS) It is used toanalyze and synthesize the HDL designs and perform timinganalysis Figure 6 shows the overall procedure of full andpartial bitstream generation The HDL design description ofthe system and the IP cores generated by the HLS tool aresynthesized Then as shown in Figure 7 we floorplannedpartially reconfigurable region so that hardware resourcesrequired for implementation of PRMs are less than 90of thetotal amount of the PRR hardware resources The hardwareresource comparison of PRR and PRMs is summarized inTable 1

As a result one full bitstream and two partial bitstreamsare generatedThe PL system is initially configured with a fullbitstream including static logic and Sobel filter If detectednoise density level becomes higher than threshold partialbitstream of Median + Sobel is used to reconfigure the PRR

Static

Reconfigblock

Median +Sobel Sobel

Figure 7 Static logic and PR modules

Table 1 Comparison of PRR and PRMs resources

Resources PRR PRMsAvailable Sobel M + S

LUT 7800 2871 (368) 3478 (446)SLICE 1400 1054 (753) 1220 (871)RAMB18 40 3 (75) 6 (150)DSPs 40 0 (0) 0 (0)

region If its level becomes lower than threshold partialbitstream of Sobel is read again from DDR memory for run-time reconfiguration

In this paper new reconfiguration interface called PCAP(Processor Configuration Access Port) available on XilinxZynq SoC is explored to perform partial reconfigurationof filter bitstreams using ARM Cortex-A9 processor Whiletheoretical speed of reconfiguration for 32-bit PCAP interfaceclocked at 100MHz is 400MBs practical reconfigurationspeed is much lower due to the internal ARM interconnectarchitecture Several examples using filter bitstream withJTAG ICAP and PCAP interfaces are shown in Table 2

Due to the design approach using partial reconfigurationwe could achieve significant reduction of both bitstream filesize and reconfiguration time through PCAP interface Asshown in Table 3 partial reconfiguration time is reducedto 12 of the full configuration time and system downtimeto replace the function of the proposed filter engine is notnecessary any longer


Table 2 Different configuration interfaces

[27] [28] [29] [30] ProposedPartial bitstream size 242KB 244KB 100KB 374KB 460KBPartial reconfig time 1 sec 460ms 29ms 6ms 10msConfiguration interface JTAG (Virtex-4) ICAP (Virtex-4) ICAP (Virtex-5) PCAP (Zynq-7000) PCAP (Zynq-7000)Frequency (MHz) 6MHz 100MHz 100MHz 100MHz 100MHzTypes of module Median filter Median filter Electronic stethoscope FPU Median + Sobel filter

(a) Noisy video 1 (salt-and-pepper noise density20)

(b) Noisy video 2 (salt-and-pepper noise density20)

(c) Output of Sobel filter original video 1 (d) Output of Sobel filter original video 2

(e) Output of Sobel filter (noisy video 1) (f) Output of Sobel filter (noisy video 2)

(g) Output of Median + Sobel filter (noisy video 1) (h) Output of Median + Sobel filter (noisy video 2)

Figure 8 Comparison of edge detection results for the noisy video sequences

Full HD video sequences of 1920 times 1080 resolution areused for experiments Boat sequence (video 1) and Beautysequence (video 2) are shown in Figure 8 Figures 8(a) and8(b) show video sequences 1 and 2 corrupted by salt-and-pepper noise with 20 noise density level respectively Sobel

filterrsquos outputs of original video sequences 1 and 2 areshown in Figures 8(c) and 8(d) Edges in the scene are clearlydetected In contrast Figures 8(e) and 8(f) show that Sobelfilterrsquos performance for the noisy video sequences 1 and 2degrades significantly resulting in lower values of PFOMs


2 4 6 8 100

002

004

006

008

01

Frame

PFO

M

5 noise density10 noise density

(a) Sobel filter with Video 1

2 4 6 8 10Frame

0

002

004

006

008

01

PFO

M


(b) Sobel filter with Video 2

2 4 6 8 10Frame

075

08

085

09

PFO

M


(c) Median + Sobel filter with Video 1

2 4 6 8 10Frame

075

08

085

09

PFO

M


(d) Median + Sobel filter with Video 2

Figure 9 PFOMs for Sobel and Median + Sobel filters

Table 3 Bitstream size and configuration time

Full bitstream Partial bitstreamBitstream size 4045564 bytes 460544 bytesPCAP configuration time 83ms 10ms

As shown in Figures 8(g) and 8(h) Median + Sobel filteris highly effective for the noisy video sequences 1 and 2Its edge detection results are significantly improved bothsubjectively and objectively For objective evaluation of edgedetection results PFOM is used to compare the performanceof Sobel and Median + Sobel filters [31 32] Video sequences1 and 2 are corrupted by salt-and-pepper noise with 5and 10 noise density level Since Median operator removesthe salt-and-pepper noise in the corrupted video framesperformance analysis of two filter engines shows that Median+ Sobel filter provides about 14 to 20 times improvement ofPFOM as indicated in Figure 9

In Figure 10 frame rates supported by Sobel and Median+ Sobel filters are indicated and run-time CPU usage ofhardware and software filter implementations is measured inFigure 11 While 100 of CPU power is used for SW imple-mentation of Sobel filter frame rates drop significantly downto 15 fps indicating software implementation is not suitablefor real-time processing of 1080p video frames Here cameracontroller supports 60 input frames per second Due to theadditional computational complexity HW Median + Sobelfilter supports up to 29 frames per second (fps) about 1 frameless than Sobel HW implementation (30 frames per second)

After PR the power consumption of hardware platformon Xilinx Zynq FPGA is estimated using Power Report inVivado Design Suite [33]

As shown in Figure 12 the power consumption ofMedian+ Sobel filter is higher than Sobel filter because Median +Sobel filter requires more hardware resources in FPGA thanSobel filter


0 1 2 3 4 5 6 7 28 29 30 31 32Frames

SW Sobel

SW Median + Sobel

HWMedian + Sobel

HWSobel

Figure 10 Comparison of frame rates

Filter CPU usage

CPU

usa

ge

100

90

80

70

60

50

40

30

20

10

0

Time domain5 10 15 20 25 30

Filter HWFilter SW

Filter off

Figure 11 CPU Usage

199

198

197

196

195

194

2

Tota

l on-

chip

pow

er (W

)

StaticSobel

Median + Sobel

19951994

1976

Non-PR Sobel-PR Median +Sobel-PR

Figure 12 Comparison of power consumption

5 Conclusion

In this paper we propose adaptive partial reconfigurablesystem to maximize the output performance of the imple-mented edge detection filter Hardware implementation offilter engine onto the FPGA fabric provides computing capa-bility of real-time edge detection of 1080p video sequences

According to detection of noise density levels in the incomingvideo adaptive self-reconfiguration of hardware bitstream isperformed during run-time and it enables significant perfor-mance improvement in both subjective and objective resultsExperimental results show that partial reconfiguration timeis reduced to 12 of the full configuration time and about 14to 20 times improvement of PFOM is achieved

Competing Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

Acknowledgments

This research was supported by Basic Science ResearchProgram through theNational Research Foundation of Korea(NRF) funded by the Ministry of Education Science andTechnology (NRF-2012R1A1A1008674) and also by Busi-ness for Cooperative RampD between Industry Academy andResearch Institute funded Korea Small andMedium BusinessAdministration (C03319350100437169) and 2014HongikUni-versity Research Fund Additionally the authors would like toacknowledge Xilinx and the Xilinx University Program for itsgenerous donation of SW design tools and HW boards

References

[1] A Majumdar S Cadambi and S T Chakradhar ldquoAn energy-efficient heterogeneous system for embedded learning andclassificationrdquo IEEE Embedded Systems Letters vol 3 no 1 pp42ndash45 2011

[2] UG1165 (v20153) Zynq-7000 All Programmable SoC EmbeddedDesign Tutorial Xilinx November 2015

[3] D Crookes K Benkrid A Bouridane K Aiotaibi and ABenkrid ldquoDesign and implementation of a high level program-ming environment for FPGA-based image processingrdquo IEEProceedings Vision Image and Signal Processing vol 147 no 4pp 377ndash384 2000

[4] P Greisen M Runo P Guillet et al ldquoEvaluation and FPGAimplementation of sparse linear solvers for video processingapplicationsrdquo IEEE Transactions on Circuits and Systems forVideo Technology vol 23 no 8 pp 1402ndash1407 2013

[5] A M Mahmood H H Maras and E Elbasi ldquoMeasurementof edge detection algorithms in clean and noisy environmentrdquoin Proceedings of the 8th IEEE International Conference onApplication of Information and Communication Technologies(AICT rsquo14) pp 1ndash6 Astana Kazakhstan October 2014

[6] Xilinx Zynq-7000 All Programmable SoC OverviewDS190(v18) Xilinx 2015

[7] UG585(v110) Zynq-7000 All Programmable SoC Technical Ref-erence Manual Xilinx February 2015

[8] J Silva V Sklyarov and I Skliarova ldquoComparison of on-chipcommunications in Zynq-7000 all programmable systems-on-chiprdquo IEEE Embedded Systems Letters vol 7 no 1 pp 31ndash342015

[9] Xilinx Vivado Design Suite User Guide Partial ReconfigurationUG909(v20144) Xilinx 2014

[10] E Stott P Sedcole and P Y K Cheung ldquoFault tolerantmethodsfor reliability in FPGAsrdquo in Proceedings of the International


Conference on Field Programmable Logic and Applications (FPLrsquo08) pp 415ndash420 Heidelberg Germany September 2008

[11] C Insaurralde ldquoReconfigurable computer architectures fordynamically adaptable avionics systemsrdquo IEEE Aerospace andElectronic Systems Magazine vol 30 no 9 pp 46ndash53 2015

[12] M G Parris C A Sharma and R F Demara ldquoProgressin autonomous fault recovery of Field Programmable GateArraysrdquo ACM Computing Surveys vol 43 no 4 article 31 2011

[13] M Liu W Kuehn Z Lu and A Jantsch ldquoRunmdashtime partialreconfiguration speed investigation and architectural designspace explorationrdquo in Proceedings of the International Confer-ence on Field Programmable Logic and Application pp 498ndash502Prague Czech Republic September 2009

[14] R Bonamy H-M Pham S Pillement and D ChilletldquoUPaRCmdashUltra-fast power-aware reconfiguration controller rdquoin Proceedings of the Design Automation amp Test in EuropeConference amp Exhibition (DATE rsquo12) pp 1373ndash1378 IEEEDresden Germany March 2012

[15] M Hubner D Gohringer J Noguera and J Becker ldquoFastdynamic and partial reconfiguration data path with low hard-ware overhead on Xilinx FPGAsrdquo in Proceedings of the IEEEInternational Symposium on Parallel amp Distributed Processingpp 1ndash8 April 2010

[16] K Vipin and S A Fahmy ldquoZycap efficient partial reconfigura-tion management on the xilinx zynqrdquo IEEE Embedded SystemsLetters vol 6 no 3 pp 41ndash44 2014

[17] XAPP1159(v10) and C Kohn Partial Reconfiguration of aHardware Accelerator on Zynq-7000 All Programmable SoCDevices Xilinx January 2013

[18] S Jin W Kim and J Jeong ldquoFine directional de-interlacingalgorithm using modified Sobel operationrdquo IEEE Transactionson Consumer Electronics vol 54 no 2 pp 857ndash862 2008

[19] P-Y ChenC-Y Lien andY-M Lin ldquoA real-time image denois-ing chiprdquo in Proceedings of the IEEE International Symposium onCircuits and Systems (ISCAS rsquo08) pp 3390ndash3393 Seattle WashUSA May 2008

[20] C Chen J Ni and JHuang ldquoBlind detection ofmedian filteringin digital images a difference domain based approachrdquo IEEETransactions on Image Processing vol 22 no 12 pp 4699ndash47102013

[21] W K Pratt Digital Image Processing PIKS Inside 3rd edition2000

[22] UG1037 (v30) Vivado Design Suite AXI Reference GuideXilinx June 2015

[23] C Kohn Partial Reconfiguration of a Hardware Accelerator withVivado Design Suite for Zynq-7000 ApSoC Processor XAPP1231(v11) Xilinx 2015

[24] UG821 (v120) Zynq-7000 All Programmable SoC SoftwareDevelopers Guide Xilinx San Jose Calif USA 2015

[25] F M Vallina C Kohn and P Joshi Zynq All ProgrammableSoCSobel Filter Implementation Using the Vivado HLS ToolXAPP890 (v10) Xilinx 2012

[26] Xilinx Vivado Design Suite User Guide High-Level SynthesisUG902 (v20154) Xilinx 2015

[27] S U Bhandari S Subbaraman S S Pujari and R MahajanldquoReal time video processing on FPGA using on the fly partialreconfigurationrdquo in Proceedings of the International Conferenceon Signal Processing Systems (ICSPS rsquo09) pp 244ndash247 Singa-pore May 2009

[28] S U Bhandari S Subbaraman S Pujari and R MahajanldquoInternal dynamic partial reconfiguration for real time signal

processing on FPGArdquo Indian Journal of Science and Technologyvol 3 no 4 pp 365ndash368 2010

[29] A A Prince and SMishra ldquoMulti-mode electronic stethoscopeimplementation and evaluation using Dynamic ReconfigurableDesignrdquo in Proceedings of the 5th IEEE International AdvanceComputing Conference (IACC rsquo15) pp 228ndash232 Banglore IndiaJune 2015

[30] M Al Kadi P Rudolph D Gohringer and M HubnerldquoDynamic and partial reconfiguration of Zynq 7000 underLinuxrdquo in Proceedings of the International Conference on Recon-figurable Computing and FPGAs (ReConFig rsquo13) pp 1ndash5 IEEECancun Mexico December 2013

[31] I E Abdou andWK Pratt ldquoQuantitative design and evaluationof enhancementthresholding edge detectorsrdquoProceedings of theIEEE vol 67 no 5 pp 753ndash763 1979

[32] J-A Jiang C-L Chuang Y-L Lu and C-S FahnldquoMathematical-morphology-based edge detectors for detectionof thin edges in low-contrast regionsrdquo IET Image Processingvol 1 no 3 pp 269ndash277 2007

[33] Xilinx Vivado Design Suite User Guide Power Analysis andOptimization UG907(v20154) Xilinx 2015

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Navigation and Observation



DistributedSensor Networks



IO Peripherals

I2C 0I2C 1

UART 1GPIOSD0

USB 0 Enet 0

GICDMA8channel

Centralinterconnect

AXImasterports

AXIslaveports

Bank 0MIO(150)

IOMUX(MIO)

Bank 1MIO

(5316) Flash memoryinterfaces Memory interfaces

Clockgeneration

0 1 2 3

General settings ResetSWDTTTC

Systemlevel

controlregs cache

MMU

Application processor unit (APU)

cache

MMUCortex-A9MPCore

CPU

Cortex-A9MPCore

CPU

NEONFPU engineNEONFPU engine

Snoop control unit

Boot ROMOCM

interconnect

AXIACPslaveports

Programmablelogic to memory

interconnect

CoreSightcomponents

DAP

DEVC

High performance

Ports

XADCConfigAESSHA

GTX

12 13 14 154 5 6 70 1 2 3

DMAchannels

IRQPS to PLclock ports

Extended MIO(EMIO)

SMC timingcalculation

Input clockand freq

PCleGen2

SelectIO

Programmable logic (PL)

Processing system (PS)

(125Gbps)

32b GP32b GP

32b

AXI 32b64b slave

32kb Icache32kb I 32kb D

cache32kb D

512kb L2 cache and controller256kb OCM

Figure 1 Zynq SoC architecture

bitstream of Median filter with the following Sobel edgedetection is also mapped to the same hardware region onFPGA

The rest of this paper is organized as follows Section 2introduces Zynq SoC platform and adaptive reconfigurationapproach is proposed in Section 3 In Section 4 experimentalresults are discussed and we conclude this paper in Section 5

2 Zynq SoC Platform

Zynq-7000 AP SoC platform is hybrid FPGA platformcombining high-performance ARM processor with FPGAfabric Figure 1 shows Zynq internal architecture It consistsof Processing System (PS) and Programmable Logic (PL)The PS consists of ARM dual-core Cortex-A9 MP coreCaches DMA controller and various built-in peripheralssuch as USB UART SPI CAN and I2C The PL attachedto the PS through AMBA AXI ports possesses a numberof hardware resources Configurable Logic Blocks (CLB)Digital Signal Processing (DSP) Blocks two 12-bit analog-to-digital converters and serial transceivers [6]

Advanced Microcontroller Bus Architecture (AMBA) isused for the connection of functional blocks in a System onChip (SoC) [7] Particularly Advanced eXtensible Interface(AXI) high-performance slave ports with configurable 32-bitor 64-bit data width and AXI general-purpose masterslaveports with 32-bit data width are available for PS-PL interfaceTherefore it ensures that user-defined functional blocks onprogrammable logic region can easily exchange data with oneanother and data can be transferred across the system [8]

Partial Reconfiguration (PR) plays a critical role forenhancing FPGA adaptability by allowing specific region

of the FPGA to be reconfigured dynamically with a newbitstream while the remainder of the FPGA continues torun Specific regions called Partially Reconfigurable Regions(PRRs) are used to implement the bitstreams of PartialReconfigurable Modules (PRMs) Throughout the designapproach using partial reconfiguration many advantagesover traditional full configuration can be provided such asreduction of hardware resource utilization and reconfigu-ration time overhead increased scalability reduced systemdowntime and less storage size required Additionally reduc-ing the size of the FPGA can lead to reduction of cost andpower consumption [9] Therefore partial reconfigurationtechniques have been widely studied in different domains toprovide benefits such as enhanced quality performance andreliability of the systems [10ndash12]

In order to access FPGArsquos configuration memory forpartial reconfiguration different types of interfaces suchas JTAG SelectMAP and ICAP (Internal ConfigurationAccess Port) have been offered by Xilinx FPGAs Whileexternal reconfiguration controller outside the FPGA isneeded for JTAG and SelectMAP ICAP enables internalaccess within the FPGA supporting self-reconfigurationapproaches Therefore ICAP interface has been widely usedtogether with soft-IP processor (Xilinx Micro Blaze) orhard-IP processor (IBM PowerPC) and many studies onnew interface for ICAP have been performed to enhancereconfiguration speed [13 14] or reduce hardware resourcesrequired [15] For Zynq SoC additional interface calledProcessor Configuration Access Port (PCAP) is provided toenable PS to configure PL region [16]

In this paper partial reconfiguration of the proposedfilter bitstreams is performed through 32-bit PCAP interfacewhich is clocked at 100MHz and can support up to 400MBs


PL PS

Static logic

Reconfiglogic

On-chipRAM

ExternalSD card

DDRmemory

DevC

PCAP

PS boot

Partial BIT file

Full BIT file


0 0 0

1 2 1

minus1minus1 minus2


0 1

0 2

0 1

minus1

minus2

minus1




3 Proposed Approach


1198661 (119909 119910) =1

sum119896=minus1

1

sum119897=minus1

1198781 (119896 119897) 119891 (119909 + 119896 119910 + 119897)

1198662 (119909 119910) =

1

sum119896=minus1

1

sum119897=minus1

1198782 (119896 119897) 119891 (119909 + 119896 119910 + 119897)

(1)


119866 (119909 119910) = radic11986621(119909 119910) + 1198662

2(119909 119910)

120579119866(119909 119910) = tanminus1

1198662(119909 119910)

1198661(119909 119910)

(2)



119879min =

2119901min minus 255 2119901min gt 255

0 otherwise

119879max =

2119901max 2119901max lt 255

255 otherwise

(3)


noisedet =

1 119901 (119909 119910) le 119879min or 119901 (119909 119910) ge 119879max

0 otherwise(4)



(119909 119910) = Median 11987211990910158401199101015840 (1199091015840 1199101015840) isin 119882(119909 119910) (5)




119877 =1

119868119873

119868119863

sum119894=1

1

1 + 1205721198892 (6)




Frame buffer


Filterprocessing

DisplayD

DR

mem

ory

Vide

o m

emor

y

CPUHDMI in

HDMI out





FMC-imageon

HDMI in

HDMI out

UART

Video in

BuildU-boot

Build linuxkernel

CreateRamDisk

SDK SD card

Vivado




BOOTbin


Monitor 1080 p







HLS

C code

IP cores

Synthesis




bitstreamsPartial

Bitstreams






Static

Reconfigblock

Median +Sobel Sobel




















2 4 6 8 100

002

004

006

008

01

Frame

PFO

M



2 4 6 8 10Frame

0

002

004

006

008

01

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M











0 1 2 3 4 5 6 7 28 29 30 31 32Frames

SW Sobel

SW Median + Sobel

HWMedian + Sobel

HWSobel


Filter CPU usage

CPU

usa

ge

100

90

80

70

60

50

40

30

20

10

0

Time domain5 10 15 20 25 30

Filter HWFilter SW

Filter off

Figure 11 CPU Usage

199

198

197

196

195

194

2

Tota

l on-

chip

pow

er (W

)

StaticSobel

Median + Sobel

19951994

1976



5 Conclusion



Competing Interests


Acknowledgments


References







































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










PL PS

Static logic

Reconfiglogic

On-chipRAM

ExternalSD card

DDRmemory

DevC

PCAP

PS boot

Partial BIT file

Full BIT file


0 0 0

1 2 1

minus1minus1 minus2


0 1

0 2

0 1

minus1

minus2

minus1




3 Proposed Approach


1198661 (119909 119910) =1

sum119896=minus1

1

sum119897=minus1

1198781 (119896 119897) 119891 (119909 + 119896 119910 + 119897)

1198662 (119909 119910) =

1

sum119896=minus1

1

sum119897=minus1

1198782 (119896 119897) 119891 (119909 + 119896 119910 + 119897)

(1)


119866 (119909 119910) = radic11986621(119909 119910) + 1198662

2(119909 119910)

120579119866(119909 119910) = tanminus1

1198662(119909 119910)

1198661(119909 119910)

(2)



119879min =

2119901min minus 255 2119901min gt 255

0 otherwise

119879max =

2119901max 2119901max lt 255

255 otherwise

(3)


noisedet =

1 119901 (119909 119910) le 119879min or 119901 (119909 119910) ge 119879max

0 otherwise(4)



(119909 119910) = Median 11987211990910158401199101015840 (1199091015840 1199101015840) isin 119882(119909 119910) (5)




119877 =1

119868119873

119868119863

sum119894=1

1

1 + 1205721198892 (6)




Frame buffer


Filterprocessing

DisplayD

DR

mem

ory

Vide

o m

emor

y

CPUHDMI in

HDMI out





FMC-imageon

HDMI in

HDMI out

UART

Video in

BuildU-boot

Build linuxkernel

CreateRamDisk

SDK SD card

Vivado




BOOTbin


Monitor 1080 p







HLS

C code

IP cores

Synthesis




bitstreamsPartial

Bitstreams






Static

Reconfigblock

Median +Sobel Sobel




















2 4 6 8 100

002

004

006

008

01

Frame

PFO

M



2 4 6 8 10Frame

0

002

004

006

008

01

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M











0 1 2 3 4 5 6 7 28 29 30 31 32Frames

SW Sobel

SW Median + Sobel

HWMedian + Sobel

HWSobel


Filter CPU usage

CPU

usa

ge

100

90

80

70

60

50

40

30

20

10

0

Time domain5 10 15 20 25 30

Filter HWFilter SW

Filter off

Figure 11 CPU Usage

199

198

197

196

195

194

2

Tota

l on-

chip

pow

er (W

)

StaticSobel

Median + Sobel

19951994

1976



5 Conclusion



Competing Interests


Acknowledgments


References







































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Frame buffer


Filterprocessing

DisplayD

DR

mem

ory

Vide

o m

emor

y

CPUHDMI in

HDMI out





FMC-imageon

HDMI in

HDMI out

UART

Video in

BuildU-boot

Build linuxkernel

CreateRamDisk

SDK SD card

Vivado




BOOTbin


Monitor 1080 p







HLS

C code

IP cores

Synthesis




bitstreamsPartial

Bitstreams






Static

Reconfigblock

Median +Sobel Sobel




















2 4 6 8 100

002

004

006

008

01

Frame

PFO

M



2 4 6 8 10Frame

0

002

004

006

008

01

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M











0 1 2 3 4 5 6 7 28 29 30 31 32Frames

SW Sobel

SW Median + Sobel

HWMedian + Sobel

HWSobel


Filter CPU usage

CPU

usa

ge

100

90

80

70

60

50

40

30

20

10

0

Time domain5 10 15 20 25 30

Filter HWFilter SW

Filter off

Figure 11 CPU Usage

199

198

197

196

195

194

2

Tota

l on-

chip

pow

er (W

)

StaticSobel

Median + Sobel

19951994

1976



5 Conclusion



Competing Interests


Acknowledgments


References







































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











HLS

C code

IP cores

Synthesis




bitstreamsPartial

Bitstreams






Static

Reconfigblock

Median +Sobel Sobel




















2 4 6 8 100

002

004

006

008

01

Frame

PFO

M



2 4 6 8 10Frame

0

002

004

006

008

01

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M











0 1 2 3 4 5 6 7 28 29 30 31 32Frames

SW Sobel

SW Median + Sobel

HWMedian + Sobel

HWSobel


Filter CPU usage

CPU

usa

ge

100

90

80

70

60

50

40

30

20

10

0

Time domain5 10 15 20 25 30

Filter HWFilter SW

Filter off

Figure 11 CPU Usage

199

198

197

196

195

194

2

Tota

l on-

chip

pow

er (W

)

StaticSobel

Median + Sobel

19951994

1976



5 Conclusion



Competing Interests


Acknowledgments


References







































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation





















2 4 6 8 100

002

004

006

008

01

Frame

PFO

M



2 4 6 8 10Frame

0

002

004

006

008

01

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M



2 4 6 8 10Frame

075

08

085

09

PFO

M











0 1 2 3 4 5 6 7 28 29 30 31 32Frames

SW Sobel

SW Median + Sobel

HWMedian + Sobel

HWSobel


Filter CPU usage

CPU

usa

ge

100

90

80

70

60

50

40

30

20

10

0

Time domain5 10 15 20 25 30

Filter HWFilter SW

Filter off

Figure 11 CPU Usage

199

198

197

196

195

194

2

Tota

l on-

chip

pow

er (W

)

StaticSobel

Median + Sobel

19951994

1976



5 Conclusion



Competing Interests


Acknowledgments


References







































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










0 1 2 3 4 5 6 7 28 29 30 31 32Frames

SW Sobel

SW Median + Sobel

HWMedian + Sobel

HWSobel


Filter CPU usage

CPU

usa

ge

100

90

80

70

60

50

40

30

20

10

0

Time domain5 10 15 20 25 30

Filter HWFilter SW

Filter off

Figure 11 CPU Usage

199

198

197

196

195

194

2

Tota

l on-

chip

pow

er (W

)

StaticSobel

Median + Sobel

19951994

1976



5 Conclusion



Competing Interests


Acknowledgments


References







































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation





































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









Zynq-Based Reconfigurable System for Real-Time Edge Detection ...

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