ZVS Modulation Scheme for Reduced Complexity Clamp … · 1 ZVS Modulation Scheme for Reduced...

1

ZVS Modulation Scheme for Reduced ComplexityClamp-Switch TCM DC-DC Boost Converter

Oliver Knecht, Student Member, IEEE, Dominik Bortis, Member, IEEEand Johann W. Kolar, Fellow, IEEE

Abstract— DC-DC boost converter Zero-Voltage-Switching(ZVS) modulation schemes such as Triangular Current Mode(TCM) offer a highly efficient operation but suffer from largeswitching frequency variations, which are complicating the EMIfilter design and the digital control. As a solution, a tri-stateboost converter operated in ZVS mode, referred to as Clamp-Switch TCM (CL-TCM) operation can be introduced, whichallows to limit the switching frequency variation significantly.This paper presents two variations of the CL-TCM boost con-verter with reduced number of active switches in the circuit,which are suitable for high input-to-output voltage conversionratios. In addition, the ZVS modulation schemes, its limitations,the converter design and the controller implementation arepresented and analyzed in detail for both converter topologies.The timing calculations for the switching signals are providedfor two operating modes, either offering a minimized switchingfrequency variation and minimized RMS inductor current or aconstant switching frequency operation, which in turn comes atthe expense of an increased RMS inductor current. The ZVSoperation and the operating modes are experimentally verifiedusing a hardware prototype.

Index Terms—DC-DC boost converter, zero voltage switching(ZVS), tri-state boost, clamp switch, triangular current mode(TCM)

I. INTRODUCTION

Zero-Voltage-Switching (ZVS) DC-DC buck or boost con-verters are commonly realized using a Triangular CurrentMode (TCM) operation with variable switching frequency [1]–[4] or a Synchronous Conduction Mode (SCM) operation witha fixed switching frequency [5]–[7]. The main disadvantageof the SCM operation is the significantly reduced partial loadefficiency due to the large peak-to-peak inductor current ripplewhich is remained constant even at light load conditions. TheTCM operation mode instead offers a much higher partialload efficiency, which in turn comes at the expense of a largeswitching frequency variation and hence, complicates the filterdesign and the implementation of the digital control.

In order to overcome these drawbacks, an additional clamp-switch can be introduced in parallel to the boost inductor,which allows to limit the switching frequency variation signif-icantly, while achieving a high partial load efficiency similarto the TCM operation. Such a topology is implemented in[8] and in the Picor Cool-Power ZVS Buck Regulator seriesprovided by Vicor Corp. and is described in [9]. ZVS of theswitches in the half-bridge configuration is enabled as for the

The authors are with the Power Electronic Systems Laboratory, SwissFederal Institute of Technology Zurich, 8092 Zurich, Switzerland (e-mail:[email protected]; [email protected]; [email protected]).

Pmax

IL,min

IL,max

IL,avgPmin

Ton

TonT’

TclToff

t

iL(t) iL(t)

(b) (c)

IL,avg

Ton Toff

L iL

usw

(a)

C1

i1i0

u1

T1

T2

C2 RL

i2 iR

u2

IL,max

∆IL,pp

u1L

u1 − u2L

TonT’

uGD

s1

s2

s3

uGD

uGDGDum

D4

T3

Figure 1: (a) Proposed 3-switch Clamp-Switch TCM (CL-TCM)boost converter topology. (b)-(c) typical CL-TCM converter inductorcurrent waveforms at minimum and maximum output power.

SCM and TCM operation by reversing the flow direction ofthe inductor current in each switching period, and as a result,allowing for ZVS for each switch in the half-bridge.

The clamp-switch boost converter topology considered inthis paper is depicted in Fig. 1(a) and was proposed in asimilar form as a hard-switched converter in [10], which isreferred to as tri-state boost converter and which allows to im-prove the dynamic performance of the converter by eliminatingthe right-half-plane zero in the small signal control-to-outputtransfer function. In another more recent application presentedin [11], a hard-switched tri-state boost converter was used onthe receiver side of a wireless power transfer system, whichallows to implement an adaptive resonant frequency tuningand load matching.

In [12] and [13], a relatively complicated ZVS modulationscheme referred to as Clamp-Switch TCM (CL-TCM) opera-tion was introduced, where the clamp-switch is realized withan anti-series connection of two active switches. The modula-tion scheme allows for ZVS for all switches, independent ofthe output power level and without restrictions on the input-to-output voltage conversion ratio, given the natural boundariesfor boost operation. A similar ZVS operation was achievedwith a bidirectional buck-boost converter for the use in hybridelectric vehicles, as described in [14].

In this paper, a simplified ZVS modulation scheme [12] isproposed for the CL-TCM converter which allows to reducethe hardware complexity and which increases the reliabilityof the converter by replacing the clamp-switch used in [8],[13] with an anti-series connection of an active switch and a

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available at http://dx.doi.org/10.1109/TPEL.2017.2720729

Copyright (c) 2017 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].

2

C2

C1

i2

i1

iL

T1

T2

[t0, t1] T3

u2

uswu1

usw

L C2

C1

i2

i1

iL

T1

T2

T3t’u2

u1

usw

L C2

C1

i2

i1

iL

T1

T2

T3[t2, t3, t4][t1, t1, t2]u2

u1

usw

L C2

C1

i2

i1

iL

T1

T2

T3[t4, t5]u2

u1

usw

L C2

C1

i2

i1

iL

T1

T2

T3[t5, t6]u2

u1

usw

L C2

C1

i2

i1

iL

T1

T2

T3[t6, t7]u2

u1

usw

L C2

C1

i2

i1

iL

T1

T2

T3[t7, t8]u2

u1

D4 D4

D4

D4

D4

D4

D4

uSW(t)

iL(t)

si(t)

t3t4

t2

t5

u1

0

u2

IL,0IL,0

IL,min

IL,max

s1s2s3

t

t

ttt

t6t7t0

t1t0t’ t3t’ t8 = t0

u1L

uF,D4L

u1 − u2L

I’

Figure 2: Operating states of the proposed 3-switch CL-TCM modulation scheme for a full switching cycle [t0, t8]. Typical waveform ofthe inductor current iL and the switch-node voltage usw, belonging to the switch control signals si.

single diode, as shown in Fig. 1(a). In this paper, this type ofconverter is referred to as 3-switch CL-TCM boost converterand allows for zero-voltage switching and unidirectional powerflow. Furthermore, in this paper, a unidirectional 2-switch CL-TCM converter operation is proposed and explained in detail,which allows for ZVS of all switches as well, but reducesthe complexity of the converter hardware and the modulationscheme to a minimum. The proposed converter structures andZVS modulation schemes come at the expense of restrictionson the input-to-output voltage conversion ratio and outputpower range, as it will be explained in detail in Section II. Thedesign of the boost inductance and the calculation of the timingintervals Ton, Toff and Tcl (cf. Fig. 1(b) and (c)) are presentedin Section III. In addition, two converter operating modes,either offering a variable or constant switching frequencyoperation are analyzed and compared. In Section IV, thecontroller implementation is explained for both converter typesand in Section V, the experimental verification of the ZVSoperation and the proposed operating modes is presented. Inaddition, a DC-DC efficiency comparison for the different CL-TCM converter types is given in the same section. Concludingremarks are given in Section VI.

II. MODULATION SCHEME

Typical inductor current waveforms for the considered CL-TCM converter operation at minimum and maximum out-put power are shown in Fig. 1(b) and (c) respectively. Atmaximum output power, the CL-TCM operation correspondsto the TCM operation, i.e. the clamp switch T3 is unused.The inductor current has a triangular shape with a negativeinductor current IL,min at the end of time interval Toff thatallows for ZVS of the low-side switch T2 at the beginningof the subsequent time interval Ton. At light load conditions,the clamp-switch allows to introduce a free-wheeling statefor the inductor current after the turn-off of switch T1 and

hence, allows to stretch the switching period as it is shownin Fig. 1(b). As a result, the switching frequency variationcan be controlled depending on the output power and on thevoltage conversion ratio. The maximum switching frequencyfmax occurs always at the maximum voltage conversion ratio,whereby the maximum feasible operating frequency is mainlylimited by the time delays in the measurement and controlcircuit, as the switching time intervals need to be calculatedand synchronized to the zero-crossings of the inductor current,as explained in detail in Section IV.

The ZVS modulation scheme proposed in this paper allowsto reduce the number of active switches in the circuit topologyand is explained in the following. However, as already men-tioned, the reduced hardware complexity comes at the expenseof a restriction on the input-to-output voltage conversion ratioin order to achieve ZVS for all switches, and, neglecting theforward voltage drop of the diodes, can be expressed by

u2 ≥CT3 + CD4

CD4u1 , (1)

which reduces to u2 ≥ 2u1 if CT3 = CD4 applies. WhereCT3 and CD4 denote the parasitic output capacitance of switchT3 and the junction capacitance of diode D4 respectively.Nonetheless, a unidirectional operation and voltage step-upratios according to (1) are common in numerous applications,such as in module integrated converters for photovoltaicsystems [15]–[17], fuel-cell based backup energy systemsand uninterruptible power supplies [18], [19] as well as inautomotive applications [20], [21].

The main focus of this paper is on the operation of the3-switch CL-TCM converter topology shown in Fig. 1(a).However, the ZVS modulation scheme can be extended toa 2-switch CL-TCM operation as well, where the high-sideswitch T1 is replaced by a diode. This type of operation andthe ZVS conditions are explained later in this section.



3

Note that both converter topologies allow to use a boot-strap gate drive power supply for the clamp-switch T3 (cf.Fig. 1(a)), which simplifies the hardware complexity signifi-cantly.

A. 3-Switch CL-TCM Operation

First, the detailed principle of operation and ZVS modula-tion scheme is explained for the 3-switch CL-TCM converter,based on the operating states and the corresponding inductorcurrent iL and switch-node voltage usw waveform shown inFig. 2.

A useful representation for the analysis of the ZVS oper-ation of the converter is provided by the state-plane diagram[22], [23], which in this case displays the switch-node voltageusw with respect to the inductor current iL scaled by thecharacteristic impedance of the resonant circuit formed by theinductor and the parasitic output capacitances of the switchesand diodes, as shown in Fig. 3(a). Assuming constant parasiticcapacitances, the resonant voltage and current transitions aredescribed with

Z0iL(t) = Z0IL,i cos (ω0t) + (u1 − Usw,i) sin(ω0t)

usw(t) = u1 − (u1 − Usw,i) cos(ω0t) + Z0IL,i sin(ω0t)(2)

which represents a circle with the center located at Z0iL = 0and usw = u1. At the beginning of the resonant transition, theinductor current has the value IL,i and the switch-node voltageis Usw,i. The radius of the circle can be expressed with

R =

√(u1 − Usw,i)

2+ (Z0IL,i)

2, with Z0 =

√L

Ctot, (3)

where Ctot is the total capacitance of the resonant circuit.Despite of the non-linearity of the parasitic capacitance of

the switches and diodes, the analysis provided in this paperconsiders constant capacitances only, in order to simplify theformalism and to give a meaningful insight into the operationof the converter. The analysis however could be extended tonon-linear capacitances as well, as it is shown in [2], [13], [24].Further it is assumed that the steady state input and outputvoltage u1 and u2 are constant, which is ensured by properinput and output filter design. The diode forward voltage dropsare denoted with uF,Dx and x ∈ [1, 4] and the turn-off processof each switch is considered to be free of power losses.

Starting with the first time interval [t0, t1], switch T2 isturned on and the body diode of switch T3 is blocking theinput voltage and prevents a short circuit of the input capacitorC1. Hence, the inductor current rises linearly. The inductorcurrent zero crossing is detected at t′0 in switch T2 and is usedto synchronize the switching times and the gate drive controlsignals si to the actual inductor current waveform as describedin Section IV. Hence, the remaining inductor current build-uptime interval T ′

on (cf. Fig. 1(a)) and the time interval Toff arecalculated such that the required average inductor current andthe current IL,0 needed at t4 to allow for ZVS of the switchesin the following time intervals, are achieved.

When the inductor current reaches the value IL,1 at timet1, switch T2 is turned off and the inductor current starts tocharge the parasitic output capacitance of switch T2, while

usw(t)

usw,t1’

u2

u1

Z0,R2IL,0

Z0,R2’IL,0

0

(a)

(b) (c)

Z0,R2IL,min

Z0iL(t)

R2

t0 = t8

t6

t7 t0t’

R2R’

I’

R1R’

R1

Z0,R1IL,1

Z0,R1’IL,1I’

Z0,R1IL,max

t1

t3t’

t2t4

t3

t5uF,D4

uF,D2

uF,D1

Tcl

usw

L

C1

iL

T3

[t1, t1]

u2

u1

uC,T3 uC,D4

t1t’

t’

usw

L

C1

iL

T3

[t1, t2]

u2

u1

D4

t’D4

CD4

CT1

CT2

CT1

CT2

CD4CT3 CT3

Figure 3: (a) state-plane diagram, showing the scaled inductorcurrent Z0iL(t) with respect to the switch-node voltage usw(t) forthe 3-switch CL-TCM converter operation. (b)-(c) Operating states ofthe converter during the time interval [t1, t′1] and [t′1, t2] respectively.

discharging the output capacitance of T1. Initially, the voltageacross the parasitic capacitance CT,3 is (u1 − uF,D4) andthe voltage across diode D4 is −uF,D4. Hence, the parasiticoutput capacitance of switch T3 is discharged and the junctioncapacitance of D4 is charged, as shown in Fig. 3(b). Dueto the series connection of CT3 and CD4, the total capac-itance that needs to be charged by the inductor current isCtot,R1 = CT1+CT2+CT3CD4/(CT3+CD4). The resonanttransition is described in the state-plane diagram with a circlearound the center located at usw = u1 and iL = 0 and a radiusgiven by

R1 =

√u21 + (Z0,R1IL,1)

2, and Z0,R1 =

√L

Ctot,R1. (4)

The maximum inductor IL,max = R1/Z0,R1 is reached assoon as the switch-node voltage usw is equal to the inputvoltage u1. At time t′1, the switch-node voltage at which thevoltage across T3 approaches zero voltage and its body diodeD3 starts to conduct, can be calculated according to

usw,t1′ = CT3+CD4

CD4(u1 + uF,D3 − uF,D4)

≈ CT3+CD4

CD4u1

, (5)

if uF,D3 ≈ uF,D4 applies. Note that if CD4 � CT3, the bodydiode of T3 will start to conduct as soon as usw approachesu1, where the inductor current reaches its maximum currentIL,max. In contrast, if CT3 > CD4, the capacitance CT3 canbe discharged to zero only if (u2 + uF,D1) ≥ usw,t1′ , whichis equal to (1) if the forward voltage drop of the diodes areneglected. If the condition (1) is not met, soft-switching ofswitch T3 cannot be achieved in the following operating states.

As soon as the body diode of T3 starts to conduct, thetotal capacitance of the resonant circuit changes to Ctot,R1′ =CT1 + CT2 + CD4, as it is shown in Fig. 3(c). Hence, the



4

characteristic impedance of the resonant circuit decreases,which appears as a discontinuity in the state-space trajectoryas shown in Fig. 3(a). The inductor current at time t′1 is givenby

I ′L,1 =1

Z0,R1

√R2

1 − (usw,t1′ − u1)2, (6)

and hence, using Z0,R1′ =√L/Ctot,R1′ , the radius R′1 can

be calculated according to

R′1 =

√(usw,t1′ − u1)

2+(Z0,R1′I ′L,1

)2

. (7)

If it is assumed that uF,D3 ≈ uF,D4 and CT3 = CD4,the switch-node voltage at time t′1 is usw,t1′ = 2u1 and theinductor current is IL,1 = I ′L,1, and hence, equation (7) isreduced to

R′1 ≈√u2

1 + (Z0,R1′IL,1)2. (8)

In this case, if the initial inductor current IL,1 is largeenough, CD4 is charged up to the voltage (u2−u1), assumingthat the diode D4 and the body diode of switch T1 have thesame forward voltage drop. At time t2, the body diode ofswitch T1 starts to conduct and clamps the voltage across T1

to the diode forward voltage drop uF,D1. If the diode voltagedrop uF,D1 is neglected, the condition for ZVS operation ofswitch T1 follows from R′1 ≥ (u2 − u1), and using (8), thecondition can be expressed with

IL,1 ≥1

Z0,R1′

√u2 (u2 − 2u1) , for (u2 > 2u1) . (9)

If conditions (1) and (9) are met, switch T1 can be turnedon at t3 at nearly zero voltage and since the parasitic outputcapacitance of T3 was discharged completely during [t1, t

′1],

switch T3 can be turned on at any time between t3 and t4without causing losses. The critical operating point, whereZVS of switch T1 could be lost is at minimum output powerand maximum output voltage.

During time interval [t3, t4] switch T1 is in on-state and theinductor current is supplied to the output and is decreasinglinearly and reverses its flow direction at time t′3.

At t4, switch T1 is turned off and the negative inductorcurrent IL,0 starts to discharge the parasitic capacitances ofswitch T2 and diode D4, while charging the output capacitanceof switch T1. Hence, during [t4, t5], the total equivalentresonant capacitance is Ctot,R2 = Ctot,R1′ = CT1+CT2+CD4

and the resonant transition is described in Fig. 3(a) as a circlewith a radius given by

R2 =

√(u2 − u1)

2+ (Z0,R1′IL,0)

2. (10)

As soon as the voltage usw reaches a value of (u1−uF,D4)at t5, the diode D4 starts to conduct and the inductor clampingtime interval [t5, t6] is initiated. During this interval, theinductor current is free-wheeling in the clamp-switch andno energy is delivered from the input to the output of theconverter. Hence, the clamping time interval can be used asa degree of freedom to control the switching period and theamount of power delivered to the load.

Due to the forward voltage drop of the diode D4, theinductor current is increasing with a slope of diL/dt =

uF,D4/L, if the ohmic losses in the inductor current loop areneglected. This needs to be taken into account, specificallyif the clamping time interval Tcl is large, since the inductorcurrent amplitude at t6, denoted with I ′L,0, could increase to avalue where ZVS of switch T2 could not be achieved anymoreat time t8. The negative inductor current I ′L,0 at the turn-offof switch T3 at t6 can be calculated with good approximationaccording to

I ′L,0 ≈ IL,min +uF,D4

LTcl and IL,min = − R2

Z0,R1′. (11)

During [t6, t7], the inductor current continues dischargingthe parasitic output capacitance of switch T2 and charges theparasitic output capacitance of T1. The output capacitance ofswitch T3 is charged as well by part of the inductor currentflowing through diode D4. Hence, the total equivalent resonantcapacitance changes to Ctot,R2′ = CT1 +CT2 +CT3 and theradius R′2 in Fig. 3(a) is given by

R′2 =

√u2

F,D4 +(Z0,R2′I ′L,0

)2

, and Z0,R2′ =

√L

Ctot,R2′.

(12)As soon as the switch-node voltage usw reaches a voltage

of −uF,D2 at t7, the parasitic output capacitance of switch T3

is charged up to the input voltage u1 and the diode D4 stopsconducting. At the same time, the body diode of switch T2

starts to conduct and the inductor current again starts to riselinearly as shown in Fig. 2 in the time interval [t7, t8]. Theswitch T2 can then be turned on at nearly zero voltage as longas the inductor current is negative, since its body diode wouldprevent a current flow in the reverse direction and the parasiticoutput capacitance of T2 would be charged again as soon asthe inductor current gets positive.

The condition for ZVS operation of switch T2 followsdirectly from condition R′2 ≥ u1 and is given by

I ′L,0 ≤ −1

Z0,R2′

√u2

1 − u2F,D4 ≈ −

u1

Z0,R2′, (13)

which is mainly dependent on the inductor current IL,0 andthe duration of the clamping time interval Tcl, if the input andoutput voltage are constant.

Note that if u2 ≥ 2u1 applies and considering traditionalTCM operation only, i.e. Tcl = 0, a zero voltage transitionof the switch-node voltage usw in the time interval [t′3, t7]can always be achieved, even when starting with an inductorcurrent IL,0 = 0. This allows to reduce the converter hardwarecomplexity further, by replacing the switch T1 by a singlediode D1 as shown in Fig. 4(a). This modification allowsto increase the converter reliability as the number of activecomponents in the circuit is reduced. However, the conductionlosses are increased as well, but compared to the powerlosses occurring in the case of a hard-switched boost convertersolution, the additional diode conduction losses are acceptable.

The operation principle, the limitations and the conditionsfor ZVS operation of the 2-switch CL-TCM converter areexplained in the following, based on the state-plane diagramshown in Fig. 4(b), which depicts the resonant transitionduring the time intervals with negative inductor current.



5

t0 = t8

usw(t)

uF,D4

u2

u1

Z0,R2’IL,0

0Z0,R2IL,min Z0iL(t)

R2

Tcl

t6

t0t’I’

ZVSHSW

uF,D1

t5

t7

R2R’

t3 = t4t’

Output Voltage (V)(b) (c)

25 30 35 40 45 50

Out

put P

ower

Ran

ge (W

)

5

10

15

20

25

30ZVS lines of constant

boost inductance

ZVS boundaryfp = 200 kHz

ZVS boundaryfp = 400 kHz

HSW

200 kHz

800 kHz

L iL

uswC1

i1i0

u1 T2

C2 RL

i2 iR

(a)

u2

D4

D1

T3

400 kHz

600 kHz u1 = 12 V

Figure 4: (a) 2-switch CL-TCM converter topology. (b) Associ-ated state-plane diagram showing the resonant transition during thetime intervals with negative inductor current. (c) Region of Zero-Voltage-Switching (ZVS) and Hard-Switching (HSW) operation forthe 2-switch CL-TCM converter with respect to output power, forthe converter designed for different output voltages and switchingfrequencies fp in the range of 200 kHz to 800 kHz.

B. 2-Switch CL-TCM Operation

The states of operation during [t0, t2] are the same as forthe 3-switch CL-TCM converter. If condition (9) is met, diodeD1 starts to conduct at t2 and the inductor current startsto decrease linearly. Switch T3 can be turned on at anytime between t2 and t′3, without causing switching losses. Att′3 = t4, when the inductor current reverses its flow direction,D1 stops to conduct naturally and the resonant transition isinitiated. The inductor current starts to charge the junctioncapacitance of D1 and as soon as the switch-node voltage usw

reaches a value of (u1−uF,D4), close to the minimum inductorcurrent IL,min, the clamping time interval is started. Thedecrease of the switch-node voltage, as a result of D1 blockinga current flow in the reverse direction, can be detected easily.Hence, also the start of the clamping time interval at t5 canbe detected without the need for an additional inductor currentzero crossing detection and allows to simplify the controllerimplementation, as it is explained in detail in Section IV.

After the clamping time interval Tcl, switch T3 is turned offand the inductor current further discharges the parasitic outputcapacitance of switch T2. If the the negative inductor currentI ′L,0 at t6 is large enough, the voltage across T2 is reduced tozero and at t7 its body diode starts to conduct. Hence, switchT2 can be turned on at nearly zero voltage at time t8.

Since the inductor current IL,0 at the beginning of theresonant voltage transition at t4 is zero and cannot be con-trolled, the ZVS operation of switch T2 at t7 depends onthe input-to-output voltage ratio, the characteristic impedanceof the resonant circuit and on the duration of the clampingtime interval Tcl, and hence also on the output power of theconverter. The radius R2 of the circle describing the resonant

transition in the state-plane diagram in Fig. 4(b) is given byR2 = (u2 + uF,D1 − u1) and hence, the minimum inductorcurrent IL,min can be expressed with

IL,min = − R2

Z0,R2, and Z0,R2 =

√L

CD1 + CT2 + CD4.

(14)The radius R′

2 of the circle describing the resonant transitionafter the clamping time interval (cf. Fig. 4(b)) is given in (12),using Ctot,R2′ = CD1 + CT2 + CT3. In order to allow forZVS for switch T2 at time t8, the condition R′

2 ≥ u1 mustbe fulfilled. By taking (11) for the inductor current I ′L,0 andassuming that u2

F,D4 �(ZZ0,R2′I

′L,0

)2applies in (12), the

ZVS condition for T2 can be expressed with

1

Z0,R2(u2 + uF,D1 − u1)−

uF,D4

LTcl ≥

u1

Z0,R2′. (15)

If it is further assumed that (u2 + uF,D1 − u1) ≈ (u2 − u1)and Z0,R2 = Z0,R2′ = Z0, i.e. if CT3 = CD4, condition (15)is simplified to

u2 ≥ 2u1 + Z0uF,D4

LTcl . (16)

Note that if the clamping-time interval Tcl = 0, i.e. atmaximum output power, expression (16) is reduced to thecondition u2 ≥ 2u1, which is equal to the ZVS conditionof the traditional TCM operation with iL,0 = 0 [2].

As an example, Fig. 4(c) shows the ZVS boundary accord-ing to (16), where the 2-switch CL-TCM converter is designedaccording to (17)-(22), as described in Section III-A, fora fixed input-to-output voltage conversion ratio, a maximumoutput power of Pmax = 30W, and a switching frequencyfp ranging from 200 kHz to 800 kHz. It is evident that ata voltage conversion ratio of u2 = 2u1, the 2-switch CL-TCM converter allows ZVS operation only at the specifiedmaximum output power, which corresponds to the traditionalTCM operation, and as soon as the output power is re-duced, the introduction of the clamping time interval leadsto hard-switching immediately. This is a main limitation ofthe 2-switch CL-TCM converter. However, at larger voltageconversion ratios, the output power range allowing for ZVSoperation is extended significantly, and is highly dependenton the specified switching frequency and input voltage of theconverter, as these parameters determine also the value of theboost inductance.

However, the 3-switch CL-TCM converter allows for ZVSoperation even in the hard-switching region of the 2-switchCL-TCM converter, since it allows to adjust the negativeinductor current IL,0 accordingly in order to achieve zero-voltage-switching.

III. OPERATING MODES

In this section, two operating modes of either the 2-switchor 3-switch CL-TCM converter are outlined and equations forthe calculation of the boost inductance value and the switchingtime intervals Ton, T ′

on, Toff and Tcl are provided.



6

u2,max

t t

Pmax

u2,min

u2,max

u2,min

fp,min

fp,max

Tp,min Tp,max Tp,const

Pmin(a)

D

C

CB

A

(d)

(b) (e)

(c) (f)

00

AA

D

IL,minIL,minI’

IL,maxI’

IL,min

IL,max IL,max

iL(t) iL(t)

D

Pmax

Pmin

CIL,rms

(min)

IL,rms(max)

DA

B

u2,maxPmax

u2,min

fp,const

Pmin

CAD

B

B

u2,max

u2,min

Pmax

Pmin

C

IL,rms(min)

IL,rms(max)

DA

B

C B

Figure 5: Switching frequency variation, inductor RMS currentvariation and inductor current waveforms for variable switchingfrequency operating (a)-(c) and for constant switching frequencyoperation (d)-(f).

A. Variable Switching Frequency Operation

The main objectives of the first mode of operation is theminimization of the switching frequency variation and thesimultaneous minimization of the inductor RMS current fora variable output power P ∈ [P2,min, P2,max] and a variableoutput voltage u2 ∈ [u2,min, u2,max]. It is assumed that theinput voltage u1 has a constant value. As explained above,the clamping time interval Tcl is used as an additional degreeof freedom to control the switching frequency variation of theconverter. Considering the typical inductor current waveformsshown in Fig. 1(b) and (c), it is beneficial to emulate TCMoperation at maximum output power, i.e. by reducing theclamping time interval Tcl to zero [8], and hence reducingthe inductor RMS current to a minimum, while maintainingZVS operation. This however implies, that if the minimuminductor current IL,min is fixed, the switching frequency willvary with changes of the input and/or the output voltage, dueto the changing slopes of the inductor current. In contrast,if the terminal voltages are fixed and the output power isvaried, the switching frequency can be maintained constantby introducing the clamping time interval. The inductor RMScurrent could be reduced only by increasing the switchingfrequency, while approaching the TCM operation again, whichis not desirable in this case.

As reported in [8] for constant switching frequency opera-tion, and assuming a lossless operation of the converter, i.e.P1 = P2, the inductor must be designed according to

L =u1 (u2,min − u1)

2u2,minfp,min (P1,max/u1 − IL,min), (17)

in order achieve TCM operation at maximum output powerand minimum output voltage u2,min. If, as described in thefollowing, a variable switching frequency is allowed, theconverter operates always at or above the minimum switchingfrequency fp,min.

For an accurate calculation of the switching time intervalsTon, T ′

on, Toff and Tcl, the increase of the minimum inductorcurrent IL,min to

I ′L,0 = IL,min +uF,D4

LTcl , (18)

during the clamping time interval cannot be neglected. Thisis specifically the case for the operation at low output powerand low output voltage when the clamping time interval Tcl

is large. Assuming that the resonant voltage transition timeintervals are much shorter than the switching period, the timeinterval Ton can be calculated for a desired average inputcurrent I1,avg = P1/u1 using

Ton = Lu1

√4I1,avg

(P1,max

u1− IL,min

)+ I2L,min

− Lu1IL,min − uF,D4

u1Tcl

, (19)

which is independent of the output voltage variation. Theswitching time intervals labeled with Toff and Tcl (cf. inFig. 1(b) and (c)) are calculated according to

Toff =Ton (uF,D4 − u1)− Tp,P(max)uF,D4

u1 − u2 − uF,D4, (20)

Tcl = Tp,P(max) − Ton − Toff , (21)

using the switching period Tp, evaluated for the nominal inputpower P1,max, which follows from (17) and is given by

Tp,P(max) =2u2L (P1,max/u1 − IL,min)

u1 (u2 − u1). (22)

After the clamping time interval, the inductor current startsrising from I ′L,0 and at the current zero crossing at t′0, theremaining on-time interval T ′

on is set by the control circuit,which is calculated with

T ′on = Ton +

L

u1IL,min +

uF,D4

u1Tcl . (23)

Note that the switching time intervals are calculated iter-atively, since the clamping time interval Tcl is not knowninitially. Hence, starting with Tcl = 0 in (19), the switchingtime intervals (19)-(21) and (23) can be calculated withinfew iterations. In order to further improve the accuracy ofthe inductance and switching time interval calculations, theDC-DC efficiency ηP(max) at maximum output power can beestimated in advance and hence, the predicted maximum inputpower P1,max = P2,max/ηP(max) can be used in (17) and (19)-(22).

Using (17) and (22), the maximum switching frequency canbe calculated according to

fp,max = fp,min · u2,min

u2,max· (u2,max − u1)

(u2,min − u1), (24)

which is obtained at maximum output voltage and is indepen-dent of the output power. Note that for large input to outputvoltage conversion ratios u2 � u1, the switching frequencyvariation is very small, i.e. fp,min ≈ fp,max.



7

B. Constant Switching Frequency Operation

Generally, a varying switching frequency operation is notdesired in EMI sensitive applications as it spreads the noiseemissions over a wide spectral range and therefore complicatesthe filter design. Therefore, the second mode of operationallows to maintain a constant switching frequency by adjustingthe clamping time interval and/or the minimum inductor cur-rent [8]. Note that this mode of operation cannot be achievedwith the 2-switch CL-TCM converter, since the magnitude ofthe minimum inductor current IL,min must be controllable.

The boost inductance can be calculated according to (17)with the desired constant switching frequency fp,const. In orderto maintain the switching frequency while the output voltageis allowed to vary, the minimum inductor current IL,min needsto be adjusted during the converter operation according to

I ′L,min =u21 (u1 − u2) + 2Lfp,constP1,maxu2

2Lfp,constu1u2. (25)

The switching time intervals Ton, T ′on, Toff and Tcl can then

be calculated by inserting (25) into (18)-(23) and Tp,P(max) =1/fp,const into (20)-(21).

In order to outline the differences of the variable andthe constant switching frequency operation, the switchingfrequency variation, the RMS inductor current - which givesan indication for the converter power losses - and the typicalinductor current waveforms are illustrated in Fig. 5(a)-(f)for both modes. The CL-TCM converter is operated withvariable output voltage and variable output power, and isdesigned for the same minimum switching frequency. Fig. 5(a)shows the variation of the switching frequency for the firstoperating mode. The switching frequency is kept constant fora fixed voltage conversion ratio and increases with increasingoutput voltage. In contrast, the RMS inductor current remainsconstant for a fixed output power and variable output voltageand is increasing almost linearly with increasing output powerand fixed output voltage, as it is shown in Fig. 5(b). Theinductor current waveforms for the converter operating pointslabeled with (A)-(D) are shown in Fig. 5(c).

The constant switching frequency operating mode of theCL-TCM converter (cf. Fig. 5(d)) comes at the expense of anincreased RMS inductor current at higher voltage conversionratios, as it is shown in Fig. 5(e). Hence, the converter powerlosses are increased at high output voltage, due to the largerpeak-to-peak inductor current ripple shown in Fig. 5(f), whichis necessary to maintain the constant switching frequency.Therefore, this mode of operation should be used only forapplications which inherently limit the variation of the inputand output voltage to a narrow range or which have a largevoltage conversion ratio.

In the following section, the controller implementation forthe CL-TCM converter operated at variable switching fre-quency is explained in detail.

IV. CONTROLLER IMPLEMENTATION

A. 3-Switch CL-TCM Control

The inductor current zero crossing detection is the keyfeature that is required to implement the digital control of

update Ton, Toff, Tcl

L C2

Rzc

C1

iL

iT2

iR

iT2

i1i0

T1

T2T3 D4

u1

u2

u2

uzc,ref

uzc,ref

FPGA

T3

uGD

uGD

uGD

Tcl

um

ToffTonT’

Tcl

Toff

TonT’

iL(t)

s1s2s3

t

ttt

t

u1, i0u2, iR

DSP

TTTupdate update

tc < Ton’

1

yes

(a)

(b) (c)

(d)

noCDout == 1

CDout == 0

FSMTimingcalc.F

?

tc < Tdead,1

2

tc < Toff

3

tc < Tcl

4

tc < Tdead,2

5

tc < Tblank

6

1 17 2 3 4 5 6 7 7

CDen = 0

CDen = 1

’

iL

Ton,’ Toff,Tcl

CDout CDen = 1†

† †

†

†

†

**i0

iRu2

u1s1s2s3

† current zero crossing detector output signal and enable signal.

Figure 6: (a) Realization of the control circuit and current zerocrossing detection for the 3-switch CL-TCM converter. (b) 3-switchCL-TCM current waveforms, modulator states and (c) modulator statemachine. (d) 3-switch CL-TCM output voltage control with loadcurrent feed-forward.

the 3-switch CL-TCM converter. An effective implementationof the zero crossing detection is shown in Fig. 6(a), wherethe low-side switch current iT2 is sensed in order to detect thecurrent zero crossing at the rising edge of the inductor current,as it is illustrated in Fig. 6(b). The timing values T ′

on, Toff andTcl are calculated by a Digital Signal Processor (DSP) andare transmitted to a Field Programmable Gate Array (FPGA),which implements the modulator Finite State Machine (FSM)shown in Fig. 6(c) and which generates the gate control signalssi, i ∈ [1, 3]. A counter tc within the FPGA is used to setthe duration of the switching time intervals. After the on-timeT ′on in state 1 has expired, the current zero crossing detector

is disabled and the modulator enters state 2, which sets thefirst dead-time interval Tdead,1 for the switches. In state 3,switch T1 and T3 are enabled and with the expiration of Toff ,the modulator enters the clamping time-interval in state 4,followed by the second dead-time interval in state 5. After thedead-time, switch T2 is turned on and the current zero crossingdetector is enabled. However, its output is blanked in the firstplace in order to prevent the detection of an erroneous currentzero crossing due to the charging of the boot-strap capacitorsof the high-side gate drivers or due to a hard-switching eventat the turn-on of switch T2. After the blanking time interval,which can be as short as 100 ns, the current zero crossingdetector output signal is evaluated. If the detector output isindicating that the inductor current is already positive, thestate machine continues with state 2 in order to reduce theinductor current until its value is below zero when exiting



8

L

C2C1

iL iRi1i0

T2

T3

D1

D4

u1

u1

u2

u2

usw

usw

u1FPGA

T2

T3

uGD

uGD

Tcl

um

ToniL(t)

s2s3

t

tt

t

u1, i0u2, iR

DSP

1 12 3 4 5

iL

Ton,’ Toff,Tcl

5

CDoutCDen = 1†

†

†

†

†

†

clamping intervaldetector output and enable signal.

tc < Ton

1

(c)

CDout == 0

tc < Tdead,1

2

3

tc < Tcl

4

tc < Tdead,2

5

CDen = 1

CDen = 0

(b)

(a)

update Ton, Tcl

Figure 7: (a) Realization of the control circuit for the 2-switch CL-TCM converter. (b) 2-switch CL-TCM current/voltage waveforms,modulator states and (c) modulator state machine.

state 6. If the inductor current is negative at the end of state6, the modulator enters state 7 and waits for the detection ofthe current zero crossing, which then triggers the start of themodulation sequence from the beginning.

A very simple and effective implementation of the outputvoltage control of the converter is shown in Fig. 6(d). Asingle PI-controller and a load current feed-forward is usedto set the input current target i∗0. Since the inductor currentcan be controlled directly cycle by cycle, the converter allowsfor a highly dynamic operation. However, since the evaluationof the timing values is computationally expensive, the valuesT ′on, Toff and Tcl may be updated only every n-th cycle, i.e.

the modulator state machine runs with the same set of timingvalues for few switching cycles until the values are updatedat the beginning of the first state (cf. Fig. 6(b)). Further notethat for the controller implementation it is not necessary tocalculate the timing values iteratively for every update, sincethe iteration process is performed within the periodic controlsequence, using the last clamping time interval Tcl as initialcondition for the next timing calculation.

Another solution to determine the timing values is togenerate a look-up table with pre-calculated timing values andto interpolate the actual values online, according to the look-up table and the measured input and output voltage and theinput current set-point.

B. 2-Switch CL-TCM Control

The realization of the control circuit of the 2-switch CL-TCM converter is shown in Fig. 7(a). In this case, thesynchronization of the modulator state machine to the inductorcurrent can be realized with very little hardware effort. Asshown in Fig. 7(b), if the current in D1 reaches zero within thefalling edge of the inductor current, D1 stops to conduct andthe switch-node voltage usw starts to decrease. As soon as theswitch-node voltage falls below the input voltage u1, D4 starts

(b)

(a)

14.3 mm17.5 mm

ValueParameter

7.8 mm InductanceLitz wireNumber of turnsCore materialCoreTotal air gapPower density

7.51 µH300 x 40 µm9N872x EELP 140.56 mm15.4 W/cm3

load connector

main switches

clamp switch

inductor connector

input capacitor

auxiliary power supply

output capacitor

gate driver

inputpower source

connector

DSP

FPGA

Figure 8: (a) Hardware prototype of the CL-TCM converter in-cluding the FPGA/DSP control board. (b) Realization and technicalspecifications of the inductor used for the measurements.

to conduct and initiates the clamping time interval. As a mainadvantage of the 2-switch topology, the start of the clamp-switch time interval can be detected easily by comparing theswitch-node voltage usw with the input voltage u1, as shownin Fig. 7(b), using a comparator circuit with a propagationdelay as small as 5 ns and a very low hardware effort.

The modulator state machine is shown in Fig. 7(c). After thepre-calculated on-time Ton and the first dead-time interval haveexpired, the clamping interval detector is enabled and switchT3 is enabled. The decreasing inductor current is suppliedto the output via diode D1 and the modulator state machinewaits in state 3 for the rising edge of the detector outputsignal, indicating that the clamping interval is initiated. Afterthe clamping time interval Tcl has expired, T3 is turned offand after a short dead-time interval, the control sequence startsfrom the beginning. The output voltage control of the 2-switchCL-TCM converter can be implemented as shown in Fig. 6(d).

In the following section, the operating modes and the ZVSoperation of the CL-TCM converter are verified experimentallyusing a hardware prototype.

V. MEASUREMENTS

Fig. 8(a) shows the hardware prototype of the CL-TCMconverter. The EPC2016C GaN FETs are used for the switchesT1-T3, operated with the half-bridge gate driver LM5113. Forthe diode D4 the Schottky diode MBR1H100SFT3G was usedbecause of its low forward voltage drop and is also placed inanti-parallel configuration with each GaN FET. Note that theprototype includes a GaN FET in parallel to D4 as well, inorder to allow for the 4-switch CL-TCM operation presentedin [13], which however is turned off permanently during the2-switch and 3-switch CL-TCM converter measurements. Theconverter is controlled with a DSP/FPGA board comprising a



9

Time (µs)(a) (b) (d)(c)0

Indu

ctor

Cur

rent

(A)

-2

0

2

4

6

8

Indu

ctor

Cur

rent

(A)

-2

0

2

4

6

8

1 2 3 4 5 6Time (µs)

0 1 2 3 4 5 6

Pmax

Pmax

PminPmin

Time (ns)Time (ns)

Cur

rent

(A)

Vol

tage

(V)

00.51.01.52.02.5

01020

0 100 200 300-0.50

0 50 100 150 200 250

304050

-10-5

0

5

10

15

400

-0.25

0

0.25

0.50

0.75

Vol

tage

(V)

Cur

rent

(A)

uswusw

umu1

um

iL

iLs2

s2s3

s1, s3

T1,ZVS

T3,ZVS

T2,ZVS

td,gd

uF,D4

u1u2u2

= 12 V= 40 V= 60 V

u1u2u2

= 12 V= 40 V= 60 V

u1u2P2

= 12 V= 48 V= 5 W

u1u2P2

= 12 V= 48 V= 5 W

td,gd td,gd

u1

Figure 9: Measurement of the inductor current waveform for the variable switching frequency operation (a) and constant switching frequencyoperating mode (b) of the 3-switch CL-TCM converter. (c)-(d) Verification of the ZVS operation of the switches T1, T3 and T2 respectively.

Texas Instruments TMS320F28335 DSP and a Lattice LFXP2-5E FPGA. The specifications and the realization of the induc-tor used for the measurements are shown in Fig. 8(b).

During the measurements, the converter was operated inopen-loop mode and the timing values for the modulatorstate-machine are calculated offline. The input voltage is setto a constant value of 12 V. The output voltage range isset to 40-60 V, with a nominal output voltage of 48 V, astypical e.g. for telecom applications, and the output powerrange is set to 5-30 W. Fig. 9(a) shows the inductor currentwaveform for the variable switching frequency operating modeof the 3-switch CL-TCM converter. It can be seen that theswitching frequency varies only by a factor 1.14 between175 kHz and 199 kHz, which is due to the large voltageconversion ratio. In Fig. 9(b), the inductor current waveformsare shown for constant switching frequency operation and theincreased peak-to-peak inductor current ripple at the higheroutput voltage is clearly evident. In this case however, theRMS inductor current is only a factor of 1.03-1.23 highercompared to the variable frequency operating mode.

The ZVS operation of the switches T1-T3 is shown inFig. 9(c) and (d) for an output voltage of 48 V and at minimumoutput power. In Fig. 9(c) the resonant voltage transition of theswitch-node voltage usw is shown at the maximum inductorcurrent. The voltage transition is initiated with the turn-offthe switch T2 after a gate drive propagation delay td,gd ofapproximately 27 ns. The inductor current is large enough todischarge the parasitic output capacitance of switch T1 wellwithin the dead-time interval of 50 ns. The output capacitanceof switch T3 is discharged even faster as indicated by theclamp-switch midpoint voltage um. Hence, the two switchesT1 and T3 can be turned on simultaneously after the dead-time interval without causing switching losses. At the end ofthe clamping time interval shown in Fig. 9(d), the resonantvoltage transition is initiated with the turn-off of switch T3.The negative inductor current discharges the parasitic outputcapacitance of switch T2 until its diode starts to conduct.Accordingly, switch T2 can be turned on at nearly zero voltageafter the dead-time interval of 100 ns.

The results for the 2-switch CL-TCM converter operationare shown in Fig. 10 for a fixed input and output voltage of12 V and 48 V respectively. Fig. 10(a) shows the measuredinductor current waveforms for variable output power andFig. 10(b) shows the verification of the calculation of theswitching time intervals according to (14) and (19)-(22).

Cur

rent

(A)

Vol

tage

(V)

6

4

2

0

60

40

20

0

-20

Cur

rent

(A)

6

4

2

0

-2

Cur

rent

(A)

6

4

2

0

-2

Vol

tage

(V)

Tim

e (u

s)

60

40

20

4

3

2

1

0

-20

0

Time (µs)0-2-4 2 4

Time (µs)

Output Power (W) Output Power (W) Output Power (W)

0

5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30

-4 -2 2 4

Pout = 5 W

Pout = 30 W

usw

iL

iL

(a)

(c)

(b)

P2,max = 30 W

P2,min = 5 W

P2

u1u2

= 12 V= 48 V

iL usw

meas.calc.

meas.calc.

meas.calc.

Ton

Toff Tcl

Figure 10: (a) Measurement of the inductor current waveformsfor the 2-switch CL-TCM converter operation for fixed input/outputvoltages and variable output power. (b) Measured and calculatedswitching time intervals Ton, Toff and Tcl. (c) Measured waveformsof the switch-node voltage usw and the inductor current waveformfor minimum and maximum output power.

In order to simplify the calculation, it is assumed that theconverter causes no power losses and that the capacitancesCD1, CT2 and CD4, used in (14), have a value of 352 pF,which is the total charge equivalent capacitance [24] of theEPC2016C GaN FET in parallel to the Schottky diode at anoutput voltage of 48 V. For the diode forward voltages a valueof 0.6 V is used, which is the typical forward voltage drop ofthe Schottky diode MBR1H100SFT3G at 300 mA and 25 ◦C.The measured waveforms of the switch-node voltage usw and



10

1.41.21.00.80.60.40.2

0

Output Power (W)

Pow

er L

oss (

W)

5 10 15 20 25 30Output Power (W)(a) (b) (c)5 10 15 20 25 30

100

98

96

94

92

90

Effic

ienc

y (%

)

Output Power (W)5 10 15 20 25 30

6543210

-1

Curre

nt (A

)

IL,max

IL,rmsIL,min

2-switch 3-switchCL-TCM operation: 4-switch†

† 4-switch CL-TCM operation according to [12] and [13].

u1u2

= 12 V= 48 V

Figure 11: (a)-(b) Measured DC-DC efficiency and power loss atvariable output power, for the proposed 2-switch and 3-switch CL-TCM operation as well as for the 4-switch CL-TCM operation ex-plained in [12], [13]. Note that these measurements do not include theconstant power loss of the DSP/FPGA control board. (c) Measuredminimum, maximum and RMS inductor current.

the inductor current iL are shown in Fig. 10(c) for minimumand maximum output power.

The measured DC-DC efficiency and the power loss ofthe proposed converter operations are shown in Fig. 11(a)and (b) respectively. The input and output power is calcu-lated, based on the measurement of the terminal voltagesand currents using Agilent 34410A multimeters. The powerloss caused by the current and voltage measurement circuits,which amount to 37.2 mW and the gate-drive power lossesare measured separately and are included in the total powerloss and efficiency calculation. However, the measurementsdo not include the constant power loss of 994 mW caused bythe DSP/FPGA control board, since it is not optimized forthe hardware prototype at hand and it could be designed withsignificantly reduced footprint and power loss.

As shown in Fig. 11(a), a maximum efficiency of 97.2 %was obtained for the 3-switch CL-TCM operation at maxi-mum output power. The efficiency of the 2-switch operationis almost 1.5 % lower compared to the 3-switch operation,which is due to the conduction losses caused in diode D1.It is important to note, that the diodes used in the hardwareprototype are intended to lower the voltage drop across theGaN switches during the short dead-time interval and are notsuited to carry the inductor current for a much longer time.Therefore, a more suitable diode such as the V10PL45-M3Schottky rectifier diode could be used for D1 to improve theefficiency of the 2-switch CL-TCM converter.

In order to provide a complete comparison, the DC-DCefficiency is measured as well for the 4-switch CL-TCMconverter operation proposed in [13]. It can be seen inFig. 11(a) that the 4-switch CL-TCM converter achieves ahigher efficiency at low output power when compared tothe 3-switch operation, which is due to the decreased powerlosses occurring during the clamping time interval. However,at maximum output power, the 4-switch CL-TCM convertershows a lower performance, because of the increased diodeconduction power loss during the dead-time intervals.

The minimum and maximum inductor current, as well asthe RMS inductor current is shown in Fig. 11(c) for eachconverter operation. The minimum inductor current cannot be

controlled for the 2-switch CL-TCM converter operation andtherefore, the same negative current was chosen for the 3-switch and 4-switch CL-TCM converter operation, in orderto achieve the same operating frequency, which is in a rangeof 187-194 kHz. As expected, the maximum and the RMSinductor current do not significantly differ among the differentCL-TCM converter operations. Hence the main differences inthe power loss measurement mainly arise from the differentdiode conduction losses and also from the different gate-drivepower losses, as the number of active switches varies for thedifferent CL-TCM converters.

VI. CONCLUSIONS

The CL-TCM DC-DC boost converter allows for ZVSof all switches and offers a significantly reduced switchingfrequency variation when compared to the traditional TCMoperation [13], which in turn simplifies the filter design inEMI sensitive applications and relaxes the requirements forthe digital control.

In this paper, two CL-TCM boost converter topologies withreduced hardware complexity and its ZVS modulation schemesare proposed. Additionally, the limitations for ZVS operation,the timing calculations and the controller implementation arepresented and analyzed in detail for both converter topologies.The reduced complexity of the CL-TCM converter hardwareand modulation scheme, however, comes at the expense of aunidirectional power flow and a restriction on the minimuminput-to-output voltage conversion ratio, which is required toensure ZVS operation for all the switches.

In addition to the ZVS modulation schemes, two operatingmodes of the CL-TCM converter are compared in this pa-per. The first operating mode allows for minimum switchingfrequency variation and a minimized RMS inductor current,which is achievable with both the 2-switch and the 3-switchCL-TCM converter. The second mode of operation allows forconstant switching frequency operation and is achieved withthe 3-switch CL-TCM converter only, because it allows tocontrol the negative inductor current. However, the constantswitching frequency operation has limitations regarding theconverter efficiency, since the RMS inductor current increasesas the output voltage is increased. Hence, this mode ofoperation is intended mainly for applications requiring a smallinput or output voltage operating range or a high voltageconversion ratio.

It is important to note that the modulation scheme and theoperating modes presented in this paper are not limited to CL-TCM boost converters only, but could be adapted easily for anunidirectional buck-type CL-TCM converter operation as well.Further note that the CL-TCM converter topologies presentedin this paper and in [13] deliver their benefits specificallyin applications with higher output voltage and higher outputpower, where the control power losses are negligible.

ACKNOWLEDGMENT

The authors gratefully acknowledge the financial supportby the Baugarten foundation. This work is part of the ZurichHeart project under the umbrella of “University Medicine



11

Zurich/Hochschulmedizin Zurich”. Further thanks goes toAndres Cao for the design of the hardware prototype in thecourse of his semester project.

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Oliver Knecht (S‘14) received the M.Sc. degree inelectrical engineering from the Swiss Federal Insti-tute of Technology (ETH) Zurich, Zurich, Switzer-land, in 2013, where he is currently working towardthe Ph.D. degree at the Power Electronic SystemsLaboratory. During his studies he focused on powerelectronics, control systems and microwave electron-ics. His current research interests include the anal-ysis, design and control of inductive power transfersystems for medical applications.

Dominik Bortis (M‘08) received the M.Sc. degreein electrical engineering and the Ph.D. degree fromthe Swiss Federal Institute of Technology (ETH)Zurich, Switzerland, in 2005 and 2008, respectively.In May 2005, he joined the Power Electronic Sys-tems Laboratory (PES), ETH Zurich, as a Ph.D.student. From 2008 to 2011, he has been a Post-doctoral Fellow and from 2011 to 2016 a ResearchAssociate with PES, co-supervising Ph.D. studentsand leading industry research projects. Since January2016 Dr. Bortis is heading the newly established

research group Advanced Mechatronic Systems at PES.

Johann W. Kolar (F‘10) received his Ph.D. degree(summa cum laude) from the Vienna University ofTechnology, Austria. He is currently a Full Professorand the Head of the Power Electronic Systems Lab-oratory at the Swiss Federal Institute of Technology(ETH) Zurich. He has proposed numerous novelPWM converter topologies, and modulation andcontrol concepts and has supervised over 60 Ph.D.students. He has published over 750 scientific papersin international journals and conference proceedings,3 book chapters, and has filed more than 140 patents.

He has presented over 20 educational seminars at leading international confer-ences, has served as IEEE PELS Distinguished Lecturer from 2012 through2016, and has received 25 IEEE Transactions and Conference Prize PaperAwards, the 2014 IEEE Power Electronics Society R. David MiddlebrookAchievement Award, the 2016 IEEE William E. Newell Power ElectronicsAward, the 2016 IEEE PEMC Council Award, and the ETH Zurich GoldenOwl Award for excellence in teaching. He has initiated and/or is the founderof 4 ETH Spin-off companies. The focus of his current research is on ultra-compact and ultra-efficient SiC and GaN converter systems, wireless powertransfer, Solid-State Transformers, Power Supplies on Chip, as well as ultra-high speed and ultra-light weight drives, bearingless motors, and energyharvesting.



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