yield optimization using power gating

5/25/2018 yield optimization using power gating

1/29

Dissertation Part I Presentation

Yield Optimization in VLSI Circuits using

Power Gatingin

Partial Fulfillment of Degree of Master of Technology (M. Tech.) Semester IIIby

Swati S. Kumar(2012PUSETMVLX01587)

(Session 2013-14)

Under supervision ofMr. Gaurav Soni

Assistant Professor

Department of Computer Engineering

School of Engineering & Technology

Poornima UniversityIS-2027 to 2031, Ramchandrapura, Sitapura Extension, Jaipur-303905 (Raj.)

2/27/2014 1


2/29

Contents Introduction / Motivation

Literature Review

Details of Review: Which include summary table of

number of research papers in each category.

Issue wise: Solution Approaches & Results: Just

Comparison

Strengths and Weaknesses: Final outcome of review in brief

Problem Statement & Objectives

Design Specifications: With proposed selected hardware /

software / platform / tool / Methodology

Experimentations carried out & results

Conclusion

References

6/6/2014 Yield Optimization In VLSI Circuits 2


3/29

Introduction / Motivation (1/2)

Continuous technologyscaling and increasingclock frequency =

increasing POWER Increasing demand of

Portable devices

Leakage powerincreasesexponentially


Fig 1: Increase in leakage power with shrinking CMOS

technologies


4/29

Introduction (1/2)

Leakage Power Reduction Techniques

oMTCMOS

o DTCMOS

o Sleep Transistors

o Power Gating



5/29

Literature Review

40 papers were reviewed to optimize the yield in VLSIcircuits

Review Process Stages Adopted : Stage 0: Get the Feel Stage 1: Get Big Picture Stage 2: Get the Details Stage 3: Evaluate the Details Stage 3 +: Synthesize the Details.



6/29

Literature Review

Literature review of Yield Optimization in VLSI

Circuits paper is categorized into following issues:

a) Power Optimization

b) Delay Optimization



7/29

Issue Wise Solution Approaches

6/6/2014 Yield Optimization in VLSI Circuits 7

S. No. Authors Year Approach Results

1 K.R.N

Karthik et al

[2]

2013 The optimal reverse body bias voltage is

generated from the leakage circuit and

calculated the sub-threshold current.

Reduction of leakage

power in both active

and stand-by mode.

2 Ruchika

Mittal

et al[4]

2013 High threshold voltage devices are inserted in

series to low threshold voltage circuitry

Reduced leakage

power is obtained.

3 Raghuvir

singh

et al[21]

2011 Driver interconnect load system were used. 25% line variation

was reduced.

4 M. Geetha

Priya

et al[14]

2012 DTMOS (dual threshold MOS) Easy fabrication with

minimal circuit is

obtained.

Issue 1 : Power Optimization in VLSI Circuits


8/29



5. Rajani H.P. et al[11] 2012 Novel sleep transistors used for

peripheral circuits based on state

retention technique.

Power reduction achieved

by X3.5 factor

6 Dr. K Srinivasa Rao

et al.[18]

2011 Multi threshold metal oxide

semiconductor was used.

Reduced leakage power

was obtained.

7. Rashmi Bahal et al 2012 7TSRAM cell in deep submicron

regime were used.

Good estimation of total

leakage in the logic

circuits.

8 M. Madhavi Latha

et al[9]

Galeorstack technique was used. Reduction in leakage

power with no increase in

delay.

10 M. Janaki Rani

et al[15]

2012 Self adjustable voltage

technique.

Reduced level of power

dissipation compared to

the other conventional

techniques.


9/29



Delay Optimization In VLSI circuitsS. No. Authors Year Approach Results11 Gyan prakash et

al[5]

2012 10TSRAM containing 10

transistors were used with

stacking effect.

66% yield improvement is

achieved.

12 Etian N. Shauley

et.al[10]

2012 Two techniques were involved.

First technique was replacing

NMOS path with PMOS.

Second technique used dynamic

voltage scaling.

26%, 50% reduction in gate

current and 37%, 57% leakage

power reduction by first and

second techniques respectively.

13 Alireza Khorospur

et.al[19]

2011 Generalized extreme value

distribution in the presence of

process variation.

Maximum 99% percentile

points with average errors of

2.0% were obtained.

14 Archana Nagda

et.al[13]

2012 A Single circuit implementation

of various techniques done in

accordance to incur minimum

delay.

Significant reduction in leakage

power is obtained.

15 De Shiaun Chiou

et.al[10]

2010 Temporal correlation algorithm 25% size reduction as well as

good leakage power reduction.


10/29



1 Mihir chaudhary

et al[12]

2010 Dominant critical gating done by

ranking the gates in decreasing order.

Full chip optimization with 57%

and 32% improvement in time

yield.

2 Amit Agarwal et

al[30]

2005 Process tolerant architecture in cache

memory is used.

Yield is improved by 94%.

3 Xiang Lu et.al[29] 2004 Parametric delay evaluation based on

LUT and delay formulas.

Accuracy in path delay as

function of multiple interconnect

was obtained

4 Smruti R. Srangi

et al[7]

2008 VARIUS technique based on the

framework to model timing error

caused by process variation.

Accurate estimation of timing

error is obtained for pipeline

stages.

5 Shida Zhong et

al[20]

2011 Analysis of resistive bridge defect

delay behavior is done.

Improved the yield by more than

12% average with good timing

optimization to finish largest case.

ISSUE 2: Delay Optimization in VLSI Circuits


11/29

Strengths and Weaknesses

Strengths Modifying and using the conventional techniques like forced

stack techniques, lector techniques etc. on the single chip has

lead to the better optimization of power and delay.

Mostly techniques of power reduction used standard verification

tools like Cadence, SPICE for which provided efficientcomparative study between conventional techniques and

proposed one.

Techniques like state retention techniques can be utilized in any

situation which doesntdemand good voltage level.

Transistor stack techniques, sleep transistors are basic techniques

that were used in most of the researches to reduce the leakage

power reduction.



12/29

Strengths

Compensated circuit for input-output buffer works at hundreds

of MHz and also provided reduction to noise. Stacking Power Gating reduced leakage power as well as

ground bound noise.

MTCMOS, DTCMOS techniques emerged use of multi Vthas

an effective and easiest way to reduce the power dissipation

with easy implementation.

In nano technologies, process tolerant cache architecture

provides the advantage to handle large number of fault without

reducing the cache size.

Dual Gating achieves 86% of short circuit power and 99% ofleakage power reduction.



13/29

Weaknesses

All the proposed leakage reduction techniques like MTCMOS,

leakage monitoring circuit etc. lead to the trade-off betweenarea and delay.

Techniques like MTCMOS had suffered from the fabrication

complexity problem.

In case of worst delay, leakage reduction techniques like DIL

and DTCMOS exhibits great increase in power dissipation and

area with loss of efficiency.

While maintaining the clock frequency distribution in WID

(With in Die), adaptive body bias lead to increase in leakage

power. Clock frequency had increased by using the CMOSleakage reduction techniques but it lost the objective of slowing

down the power for 65nm technology.

Delay evaluation technique involved the implementation

complexity6/6/2014 Yield Optimization In VLSI Circuits 13


14/29

Problem Statement & Objectives

To optimize the yield in the circuit after the

technology mapping phase.

without increase in leakage power

Without increase in delay



15/29

Design Specifications


CMOSinverter with

Low Vth

CMOS inverterwith Power

gating

Generate net list Generate net list

Save net list in .sp and library file in

.pm extension

Save net list in .sp and library file in

.pm extension

Simulate by H-Spice Simulate by H-Spice

A B


16/29


A B

Analyze result with .lis file and view

the waveform in CosmosScope

Analyze result with .lis file and view

the waveform in CosmosScope

Compare result for average power with waveform in

CosmosScope

OptimizedCMOS inverter

Fig. 2 : Architectural Design Flow


17/29

Proposed Technique


Power Gating Technique

Switch the power OFF to the FU when not needed

Achieved by using a suitably sized header or footer transistor

Popular technique to reduce FU power

Fig 3: Power Gating Technique


18/29

Hardware and Software


Hardware

o CMOS inverter

Software's Used

H-Spice

CosmoScope

S-Edit

Fig 4 : Basic CMOS Inverter


19/29

Experimentations Carried out & Results

Objectives To understand the power gating technique.

To study the different type of methodology in power

gating used by the researcher. To study various type of variations in power gating.

To simulate the VLSI circuits in the HSPICE.

The final objective selected for experiment isTo optimize the yield of the CMOS inverter with

Power Gating technique using H-SPICE.



20/29


Experimental Results

Power dissipation without using Power Gating

o Average power= 8.3680E-10

Power Dissipation using Power Gating

o Average power =2.6921E-13


21/29


Simulation Graph 1 : Power Characteristic of

CMOS Inverter without using Power Gating


22/29


Simulation Graph 2: Power Characteristic of

CMOS Inverter using Power Gating


23/29

Conclusion

Technology scaling has given rise to increase in

power consumption and delay of the digital integrated

circuits.

Power Gating is an effective technique to reduce theleakage power of the CMOS technology scaled

circuits.

Yield optimization has been achieved with significant

leakage reduction .



24/29

References[1] Jatin Nawnit Mistry Leakage power minimization technique for embedded

processorsPh.D dissertation,2013, University of Southampton

[2] K.R.N. Karthik, M. Nagesh Babu, V. Narsimha Nayak, S. RajeshwariCadenceDesign

of Leakage Power Reduction Circuit in CMOS VLSI Design,2013, IJERA

[3] Mrs. Sonika, Mr. Anshuman Singh Adaptive body biasing process compensation

techniques for Digital circuit,2013IJERA

[4] Ruchika Mittal, Sarita Bajaj LeakagePower Reduction in CMOS,2013, IJERA

[5] Gyan parkash, Umesh Dutta, Mohd. Tauheed Khan Dynamic Power Reduction InSram / International Journal of Engineering Research and Applications (IJERA)

ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.1781-

1784

[6] Kumar Yelamarthi Timing-Driven Variation-Aware Partitioning and Optimization of

Mixed Static-Dynamic CMOS Circuits2012, circuits and systems[7] Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari,

and Josep Torrellas VARIUS: A Model of Process Variation and Resulting Timing

Errors for Microarchitects,2012, IJCA



25/29

[8] Rashmi Bahal, Shyam Akashe Modelingand Estimation of Total Leakage Current

in Nano-scaled 7T SRAM Cell Considering the Effect of Parameter Variation2012,

IJERA

[9] M. Madhavi Latha, A. Sai Ramesh, V. Leela Rani Galeorstack- A NovelLeakage Reduction Technique for Low Power VLSI Design,2012, IJCA

[10] Etian N. Shauley CMOS Leakage and Power Reduction in Transistors and

Circuits. 2012, JLPEA

[11] Rajani H.P, .Shriman Narayan Kulkarni LPSR: Novel Low Power State Retention

Technique for CMOS VLSI Design2012, IEEE[12] Mihir choudhary, Masoud Rostami, and Kartik Mohanra DominantCritical Gate

Identification for Power and Yield Optimization in Logic Cicuits,2012,IJCA

[13] Archana Nagda Rajendra Prasad, N. K. Vyas Leakage Power Reduction

Techniques: A New Approach,2012, IJERA

[14] M. Geetha Priya, K. Baskaran ANew Leakage Power Reduction Technique for

CMOS VLSI Circuits2012.EJCA

[15] M. Janaki Rani, S. Malarkann Leakage power reduction and analysis of cmos

sequential circuitsVol. 3 No.1, 2012, VLSICS

[16] Hai Zhou, L. He. FastBuffer Insertion for Yield Optimization Under Process

Variations Scalable to 20 nm,2012, IEEE



26/29

[17] Hailong Jiao NoiseMitigation in MTCMOS circuits,Ph.D. dissertation, 2012,The Hong Kong University of Science and Technology

[18] Dr. K. Srinivasa Rao, B, Ramparamesh, Dr, V, Maleshwara Rao Reduction ofPower Dissipation in Logic Circuits,2011, IJCA

[19] Alireza Khosropour, Ali Afzali-Kusha, Massoud Pedram, Hossein AghababaStatistical estimation of leakage power dissipation in nano-scale complementarymetal oxide semiconductor digital circuits using generalized extreme valuedistribution. 2011,IET Circuits, Devices & Systems

[20] Shida Zhong, Saquib Khursheed, Sudhakar M. Reddy, Krishnedu Chakrabarty AFast and Accurate Process Variation-Aware Modeling Technique for ResistiveBridge Defects2011, IEEE

[21] Raghuvir Singh, B. K. Kaushik, K. G. Verma, Brijesh KumarEffect of LineParasitic Variations on Propagation Delay in Global VLSI Interconnects 2011,IJCA

[22] Golshan S, Homayoun, H., S. Bozorgzadeh, E. Videnbaum Post-Synthesis SleepTransistor Insertion for Leakage Power Optimization in Clock Tree Networks,2010, IEEE

[22]Yi-Ling Liu, Chun-Yao Wang ANovel ACO-based Pattern Generation for PeakPower Estimation in VLSI Circuits2009IEEE

[24] S. Mohanty, Bijaya K. Panigarhi ILPBased Leakage Optimization During Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS Perspective,2009, IEEE

[25] De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, and Shih-Chieh Chang SleepTransistor Sizing for Leakage Power Minimization Considering ChargeBalancing,2009, IEEE



27/29

[26] Yi Ling Liu, Chun Yao Wang, Yung Chih Chen, Ya Hsin Chang Anovel ACO-based pattern generation for peak power estimation in VLSI circuits,2009, IEEE

[27] Erik Anderson, Wen Chin Lee, Hideki Takeuchi, Kazuya Asano, Charles Kuo,

Digh Hisamoto FinFETA Self-Aligned Double-Gate MOSFET,2007, IEEE[28] Harmander Singh, Member, IEEE, Kanak Agarwal, Member, IEEE, DennisSylvester, Senior Member, IEEE, and Kevin J. Nowka, Senior Member, IEEEEnhanced Leakage Reduction Techniques Using Intermediate Strength PowerGating,2007, IEEE

[29] Xiaiyo Lang, David Brooks Mitigating the Impact of Process Variations onProcessor Register Files and Execution Units2006, IEEE

[30] Amit Agarwal, Vipul C. Paul, Hamid Mahmoodi, Animesh Dutta, Kaushik RoyA Process-Tolerant Cache Architecture for ImprovedYield in NanoscaleTechnologies2005, IEEE

[31] S. Borkar T. Karnik Design and reliability challenges in nanometertechnologies,2004, IEEE

[32] Hyunsik, Im, Inukai, T., Gomoyo, H., Hiramoto, T. VTCMOSCharacteristics andIts Optimum Conditions Predicted By a Compact Analytical Model, 2003, IEEE

[33] Jason H. Anderson, Jason H. Anderson Power Estimation Techniques forFPGAs,2004,IEEE

[34] Toshiro Hiramoto, Makoto Takamiya Optimum Device Parameters andScalability of Variable Threshold Voltage Complementary MOS (VTCMOS),2001, JJAP



28/29

[35] Wen-Tsong Shiiie Leakage Power Estimation And Minimization In VLSI

Circuits2001 IEEE

[36] Michael B. Henry EmergingGating Technique for Low Power Digital Cicuits.

Ph.D dissertation, Virginia Polytechnic Institute and State University

[37] Luca Benini, Alberto Macii, Enrico Macii Multiple Power-Gating Domain

(Multi-VGND) Architecture For Improved Leakage Power Reduction2000, IEEE

[38] Junzo Yamada 1 -V Power Supply High-speed Digital Circuit Technology with

Multi threshold Voltage CMOS,1995, IEEE

[39] Mahadevamurty Nemani, Farid N. Najm High-Level Area and Power Estimationfor VLSI Circuits1999IEEE

[40] Macii E, Liu D. Power consumption of static and dynamic CMOS circuits: A

comparative study,1996, IEEE



29/29


yield optimization using power gating

Documents

Transcript of yield optimization using power gating