cellular automata as a test pattern generator and output response compactor for bist
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Transcript of XTP041: SP601 Built-In Self Test Flash Application BIST (Built-In Self Test) ... SP601 BIST Second...
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© Copyright 2012 Xilinx
SP601 Built-In Self Test Flash Application
March 2012
XTP041
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© Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the “Information”) is provided “AS-IS” with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
Revision History
Date Version Description 03/16/12 13.4 Up-rev 13.3 BIST Design to 13.4.
10/26/11 13.3 Up-rev 13.2 BIST Design to 13.3.
07/06/11 13.2 Up-rev 13.1 BIST Design to 13.2.
03/01/11 13.1 Up-rev 12.4 BIST Design to 13.1.
12/21/10 12.4 Up-rev 12.3 BIST Design to 12.4. Change to SDK Software flow.
10/05/10 12.3 Up-rev 12.2 BIST Design to 12.3.
07/23/10 12.2 Up-rev 12.1 BIST Design to 12.2. Set RZQ and ZIO pins in MPMC core GUI. See MPMC 6.01.a Product Specification for more details. Added AR36291 – MCB Data errors on initial programming of FPGA Updated SI Labs USB UART Drivers URL
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Overview
Xilinx SP601 Board Software Requirements SP601 Setup SP601 BIST (Built-In Self Test) Compile SP601 BIST Design Program SP601 with BIST Design Program SP601 BPI References
Note: This presentation applies to the SP601
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SP601 BIST Design Description
Description – The Built-In System Test (BIST) application uses an EDK MicroBlaze system
to verify board functionality. A UART based terminal program interface offers users a menu of tests to run.
Reference Design IP – EDK IP: MicroBlaze, plb_v46, lmb_v10, mdm, lmb_bram_if_cntlr,
bram_block, xps_bram_if_cntlr, xps_uart16550, xps_gpio, clock_generator, mpmc, proc_sys_reset, xps_intc, xps_timer, xps_iic, xps_mch_emc, xps_spi, util_io_mux, util_bus_split, xps_ethernetlite • Embedded System Tools Reference Guide (UG111) • http://www.xilinx.com/ise/embedded/edk_ip.htm
Reference Design Source – rdf0045.zip – Available through http://www.xilinx.com/sp601
Note: Presentation applies to the SP601
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Embedded Processor Design
The provided embedded reference design is supported “as is” – Please refer to the click through license agreement
Embedded reference design has been verified on the SP601 Evaluation Kit – Design consists of Early Access IP – Design may change in subsequent releases
The reference design will allow users to: – Re-build and verify functionality on the SP601 evaluation kit
Note: Presentation applies to the SP601
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Xilinx SP601 Board
Note: Presentation applies to the SP601
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SP601 MicroBlaze Hardware
The SP601 MicroBlaze design hardware includes: – DDR2 Interface (128 MB) – BRAM – External Memory Controller (EMC)
• Flash Memory
– Networking – UART – Interrupt Controller – GPIO (IIC, LEDs and LCD) – Timer – SPI – PLB v46 Bus
Note: Presentation applies to the SP601
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ISE Software Requirement
Xilinx ISE 13.4 software
Note: Presentation applies to the SP601
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EDK Software Requirement
Xilinx EDK 13.4 software
Note: Presentation applies to the SP601
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EDK Software Requirement
Xilinx SDK 13.4 software
Note: Presentation applies to the SP601
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SP601 Setup
Connect a USB Mini-B Cable to the USB UART connector on the SP601 board
– Connect this cable to your PC
Power on the SP601 board for UART Driver Install
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SP601 Setup
Install USB UART Drivers – CP210x_VCP_Win_XP_S2K3_Vista_7.exe
Note: Presentation applies to the SP601
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SP601 Setup
Reboot your PC if necessary Right-click on My Computer
and select Properties – Select the Hardware tab – Click on Device Manager
Note: Presentation applies to the SP601
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SP601 Setup
Expand the Ports Hardware – Right-click on Silicon Labs
CP210x USB to UART Bridge and select Properties
Note: Presentation applies to the SP601
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SP601 Setup
Under Port Settings tab – Click Advanced – Set the COM Port to an open Com
Port setting from COM1 to COM4
Note: Presentation applies to the SP601
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SP601 Setup
Board Power must be on before starting Tera Term Start the Terminal Program
– Select your USB Com Port – Set the baud to 9600
Note: Tera Term may need to be restarted if board power is cycled
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SP601 Setup
Set the mode pins for BPI Flash
– M0 = 0 – M1 = 0
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SP601 BIST
Press PROG and view initial BIST screen – Type “1” to start the UART Test
Note: As per AR36291, hold the PROG button for a extra second or two if seeing errors
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SP601 BIST
UART Test completed – Press PROG and type 2 to begin LED Test
Note: Presentation applies to the SP601
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SP601 BIST
LED Test completed – Press PROG and type 3 to begin Timer Test
Note: Presentation applies to the SP601
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SP601 BIST
Timer Test completed – Press PROG and type 4 to begin Flash test
Note: Do not press PROG until this test completes
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SP601 BIST
Flash Test completed – Press PROG and type 5 to begin IIC EEPROM Test
Note: Presentation applies to the SP601
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SP601 BIST
IIC EEPROM Test completed – Press PROG and type 6 to begin Ethernetlite Test
Note: Presentation applies to the SP601
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SP601 BIST
Ethernetlite Test completed – Press PROG and type 7 to begin GPIO Switch Test
Note: Presentation applies to the SP601
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SP601 BIST
GPIO Switch Test completed – Press PROG and type 8 to begin External Memory Test
Note: Presentation applies to the SP601
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SP601 BIST
External Memory Test running with caches on
Note: Presentation applies to the SP601
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SP601 BIST
Second part of External Memory test (caches off)
Note: Presentation applies to the SP601
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Compile SP601 BIST Design
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Compile SP601 BIST Design
Unzip the rdf0045.zip file – Available through http://www.xilinx.com/sp601 – Includes AR32713 – Recommended constraints for the XPS_LL_TEMAC
systems
Note: Presentation applies to the SP601
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Compile SP601 BIST Design
If desired, FPGA compile can be skipped by opening SDK directly: Start → All Programs → Xilinx ISE Design Suite 13.4 → EDK → Xilinx Software Development Kit
Select the workspace: <design files>\SDK\SDK_Workspace_35 Go to SDK Software Compile
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Compile SP601 BIST Design
Open XPS project <project directory>\ system.xmp
Create the hardware design, system.bit, located in <project directory> /implementation – Click the Generate
Bitstream button (1) – Or from the menu,
select Hardware → Generate Bitstream
Note: Presentation applies to the SP601
1
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Compile SP601 BIST Design
Open SDK – Click the Export
Design button (1) – Click Export & Launch
SDK (2)
2 Note: Presentation applies to the SP601
1
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Compile SP601 BIST Design
SDK Software Compile – Build ELF files in SDK – Select Project → Build All (1) – Note: If by-passing the FPGA compile, the ELF files are already built; if
desired, the ELF files can be re-built by selecting Clean… followed by Build All
1
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Program SP601 with BIST Design
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Program SP601 with BIST Design
Add a second USB Type-A to Mini-B cable to the USB JTAG connector on the SP601 board
– Connect this cable to your PC
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Program SP601 with BIST Design
Init memory with the Bootloop ELF – Update the bitstream (download.bit) with the Bootloop ELF – Select Xilinx Tools → Program FPGA (1)
1
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Program SP601 with BIST Design
Init memory with the Bootloader Application ELF – Select bootloop (1) – Click Program
1
Note: Verify the Bitstream and BMM File paths match your design path
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Program SP601 with BIST Design
Launch XMD – Select Xilinx Tools → XMD Console (1)
1
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Program SP601 with BIST Design
Connect XMD to the MicroBlaze: cd C:/sp601_bist/SDK/SDK_Workspace_35 connect mb mdm
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Program SP601 with BIST Design
Download the bootloader with xmd: dow bootloader/Debug/bootloader.elf
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Program SP601 with BIST Design
Download the bootloader with xmd: con
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Program SP601 with BIST Design
Bootloader runs in the terminal window
Note: Presentation applies to the SP601
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Program SP601 with BIST Design
Init memory with the Bootloader ELF – Update the bitstream (download.bit) with the Bootloader ELF – Select Xilinx Tools → Program FPGA (1)
1
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Program SP601 with BIST Design
Init memory with the Bootloader Application ELF – Select <Design Files>\SDK\SDK_Workspace_35
\bootloader\Debug\bootloader.elf (1) – Click Program
Note: Always reselect the desired ELF file at this step
1
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Program SP601 with BIST Design
Bootloader runs in the terminal window
Note: Presentation applies to the SP601
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Program SP601 BPI
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Program SP601 BPI
The bitstream must be converted to hex format (.bin) prior to programming into flash – Select Xilinx Tools → Launch Shell (1)
1
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Program SP601 BPI
Generate a BIN file from the bitstream promgen -w -p bin -c FF -o hw_platform_0/download.bin -u 0 hw_platform_0/download.bit
Note: Presentation applies to the SP601
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Program SP601 BPI
Program the bitstream and ELF files into BPI Flash – Select Xilinx Tools → Program Flash Memory (1) – FPGA must contain the BIST bitstream at this point
1
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Program SP601 BPI
Program the BPI Flash with the bitstream bin file – Bitstream hw_platform_0/
download.bin – Offset: 0x00000000 – Working Memory:
DDR2_SDRAM
Note: Click Program after the data is entered
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Program SP601 BPI
Program the BPI Flash with an SREC file: – ELF: hello_uart/
Debug/hello_uart.elf – Select Auto-convert to SREC – Offset: 0x00120000 – Working Memory:
DDR2_SDRAM
Note: Presentation applies to the SP601
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Program SP601 BPI
Program the BPI Flash with an SREC file: – ELF: hello_gpio/
Debug/hello_gpio.elf – Select Auto-convert to SREC – Offset: 0x00140000 – Working Memory:
DDR2_SDRAM
Note: Presentation applies to the SP601
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Program SP601 BPI
Program the BPI Flash with an SREC file: – ELF: hello_timer/
Debug/hello_timer.elf – Select Auto-convert to SREC – Offset: 0x00160000 – Working Memory:
DDR2_SDRAM
Note: Presentation applies to the SP601
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Program SP601 BPI
Program the BPI Flash with an SREC file: – ELF: hello_flash/
Debug/hello_flash.elf – Select Auto-convert to SREC – Offset: 0x00180000 – Working Memory:
DDR2_SDRAM
Note: Presentation applies to the SP601
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Program SP601 BPI
Program the BPI Flash with an SREC file: – ELF: hello_iic/
Debug/hello_iic.elf – Select Auto-convert to SREC – Offset: 0x001a0000 – Working Memory:
DDR2_SDRAM
Note: Presentation applies to the SP601
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Program SP601 BPI
Program the BPI Flash with an SREC file: – ELF: hello_emac/
Debug/hello_emac.elf – Select Auto-convert to SREC – Offset: 0x001c0000 – Working Memory:
DDR2_SDRAM
Note: Presentation applies to the SP601
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Program SP601 BPI
Program the BPI Flash with an SREC file: – ELF: hello_switch/
Debug/hello_switch.elf – Select Auto-convert to SREC – Offset: 0x001e0000 – Working Memory:
DDR2_SDRAM
Note: Presentation applies to the SP601
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Program SP601 BPI
Program the BPI Flash with an SREC file: – ELF: hello_mem/
Debug/hello_mem.elf – Select Auto-convert to SREC – Offset: 0x00200000 – Working Memory:
DDR2_SDRAM
Note: Presentation applies to the SP601
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Program SP601 BPI
Press PROG and view initial BIST screen – Type “1” to start the UART Test
Note: Presentation applies to the SP601
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References
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References
EDK Documentation – Embedded System Tools Reference Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/est_rm.pdf
Spartan-6 Configuration – Spartan-6 FPGA Configuration User Guide
http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
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Documentation
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Documentation
Spartan-6 – Spartan-6 FPGA Family
http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/index.htm
SP601 Documentation – Spartan-6 FPGA SP601 Evaluation Kit
http://www.xilinx.com/products/boards-and-kits/EK-S6-SP601-G.htm – SP601 Getting Started Guide
http://www.xilinx.com/support/documentation/boards_and_kits/ug523.pdf – SP601 Hardware User Guide
http://www.xilinx.com/support/documentation/boards_and_kits/ug518.pdf – SP601 Reference Design User Guide
http://www.xilinx.com/support/documentation/boards_and_kits/ug524.pdf