Flat ½, 79 Raeberry Street Glasgow G20 6EQ, Scotland U.K.

+44 (0)7897002079, xingsheng.wang@gmail.com http://userweb.eng.gla.ac.uk/xingsheng.wang/

Education University of Glasgow (UK), 2006-2010 (Supervisor: Prof. Asen Asenov, Prof. Scott Roy)

Ph.D. in Electronics and Electrical Engineering, fully supported by ORSAS and EPSRC grant. Tsinghua University (China), 2004-2006 (Advisor: Prof. Jiaxin Hu)

MPhil in Mathematics, with the first prize. Best Master Thesis. Beijing Technology and Business University (China), 2000-2004

B.S. in Electronic Science and Technology, with the first prize. Best Bachelor Thesis. Work

Research Associate, University of Glasgow 08.2012-present Electronic and Nanoscale Engineering.

Research Assistant, University of Glasgow 03.2010-07.2012 Electronic and Nanoscale Engineering.

Teaching Assistant, Tsinghua University (part-time) 2005-2006 Higher Mathematics.

Research Experience l (2012 – present) Scottish Funding Council Project “Statistical Design and Verification of Analogue System

(StatDes).” (Project industrial partners: IBM, Wolfson, GSS, Dialog, and others) Research Associate, supervised by Prof. Asen Asenov Path finding for 14nm CMOS technology and Device/SRAM co-optimization. SOI DG FinFETs, Device and SRAM co-optimization/co-design, Process Corners and statistical variability and reliability. Interplay of long-range process variation and short-range statistical variability. The comprehensive simulations are carried out in CD process variation space. The strong dependence of statistical variability on finFET CD variation is found. Novel unified compact modelling strategies for process and statistical variability in FinFETs. The novel PCA based and nonlinear power method based compact model strategies are developed to accurately represent both long range and local variations.

l (2012 – 2012) EPSRC Platform Grant “Atomistic Scale Simulation of Nanoelectronic Devices.” Research Associate, supervised by Prof. Asen Asenov Extend the simulation scale and the knowledge for advanced FETs and memories in terms of variability. ( http://web.eng.gla.ac.uk/groups/devmod/index.php/research/atomistic/ )

l (2010.9 – 2012.9) EU ENIAC joint undertaking project “MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems (MODERN).” (Project industrial partners: STMicroelectronics, IMEC, and others) (supervised by Prof. Asen Asenov) Statistical Variability in 32/28nm CMOS technology. Responsible for simulation calibration of 32nm CMOS technology shipped from STMicroelectronics, and comprehensive full-scale 3D statistical simulation study including the major variability sources RDD, LER and MGG. Device Design and Statistical Variability in 22nm 3D transistor FinFET technology. Responsible for designing 22nm FinFET technology, and comprehensive full-scale 3D statistical simulation study including the major variability sources RDD, LER and MGG. Statistical Compact Modelling for 32/28nm and 22nm CMOS technologies. Responsible for shipping the uniform compact models of 32nm and 22nm CMOS technology, and statistical compact modelling for TCAD-based PDK methodology.

l (2010.3 – 2010.9) European FP7 project “Terascale Reliable Adaptive Memory Systems (TRAMS).” (Project industrial partners: Intel, IMEC) Postdoctoral research assistant, supervised by Prof. Asen Asenov Statistical Variability in 13nm gate-length CMOS technology. Responsible for simulation calibration of 13nm gate-length CMOS technology designed in Device Modelling Group at University of Glasgow, and comprehensive full-scale 3D statistical simulation study including the major variability sources RDD, LER and MGG. Work reported.

l (2006.10 – 2010.2) UK EPSRC project “Meeting the design challenges of nano-CMOS Electronics

Xingsheng Wang

(nanoCMOS)” (Project partners: ARM, Synopsys, Wolfson, Freescale, et al.) PhD student, supervised by Prof. Asen Asenov, Prof. Scott Roy. CMOS device scaling study based on state-of-the-art bulk 45nm technology generation. Responsible for this part, four generations of conventional n/p-channel MOSFETs are developed using Sentaurus process simulator and performance parameters and electrical characteristics are obtained by Sentaurus Device. Statistical variability sourced from random discrete dopants (RDD), line edge roughness (LER) and grain poly-silicon Fermi pinning for scaled devices. Predictive statistical variability of parameters such as threshold voltage in developed MOSFETs is obtained in a cooperation ‘atomistic’ team. Involved in discussion and simulations, and partially charge for characterizing obtained electrical characteristics data. Optimal application and modelling of stress engineering, and simulation study of strain variability. Strain application since 90nm node has enhanced carrier mobility. Tensile contact etch stop layer (CESL) for nMOS and compressive CESL and eSiGe source/drain for pMOS are implemented to introduce corresponding channel stress. Optimum design is achieved among stressor geometry, space and short-channel effects. Due to the sensitivity to geometry variation, channel strain variability induced by gate LER is characterized for the first time, and its impact on device performance is statistically obtained. Enhanced variability and reliability issue related with shallow trench isolation (STI) in narrow-channel MOSFETs. For the first time width effect of statistical variability in the presence of the STI structure is examined. Inverse narrow channel effect is examined, and the impact of possible channel junction shapes is also considered. The statistical variability and reliability in the presence of the STI structure is enhanced although it also depends on junction shape. Small signal analysis of deep decananometer MOSFETs, and physical simulation and understanding of transient behaviour in basic circuits. The capacitances of developed MOSFETs are examined using rigorous S3A method. Intrinsic and extrinsic parts are separated. Parasitics are drastically weakening performance. Compact representation based physical simulation of inverter behaviour is given. Improved the understanding and achieved better characterization accuracy of inverter transfer characteristics.

l (2004.9 – 2006.9) Applied Mathematics, in Tsinghua University Research Master student, advised by Prof. Jiaxin Hu Fractal geometry and Laplacian related partial differential equations. Gave the estimates of a metric in one class of fractals and characterized the domain of an operator on a kind of fractals. Several theorems are proved.

l (2003.9 – 2004.6) Electronic Science and Technology, in Beijing Technology and Business University Senior undergraduate student Signal processing and direct sequence spread spectrum communication system. A direct spread spectrum communication system employing adaptive filters based on LMS is simulated using the MATLAB programs written specially.

Knowledge & Tools (selected) l Advanced transistors (bulk, FDSOI, FinFET), device physics, variability & reliability l Numerical device simulation (drift-diffusion, Monte Carlo), compact modelling, circuit simulation l MOSFET process, PDK l Memory cell (SRAM, DRAM), basic digital/analogue circuit cells l Sentaurus suite, Taurus, GSS Garand, SPICE l Bash, Tcl, Python, Matlab, R, Office, MacOS/Linux/Windows

Teaching Experience l (2010 – 2013) Assisting supervision of a PhD student in University of Glasgow

Thesis on fully-depleted silicon on insulator transistor design and statistical variability l (2008) Undergraduate course “Digital circuits” in University of Glasgow

Lab Demonstrator l (2005 – 2006) Undergraduate course “Higher mathematics 1 & 2” in Tsinghua University

Teaching assistant, tutorials/homework and exam assessments of calculus and algebra.

Reports on research results • “IEDM 2011 Preview”, Solid State Technology, 29/11/2011 • “IEDM 11: THE SOI PAPERS”, www.advancedsubstratenews.com, 7/2/2012 • “SOI FinFETs for 11nm CMOS”, Computer Scotland, 5/12/2011 • “Fins on transistors change processor power and performance”, IBM Research, 27/7/2012

Academic Affiliation and Service • (2011.9 – present) IEEE Member, IEEE Electron Device Society Member • (2008 – present) Reviewer of Solid-State Electronics • (2009 – present) Reviewer of IEEE Transactions on Electron Devices • (2012 – present) Reviewer of Microelectronic Engineering • (2012 – 2013) Expert Reviewer of 50th Design Automation Conference (DAC), 2013 • (2012 – present) Reviewer of IEEE Electron Device Letters

Awards and Scholarship • Overseas research students awards scheme (ORSAS) 2007, Secretary of State for Education and Science, U.K.

(In total only approximate 900 recipients in U.K. per year) • EPSRC studentship 2006, Engineering and Physical Science Research Council, U.K. • Tsinghua University Excellent Master Postgraduate 2007, Tsinghua University, 2007 (< 2% acceptance) • Tsinghua University Best Master Thesis 2007, Tsinghua University • Tsinghua University ‘Guanghua’ scholarship 2005, Tsinghua University. • Beijing Outstanding Graduate 2004, Beijing Municipal Education Commission (< 0.1% acceptance) • BTBU Best Bachelor Thesis 2004, Beijing Technology and Business University (3% acceptance) • China National Scholarship 2002, First-class, Ministry of Education, China (<0.25% acceptance)

Selected Publications Google Scholar Citations: h-index 7. http://scholar.google.com/citations?user=yx5kv74AAAAJ&hl=en Full publication list: http://userweb.eng.gla.ac.uk/xingsheng.wang/research.php Book Chapters

1. A. Asenov, B. Cheng, A.R. Brown, and X. Wang, “Impact of Statistical Variability on FinFET Technology: From Device, Statistical Compact Modelling to Statistical Circuit Simulation,” Nyquist AD Converters, Sensor Interfaces, and Robustness: Advances in Analog Circuit Design, 2012, edited by Arthur H. M. van Roermund, Andrea Baschirotto, and Michiel Steyaert, New York: Springer, 2012. Chapter 15. pp.281-291.

Refereed Journal Papers

1. X. Wang, A.R. Brown, B. Cheng, S. Roy, and A. Asenov, “Drain Bias Effects on Statistical Variability and Reliability and Related Subthreshold Variability in 20-nm Bulk Planar MOSFETs,” Solid-State Electronics. (Invited Submission)

2. X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, “Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS technology Double-Gate SOI FinFETs,” IEEE Transactions on Electron Devices, Vol.60 No.8, pp.2485-2492, August 2013.

3. B. Cheng, X. Wang, A.R. Brown, C. Millar, C. Alexander, J.B. Kuang, S. Nassif, A. Asenov, “DG FinFET Robustness to Process Variability and its Representation in BSIM-CMG,” submitted to IEEE Transactions on Electron Devices.

4. X. Wang, B. Cheng, A.R. Brown, C. Millar, J.B. Kuang, S. Nassif, A. Asenov, “Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm node SOI FinFET Technology,” IEEE Design and Test of Computers, 2013. Accepted. (Invited Paper)

5. X. Wang, F. Adamu-Lema, B. Cheng, and A. Asenov, “Geometry, Temperature and Body Bias Dependence of Statistical Variability of 22-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis,” IEEE Transactions on Electron Devices, Vol.60 No.5, pp.1547-1554, May 2013.

6. X. Wang, G. Roy, O. Saxod, A. Bajolet, A. Juge, and A. Asenov, “Simulation Study of Dominant Statistical Variability Sources in 32-nm High-k/Metal Gate CMOS,” IEEE Electron Device Letters, Vol.33, No.5, May 2012, pp.643-645.

7. K. Abid, X. Wang, A.Z. Khokhar, S. Watson, S. Al-Hasani, F. Rahman, “Electrically tuneable spectral responsivity in gated silicon photodiodes,” Appl. Phys. Lett.,Vol. 99 No.23, 231104, 2011.

8. B. Benbakhti, K. Chan, E. Towie, K. Kalna, C. Riddet, X. Wang, G. Eneman, G. Hellings, K. De Meyer, M. Meuris and A. Asenov, "Numerical analysis of the new Implant-Free Quantum-Well CMOS: DualLogic approach," Solid-State Electronics, Vol. 63, No. 1, pp. 14–18, 2011.

9. X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy and A. Asenov, "Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study," IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2293–2301, Aug. 2011. (Cover   Story   in   the  special  issue  “Characterization  of  Nano  CMOS  Variability  by  Simulation  and  Measurements”)

10. S. Markov, X. Wang, N. Moezi, and A. Asenov, "Drain Current Collapse in Nanoscaled Bulk MOSFETs Due to Random Dopant Compensation in the Source/Drain Extensions," IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2385–2393, Aug. 2011.

11. X. Wang, S. Roy, A. R. Brown and A. Asenov, "Impact of STI on Statistical Variability and Reliability of Decananometer MOSFETs," IEEE Electron Device Letters, Vol. 32, No. 4, pp. 479–481, Apr. 2011.

12. B. Bindu, B. Cheng, G. Roy, X. Wang, S. Roy and A. Asenov, "Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction," Solid-State Electronics, Vol. 54, No. 3, pp. 307–315, Mar. 2010.

13. B. Cheng, D. Dideban, N. Moezi, C. Millar, G. Roy, X. Wang, S. Roy and A. Asenov, "Statistical Variability Compact Modeling Strategies for BSIM4 and PSP," IEEE Design and Test of Computers, Vol. 27, No. 2, pp. 26–35, Mar./Apr. 2010.

14. J. Hu, X. Wang, “Domains of Dirichlet forms and effective resistance estimates on p.c.f. fractal,” Studia Math., 177 (2006), 153-172. (Tsinghua University Best Master Degree Thesis)

15. X. Wang, Y. Chen, “Suppression Techniques against Narrow-Band Interference in DS/SS Communications System,” Computer Simulation, 23(1), 2006, 294-298. (Beijing Technology and Business University Best Bachelor Degree Thesis)

Refereed Conference Papers 1. X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, “Impact of Statistical

Variability and Charge Trapping on 14 nm SOI FinFET SRAM Cell Stability,” Accepted, 43rd European Solid-State Device Research Conference (ESSDERC 2013), Bucharest Romania, 16-20 September 2013. Oral.

2. X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, “Unified Compact Modelling Strategies for Process and Statistical Variability in 14-nm node DG FinFETs,” Accepted. 18th International conference on Simulation of Semiconductor Processes and Devices (SISPAD 2013), Glasgow UK, 3-5 September 2013. Oral.

3. B. Cheng, X. Wang, A. R. Brown, J. B. Kuang, D. Reid, C. Millar, S. Nassif and A. Asenov, "SRAM Device and Cell Co-Design Considerations in a 14nm SOI FinFET Technology," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing China, 19-23 May 2013, pp. 2339–2342. Oral.

4. X. Wang, A. R. Brown, B. Cheng, and A. Asenov, “Drain Bias Impact on Statistical Variability and Reliability in 20 nm Bulk CMOS Technology,” in Proc. 14th Conference on Ultimate Integration on Silicon (ULIS 2013), March 2013, pp.65-68. Oral.

5. X. Wang, B. Cheng, A.R. Brown, C. Millar, and A. Asenov, “Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design,” in Proc. 42nd European Solid-State Device Research Conference (ESSDERC 2012), Bordeaux France, 17-21 September 2012, pp.113-116. Oral.

6. B. Cheng, X. Wang, J.B. Kuang, A.R. Brown, C. Millar, S. Nassif, and A. Asenov, “Statistical TCAD based PDK development for a FinFET technology at 14nm technology node,” in Proc. 17th International conference on Simulation of Semiconductor Processes and Devices (SISPAD 2012), Denver CO USA, 5-7 September 2012, pp.113-116. Oral.

7. X. Wang, A.R. Brown, B. Cheng, and A. Asenov, “RTS amplitude distribution in 20nm SOI FinFETs subject to statistical variability,” in Proc. 17th International conference on Simulation of Semiconductor Processes and Devices (SISPAD 2012), Denver CO USA, 5-7 September 2012, pp.296-299. Oral.

8. B. Cheng, A.R. Brown, X. Wang, and A. Asenov, “Statistical variability study of a 10nm gate length SOI FinFET device," in Proc. IEEE Silicon Nanoelectronics Workshop (SNW 2012), Honolulu HI USA, June 10-11, 2012, pp. 69–70. Oral.

9. X. Wang, A.R. Brown, B. Cheng, and A. Asenov, “Statistical distribution of RTS amplitudes in 20nm SOI FinFETs," in Proc. IEEE Silicon Nanoelectronics Workshop (SNW 2012), Honolulu HI USA, June 10-11, 2012, pp. 77–78. Oral.

10. A. Asenov, B. Cheng, A.R. Brown, and X. Wang, “Impact of statistical variability on FinFET technology: from device statistical compact modelling to statistical circuit simulation,” in 21st Workshop on Advances in Analog Circuit Design (AACD 2012), March 2012. (Invited talk)

11. X. Wang, A. R. Brown, B. Cheng and A. Asenov, "Statistical Variability and Reliability in Nanoscale FinFETs," in Proc. IEEE International Electron Devices Meeting (IEDM 2011), Washington DC, Dec. 5-7, 2011, pp. 103–106. Oral.

12. X. Wang, S. Markov and A. Asenov, "Channel-length dependence of statistical threshold-voltage variability in extremely scaled HKMG MOSFETs," in Proc. 12th Ultimate Integration on Silicon (ULIS 2011), Cork, Ireland, Mar. 14-16, 2011, pp. 175–178. Oral.

13. B. Cheng, D. Dideban, N. Moezi, C. Millar, G. Roy, X. Wang, S. Roy and A. Asenov, "Capturing Intrinsic Parameter Fluctuations using the PSP Compact Model," in Proc. Design, Automation and Test in Europe (DATE 2010), Dresden, Germany, Mar. 8-12, 2010, pp. 650–653. Oral.

14. X. Wang, S. Roy and A. Asenov, "Impact of Strain on the Performance of high-k/metal replacement gate MOSFETs," in Proc. 10th Ultimate Integration on Silicon (ULIS 2009), Aachen Germany, Mar. 18-20, 2009, pp. 289–292. Poster.

15. A. Asenov, S. Roy, A. R. Brown, G. Roy, C. L. Alexander, C. Riddet, C. Millar, B. Cheng, A. Martinez, N. Seoane, D. Reid, M. Faiz. Bukhori, X. Wang and U. Kovac, "Advanced simulation of statistical variability and reliability in nano CMOS transistors," in Proc. IEEE International Electron Devices Meeting (IEDM 2008), USA, Dec. 2008, p. 421. (Invited talk)

16. X. Wang, S. Roy and A. Asenov, "High Performance MOSFET Scaling Study from Bulk 45 nm Technology Generation," in Proc. IEEE 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT 2008), Beijing China, Oct. 20-23, 2008, pp. 484–487. Oral.

17. X. Wang, S. Roy and A. Asenov, "Impact of Strain on LER Variability in bulk MOSFETs," in Proc. 38th European Solid-State Device Research Conference (ESSDERC 2008), Edinburgh Scotland U.K. Sept. 15-19, 2008, pp. 190–193. Oral.

18. X. Wang, B. Cheng, S. Roy and A. Asenov, "Simulation of Strain Enhanced Variability in nMOSFETs," in Proc. Ultimate Integration on Silicon (ULIS 2008), Udine Italy, Mar. 12-14, 2008, pp. 89–92. Oral.

References

1. Prof. Asen Asenov James Watt Chair in Electrical Engineering, School of Engineering, University of Glasgow Rankine Building, Oakfield Avenue, Glasgow G12 8LT, Scotland, U.K. ; CEO, Gold Standard Simulations Ltd., Rankine Building, Glasgow G12 8LT, U.K. Asen.Asenov@glasgow.ac.uk

2. Prof. Scott Roy Head of discipline division, School of Engineering, University of Glasgow Rankine Building, Oakfield Avenue, Glasgow G12 8LT, Scotland, U.K. Scott.Roy@glasgow.ac.uk

3. Dr. Sani Nassif Senior research staff member, Member of the IBM Academy of Technology IBM Austin Research Lab., IBM Research Division 11501 Burnet Road, Austin, TX 78758, USA. nassif@us.ibm.com , sani.nassif@gmail.com

4. Dr. Jente B. Kuang Research staff member, IBM Austin Research Lab., IBM Research Division 11501 Burnet Road, Austin, TX 78758, USA. kuang@us.ibm.com

5. Prof. Jiaxin Hu Department of mathematical sciences, Tsinghua University Beijing, 100084, P.R.China hujiaxin@mail.tsinghua.edu.cn

6. Dr. Binjie Cheng School of Engineering, University of Glasgow Rankine Building, Oakfield Avenue, Glasgow G12 8LT, Scotland, U.K. Binjie.Cheng@glasgow.ac.uk

7. Dr. Andre Juge Staff Engineer, STMicroelectronics 38920 Crolles, France. andre.juge@st.com

Fig. 3 in the paper: X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy and A. Asenov, "Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study," IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2293–2301, Aug. 2011.

The paper is selected on the cover in Special Issue on “Characterization of Nano CMOS Variability by Simulation and Measurements” of IEEE Transactions on Electron Devices (Vol.58 No.8).

The introduction is as follows: “About the Cover: Figure on the cover represents the electron density distribution in 35 nm device, simulated with random discrete dopants (RDD), line edge roughness (LER), and metal gate granularity (MGG) as sources of variability. The blue and red colors correspond to the electron densities of 105 cm-3 and 1020 cm-3, respectively. The different sources of variability result in several order of magnitudes electron concentration variation in the channel region. The surface indicates the potential landscape with the evidence of variability effects. The figure with more details appears in the paper by Wang et al. that begins on page 2293 of this Special Issue.”

Fig. 2 in the paper: X. Wang, A. R. Brown, B. Cheng and A. Asenov,

"Statistical Variability and Reliability in Nanoscale FinFETs," in Proc. IEEE International Electron Devices Meeting (IEDM 2011), Washington DC, Dec. 5-7, 2011, pp. 103–106.

The caption is “Full-scale 3D statistical simulations of FinFETs, showing the electron density in the fin and potential on the gate. It is easily seen that doping fluctuations, fin-edge and gate-edge roughness, and gate workfunction fluctuation are occurring in concert.”

It is the only paper with the lead author from U.K. in IEDM 2011.