Xilinx 4000 series
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Transcript of Xilinx 4000 series
Digital System Design And Testing
Xilinx 4000 Series FPGA
ME- Applied Electronics(PT)Department Of Electrical And Electronics Engineering
PSG College of Technology (Autonomous)Coimbatore
Xilinx General Architecture
CONFIGURABLEGLOBAL INTERCONNECTION
CONFIGURABLE INPUT/OUTPUTBLOCKS
CONFIGURABLE LOGICBLOCKS
Fixed array of Configurable Logic Blocks (CLBs) connectable by a system of pass transistors, driven by SRAM cells
Xilinx 4000 Architecture
*CLB: Configurable logic Blocks
*IOB: Input/output blocks
*Programmable interconnections
Xilinx 4000 Spec & FeaturesCLB:
2 FF per CLB + 2 per I/O cell25 gates per CLB for logic32 bits of SRAM per CLBSpecial fast carry logic between CLBs
Interconnects: Direct and general-purpose wires replaced with more efficient single-length and double-length lines.
Sufficient resources for most applications
Features:
Synchronous Single and Dual-Port RAM Internal Three-state buffers.System performance to 80 MHz0.5 µ SRAM Process Technology
Functional BlocksLogic blocks (CLB)
*configurable logic block, logic element, logic module, logic unit, logic array block, *to implement combinational and sequential logic
Interconnect
*wires to connect inputs and outputs to logic blocks
I/O blocks
*special logic blocks at periphery of device for external connections
Xilinx 4000 CLB
CLB-Configurable Logic Blocks
CLB - Configurable Logic Block* 5-input, 1 output function* 2 4-input, 1 output functions* optional register on outputs Built-in fast carry logicCan be used as memoryThree types of routing* direct* general-purpose* long lines of various lengthsRAM-programmable* can be reconfigured
CLB Function GeneratorsUse RAM for truth tables* F, G: 4 input -> 16 bits of RAM (each)* H: 3 input –> 8 bits of RAM* RAM is loaded at system initialization fromexternal PROM MUX control logic maps 4 control inputs into 4 inputs:* LUT input H1* Direct In (DIN)* Enable Clock (EC)* Set/Reset control (S/R) for FFs•Control F,G LUTs as 32 bit SRAMBroad capability:*Any 2 functions of 4 variables plus a function of 3 variables*Any function of 5 variables*Any function of 4 variables plus some functions of 6 variables*Some functions of 9 variables * Parity *4-bit case cadable equality checking
CLB input and output connections
Xilinx 4000 IOB
Xilinx 4000 IOBOutput: Combinational or registered; direct or inverted
Input: combinational. Or registered;zero holdtime option
Internal FFs for input & outputpathsFast/Slow outputs5 ns vs. 30 ns rise
Pull-up/downused withunused IOBs
Interconnections
//
GLOBAL INTERCONNECTION
PROGRAMMABLELOCAL INTERCONNECTIONS
CONFIGURABLE LOGIC BLOCKS
CONFIGURABLE INTERCONNECTION MATRIX
Xilinx 4000 interconnect
Xilinx 4000 Interconnections
3 types:
* Fast Direct Connections* General Purpose Connections with Switching Matrix*Horizontal/Vertical Long
Lines
Types of lines:* Single length (8)* Double length (4)* Long lines (6)* Global lines (4)
Methods Of Interconnections
Direct interconnect:Adjacent CLBs are wired together in the horizontal or vertical direction. The most efficient interconnect (< 1 ns delay)
General-purpose interconnect: used mainly for longer connections or for signals with a moderate fan-outFew, so problem in fitting a large design intoXC3000, and 2000
Long line interconnect: for time critical signals (e.g.clock signal need be distributed to many CLBs
Direct Connections
*Between neighboring locks
*From CLB to CLB
*From CLB to IOB
*Fastest, short distance connections
*X: Horizontal Connection
* Y: Vertical connection
Switch Matrix
Interconnection Details
Detail view of inside wiring
Xilinx 4000 Series Products
Applications Of FPGAImplementation of random logic*easier changes at system-level (one device is modified)* can eliminate need for full-custom chipsPrototyping* ensemble of gate arrays used to emulate a circuit to be manufactured* get more/better/faster debugging done than possible with simulationReconfigurable hardware* one hardware block used to implement more than one function*functions must be mutually-exclusive in time* can greatly reduce cost while enhancing flexibility* RAM-based only optionSpecial-purpose computation engines* hardware dedicated to solving one problem (or class of problems)*accelerators attached to general-purpose computers
FPGA Advantages
*Faster than CPU solution*Lower power than CPU solution (usually)*Low NRE costs*Off-the-shelf part designed by FPGA vendor*You are sharing NRE costs with all other customers*Fast design time*Low time-to-market*Fast re-design / re-fabrication time*Easy to correct an error, to add functionality, in response to spec change*Can even change product after deployment*Good for low to middle volume applications
FPGA Disadvantage
*High per-part costs*High volume applications should consider ASICs*Perhaps use FPGA for prototyping*Lower performance than ASIC*Higher power than ASIC*More specialized design skills than CPU
Thank you