x86-session09.ppt

X86 Session_0980286 & 80386

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80286The needs of multitasking/multiuser OS environment preservation during task switchesOS and user protectionvirtual memory management80286 was the first 8086 family member designed to make these implementations


80286-ArchitectureThe Bus UnitPerforms all memory and I/O reads and writes,prefetches instruction bytes and controls math processorThe instruction Unitfully decodes up to three instructions and holds them in a queueThe Execution Unit16 bit ALU,16 bit machine status wordThe Address Unitcomputes the physical addresses


Modes of OperationReal address modeAddress unit computes the addresses using a segment base and an offset - same as 8086Protected virtual address modeAddress unit functions as a MMU to access up to 16 Mbytes of physical memory and one gigabyte of virtual memory using the descriptor table


Architecture68 pin package16 bit data bus24 bit non multiplexed address busmemory hardware is set up as an odd bank and an even bankHOLD,HLDA,INTR,/INTA,NMI,/READY,/LOCK, and RESET pins are similar to 8086


80286 Real ModeWhen 80286 is reset,it goes in to the real address mode and can address up to 1MB of memoryThe IVT is located in the first 1Kbyte of memoryInterrupts are classified asinterruptsexceptionstraps and faults


80286 protected modeIf an OS of type OS/2 or Windows is used,the real mode is used toinitialize peripheral devicesload the main part of the OS in to memoryload some registersenable interruptsset up descriptor tables and switch to protected mode


80286 Protected mode80286 is switched in to protected mode by setting the protection enable bit in the machine status word register followed by an inter segment jump to the start of the main system programThis flushes the instruction byte queue and this is necessary because the queue functions differently in the protected mode


80286 Protected modeThis enables the integrated MMU to provide virtual memory and protectionCan be brought back to the real mode only by resetting the systemHence,80286 cannot easily multitask a mixture of programs in the real mode and protected modeThis is overcome in 386 and 486


80386 - FeaturesHas a 32 bit ALUSegments as large as 4Gbytes with 16384 segments making the virtual address space 64Tbytes32 bit address bus addresses up to 4Gbytes of physical memoryOperates in a virtual 8086 mode to switch back and forth between real mode and protected mode


INTEL 80386DXHas separate 32 bit data and address pins and generates a 32 bit physical addressCan address 4GB physical memory and 64 terabytes of virtual memoryThe IC has 132 pins and is housed in a Pin Grid Array (PGA) packageThe IC is designed using high speed CHMOS III technology


80386 for Embedded Highly pipelined as it performs instruction fetching,decoding,execution and memory management functions in parallelOn-chip memory management translates logical addresses to physical addresses and provides the protection rulesA 16 MHz 80386 can save the state of one task and load the state of another task in less than 16 mS - Task Switching


80386 Pins and Signals

80386 is available in two versions as 386DX & 386SXThe 386DX is a 132 pin ceramic Pin Grid Array (PGA ). Pins are arranged 0.1 inch ( 2.54 mm ) center - to - center , in a 14 x 14 matrix with three rows around386SX is packaged in 100 pin flat pack and has only 24 bit address bus and a 16 bit data bus


80386DX PGA pin out1234567891011121314

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A B C D E F G H J K L M N PA B C D E F G H J K L M N P


Functional Signal Groups80386 Processor2X CLOCKD0-D31 Data BusADS#NA#BS16#READY#Bus ControlHOLDHLDABus ArbitrationINTRNMIRESETInterruptsA2 - A31BE3#BE2#BE1#BE0#Byte Enables32 bitAddressW/ R#D/ C# M/ IO#LOCK#Bus CycleDefinitionPEREQBUSY#ERROR#Vcc GNDCoProcessorSignalingPowerConnectionsCLK2


Exploring the SignalsThe clock applied to the 386 CLK2 input is internally divided by 2Hence for a 33 MHz operation, a 66 MHz signal is applied to the CLK 2 input by an external clock generator such as 82384


Exploring the Signals

The 386 address bus consists of the A2 - A31 address lines and the byte enable lines BE0# - BE3# which are decoded from internal address signals A0 and A1The WR/R# signal differentiates Read and Write operation


Exploring the Signals (Contd.)

The D/C# indicates data read/write or a control word transferM/IO# indicates whether the operation is a memory or an I/O operationThe PEREQ is from a co-processor to tell 386 to fetch the first part of the data word for the co-processor


Exploring the Signals (Contd.)

BUSY# signal is used by the co-processor to prevent 386 from going on with its next instructionIf ERROR# signal is asserted by a co-processor , 386 will perform a type 16 exception386 has a large no. of Vcc and GND pinsThe READY# signal is used to insert wait states in bus cycles


Exploring the Signals (Contd.) The 386 address bus is not multiplexed. So an 8086 type ALE signal is not neededThe BS16# input allows the 386 to work with a 16 bit and or a 32 bit data busThe ADS# signal will be asserted when valid addresses,BE signals and bus cycle definition signals are present on the buses


The Byte Enable SignalThe byte enable outputs, BE0# through BE3# define which bytes of D0-D31 are utilized in the current data transferBE0# is low when data is transferred via D0-D7 BE1# is low when data is transferred via D8-D15BE2# is low when data is transferred via D16-D23BE3# is low when data is transferred via D24-D31


In the real mode of operation,the 80286 register set is the same as that of an 8086 except for the addition of a 16 bit machine status word register.Faults are exceptions that are detected before the faulting instruction is executed.The segment not present exception is an example of a fault.

The trap is an exception which are reported after the instruction which caused the exception executes.The divide by zero exception and the INT n interrupts are examples of traps.Setting the protection enable bit in the machine status word is done with the help of a LMSW(load machine status word) instruction.

x86-session09.ppt

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