X86 Session_01Introduction to Intel processors

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The 8086 Family16 bit processorCan address up to 1MB of memoryIf the first byte of a word is at even address, 8086 reads the entire word in one bus operationIf the first byte of a word is at odd address, 8086 reads the entire word in two bus operation

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8086 Internal FeaturesTwo independent functional partsBus Interface UnitBIU sends out addresses,fetches instructions, reads/writes data from/to ports and memoryExecution UnitEU tells the CPU where to fetch instructions from,decodes and executes the instructions

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The Execution UnitContains the control circuitryA decoderA 16 bit ALU A 16 bit Flag Register with nine flagsGeneral Purpose RegistersAH, AL, BH, BL, CH, CL, DH, DL16 bit stack pointer, base pointer, source index register and destination index register

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Flag RegisterU U U U OF DF IF TF SF ZF U AF U PF U CF8085 compatible flagsU - unusedOverflow flag

Direction flagInterrupt flagSingle step flag

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Bus Interface UnitA set of 16 bit segment registersdata segment,stack segment,code segment & extra segmentA FIFO 6 byte register set called queue

-PipeliningA 16 bit instruction pointerA memory interface

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8086 SignalsIt comes in a 40 pin DIP packageAD15 - AD0 form a time multiplexed address and data busA19 - A16 / S6 - S3 form the higher order address bits as well as 4 status signals that identify the type of operation being done in that cycleBHE indicates whether a complete word or one byte from/to an odd byte, or one byte from/to an even byte is being transferred

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8086 SignalsMN/MX signal selects one of the two operating modes,minimum mode and maximum modeS4 and S3 indicate the segment register that is used for the accessThere are two interrupt pins INTR and NMIRQ/GT0 and RQ/GT1 are used for switching the local bus between various bus mastersA bus controller such as 8288 is used

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8086 SignalsRESET input,if asserted takes the 8086 to the physical address FFFF0h8086 in minimum mode requiresa clock generator such as 8284address latchesdata bus buffersROM and RAM

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