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General Comment: You must notice that I have underlined all the teams.that appear in

this weekly report. Up to now, I overlooked them since its only a minute/insignificant

matter. But, since our relationship with foreign partners is increasing, I think its time tostop using this word for describing our organization.

Usually, an organization is divided into DIVISIONS or DEPARTMENTS as shown in

following two typical examples:

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The first is product-based organization, the second is job-based one.

TEAM is usually used for a small group assigned with a specific job, such as the

following organization.

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I know that you folks are very fond of SOCCER (British FOOTBALL). Therefore, you

like the word TEAM. But I have never seen any organization divided only in TEAMS

as you may think of ICDREC.From now on, lets divide ICDREC in to Departments; each Department may include

many Groups; each Group can include many Teams; each Team may include many

Forces; etc.

Stop calling you organization by TEAMS! OK?

Let me suggest that Director Hoang will hold a meeting of all group leaders to discuss

about ICDRECs organization, building an authentic organization chart for it, etc.

Dang Luong Mo

1. Spec2

2.1 Ngoc

In recent weeks, I focused on the MPEG-4 Encoder IP which is used in Camera IP. I

completed its specification including the features, the block diagram, pin diagram of the

whole system and each module. This system has 16 sub-modules with 3 sub-modules of

which three are reused ones from the previous projects. I also finished designing 2

important sub-modules, : (Note: the comma is not appropriate for this case. Use a

colon.) DC Prediction and AC Prediction. I will assign Dong and 1 new member to join

this project when they finish their current job. Next week, I will design the VLC

(Variable Length Coding) Module and Scan Module in the MPEG-4 Encoder IP.

2.2 Huynh

This week, I continue to check the file name format of the SD card in the TTS system. I

can use the long name format for files but for directories, there are still some issues.

Besides that, I continue to revise the introduction document of WLAN802.11n project.

We already presented it onWednesday at to The Department of Science and Technology.

Note: If you wish to use the word at here, you must write: We already made a

presentation about it on Wednesday at the Dept.2.3 Toan

This week, I also modified the content of the IPM2201 manual document and supported

the VCS team members to debug the IPM2201 chip bug. Next week, I will start to write

the IPM2201 datasheet document.

2.4 Thai

This week, I helped VCS team solve some small problems in the IPM chip. I and VCS

members also ran the newest sigma-delta model to find the best result of system gain

(value). We had this value and started running the system with this gain. Next Monday,

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we will check it and report to Analog team. I also received the Floatingpoint Unit

Designing task. So, I will start investigating the adder, multiplier and divider modules.

2.5 KhanhThis week, I continued working on the PEM chip project. I debugged the Calibration

module. Besides, I rewrote the RTL code for the Tiling module in version 3.

2.6 Quang

This week, I ran simulation for the Video scaler IP. There are some bugs;so I have to fix

it. Next week, I will complete the simulation and run move on to the FPGA.

2.7 Quynh

This is my first weekly report at ICDREC. This week, I design the 8 bit Counter module

which is the first mini-project in my training process. I also investigate about Digital

Design Rules and Hardware Implementation for DSP through related documents of

Spec2 team.

2. PCB

This week, Wwe are working on the layout on of the VIRTEX7-WLAN (FBPGA

group), modifying the layout on the REEFER-SG8V1, RS232-485 (APP group) project.

Besides, Wwe completed the layout of the HF-RFID-FIXED-READER-V03,

3PHASE-ELECTRICAL-METER and run gerber for FAB out. Next week, We

continue working on these boards.

3.

Physical Design

1. Binh

This week, I spend all of time to teach the IC Compiler tool in HaNoi. Besides, I run

Place and Route VN32V2 chip with new netlist (R1134V1) and export database to Mr.

Duong for timing checking.

2. Duong

This week, I continued to support Mr. Binh & Mr. Thai to analyze post-layout timing

analysis for the vn32v2 chip with the RTL_1134V1 version. After, I sent data layout to

the VCS team.3. Sang

This week, I continue working on the tape out process of VR and ADC24BIT projects.

All the request forms are filled, and the real tape out has been started. I also check on

Faraday IP website for the necessary libraries of the next 8-bit project. We need to sign

a NDA form to access the back-end libraries.

4. Dai

This week, I spent all of time to teach the Design Compiler tool in Hanoi.

5. Thai

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This week, I continue designing for R1134_V1 version netlist for VN32V2 project. I

continue fixing DRC and timing violation for R1134_V1-DFT version netlist. All

timing and DRC violations have been fixed. I have just received R1136_V1-DFTversion netlist. I will release data in next week.

4. FPGA

Mr. Chanh Nguyen

I studied some tools of Xilinx to build a digital system design training program on

FPGA for Luna Nexus company.

Mr. Khoa Hong

This week, I focused on writing the special reports for the RFID project. Besides, I

supported Mr. Vu to verify more test-cases for the VN1632LP version 2 system.

Mr. Quang Trinh

This week, I focused on reading docments about the WLAN. Then, I supported Mr.

Khoa writing thematic for the RIFD project.

Mr. Thinh Ngo

This week, I continued working on the Energy Meter IPM 2201 (PEM) project. I'm

building a system for testing Energy Meter IPM 2201 (PEM) on FPGA. I focused on

draw the flowchart for calibration process of IPM2201 chip. Besides, I also focused on

reading the user guide of SG8V1 chip.

Mr. Vu Tran

This week, I continued working on the VN32 project. I analyzed some test-cases to test

the DMA controller and the UART peripheral in the VN32 system. Currently, I'm

testing functions of the DMA controller.

5. Application

1. Dieu

This week, I continued writing the code for radioactive device supervising project. Mr.

Thinh and I had a surveying day to at Ung Buou hospital to learn about the shape and

the operation of radioactive devices. The survey aims to find out how to install oursupervising board on these devices. Besides, I also made some modifications for

XM100 based on comments from SaigonTrack Company.

2. Dong

This week, I continued writing some AT command functions to access the ethernet

module. I also wrote some functions to test reading and writing data of MX25L1606E

ash memory chip.

3. Tuyen

This week, I designed 95

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4. Cong

This week, I coded storing data into serial ash MX25L6460E. Because there werent

(barbarism!) some components, the board hasnt (barbarism!)been completed yet. So, Icouldnt (barbarism!)programme this code on the board to test it. Next week, I will have

enough components to complete the board and test the code.

Note: Write: werent, etc.

5. Duong Pham

This week, I continued to modify the code of the X200's black box for SaigonTrack

company. The camera is integrated in this black box. It has the ability to capture

cyclical and events(Remember: captureis a transitive verb. It needs a direct object. In

your case, events is alright as a direct object, but cyclical is an adjective! I dont

know what you really mean. Do you mean cyclical occurences and events?). Besides,

I also wrote the code for the X200SG8V1 device to connect the Taxi meter.

6. Minh Tran, La Thai Minh

This week, we review the impedance matching circuit between HF RFID reader with

directly matched antenna. Then, we measure some measures made some measurements

on the reader board to verify the theory. I'm also performing EEPROM reading and

writing test for RFID tag of ICDREC.

7. Quang Tran

This week, I receive HF handheld project from Mr.Khiem. He told me about building

OS, boardx schematics (Do you understand why I change the s from board to

schematic? Actually, youd better use the word schema.) and his android

application.

8. Tanh

Last week, I finished calculating the waiting time and money for a routine. Besides, I

finished storing the data into SD Card.

9. Loc

Last week, Renesas's Technical department worked with us on line quality. In duringthe test, we can't transfer data in room. The module didnt operate as the specification.

Transmit power is low so distant is short. Renesas concluded interference signal

transmission. They will provide a solution in the next week.

10. Hai

This week, I finished writing protocol for the transmission of data between the target

device and the server of the refrigerated container project. Besides, I checked

refrigerated temperature monitor devices which were installing on Saigon Newport.

11. Duy

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This week, I wrote the base firmware for the Bus Reader using SG8V1 and fixed some

bugs for the ash memory MX25L1606E driver.

12. TrungThis week I wrote Ethernet driver for CSEM53 module and ash driver that using for

Stand Alone readers using SG8V1 MCU. Besides, I converted firmware of the HF

RFID Simple Reader using PIC MCU to SG8V1 MCU.

13. Thinh

This week, I finished about 90

6. Spec1

Author: Le Phuc

Last week, I had three tasks. First, I worked with Verification and Embedded System

groups to verify the VN32 system. Second, I studied a 32-bit MCU architecture. I

focused on studying the memory map and AXI bus system. Finally, I wrote the

VN1632LP reports.

Author: Nguyen Hung Quan

After discussing the breakpoint and programming function with Mr. Nghi, Mr. Quoc

and Mr. Cuong, I completed the general specification of JTAG controller. I also

completed the instruction set description of JTAG controller. For the EEPROM chip, I

designed the new memory organization. Besides, I took part in the AMI project's

meeting on Friday.

Author: Nguyen Viet

Last week, I checked the specification of the Timer project and revised it to correct

some functions. I used the LEDA tool to fix some bugs in RTL code. I also cooperated

with Mr.Cuong to verify the Timer project by using the VCS tool.

7. Embedded

Mr. Phuc Truong:

This week, I suspended the three-phase smart electric meter project. I focused on testing

the DCM and the one-phase smart electric meter project.Mr. Loi Nguyen:

This week, I continued working on the GSM modem. I focused on verifying the first

firmware version of this modem. Besides, I kept on supporting Mr. Vu (Software team)

to verify this firmware. I also added some functions to write the default IP and Modem

ID from PC and completed verifying the 5 new GSM hardware. I mainly read the rate

table of supported meters now.

Mr. Tri Nguyen:

This week, I continued working on the single-phase smart electric meter project. I found

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some documents about RF module of DDS26D meter and LTE6 meter. Then, I studied

about data exchange between HHU (hand held unit) and RF module of these two meters.

I currently capture data which is used for configuring RF module of DDS26D meter. Iwill continue capturing data which is used for configuring RF module of DDS26D

meter next week.

Mr. Tai Trinh:

This week, I continued working on the HHU project. I optimized the schematic of the

HHU device. Currently, I subdivide the HHU schematic into 4 smaller schematics. They

are parts of the final device: main PCB, keyboard PCB, stamp board PCB and external

PCB.

Mr. Thang Tran:

This week, I worked on the DCU project. I am selecting the appropriate Sub-1Ghz

module used for DCU project. I also studied the ARM embedded programming with the

board that Mr. Tuyen (Application) gave to me.

8. Software

_ Hoa

This week, I modified the console-driver. Busy-box can connect to VN32-Kernel and

print some message via System-call function. But UNIX-System-V is not working.

Next week, I will test the console-driver. And I will fix bug of Busy-box.

_ Anh

This week, I studied protocol of VN8-GDB with JTAG. And I fixed some bug of

VN8-Simulator.

Next week, I will read documents for JTAG debugger.

_ Hieu Le

This week, I continued reading DMA memory. I debugged on VN32LP Kernel. I also

fixed programming function for IFast IDE.

Next week, I will continue debugging on VN32LP kernel.

_ Hieu HuynhThis week, I have continued to read about Lexer and Parser phase in GCC. So, I have

learned how to create a Lexer and Parser file for a simple Assembler. Then, I written

some basic instructions set for 8051 micro-controller.

Next week, I will continues for this task.

_ Khuong

This week, I reviewed about Predicates and Constraints in Machine Description, then I

read about VN8 Application Binary Interface.

Next week, I will continue readingit and Instruction Attributes, Iterators and Peephole

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Optimizer in Machine Description.

_ Ngoc

This week, I fixed some bugs of the VN8 compiler when I run the test-suite.Next week, I'll continues doing for this task.

_ Nghi

This week, I finish write functions which optimize IHA and IHO instructions for

VN8-LD linker. Besides, I discussed in designing how to design theJTAG Debugger

for VN8 with Mr. Quan. This week, I will test UART driver in Kernel of VN32LP with

Mr. Hoa.

9. IDL

1. Van Anh

This week, after reviewing, I corrected the design of HHU and RFID handheld in detail.

2. Thao Nguyen

This week, I completed the cover of taxi meter and reefer supervisor device by

correcting, rendering and exporting their dimension drawing. Then, I designed one more

style of Hand Held Unit (HHU) cover to show ? (Where is the object of this verb?).

3. Bao

This week, I have assemblied components for:

-board Reefer.

-board X-SUPERVISOR- DV-PRO.

(This man, Bao, must come to see me!)

4. Man

This week, my work is performed as follows: - To designing the cover of the RFID

Handheld and HHU. - To export the design of Access-sample and Name-display follow

CNS's request.

10.IT Man.

This week, our activities were as follows:

With regard to the Design House, we sent some emails to seek for technical support toWestern Technology and Services Corporation, a distributor of NetApp in Vietnam. We

collected as many NetApp system logs as we can to send to NetApp technical team for

them to analyze. While we were waiting for NetApp technical support, we tried to solve

problems on NetApp data-store. We migrated DC02 server to another data-store. We

then cloned DC01 and VC01 to VMware templates and NetApp Filer templates. On

Friday, together with NetApp technician, we did some re-configurations on two NetApp

controllers to solve problems on NetApp data-store. We also asked them to create an

account to open a case for NetApp Support Site. We also did the same way for Cisco

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UCS.

With regard to technical help desk, for email accounts, we supported resetting some

accounts for Project Management team and Education team. For network-relatedproblems, we supported assigning static IP addresses for remaining computers. We also

support reinstalled OS and fixed network connection for computer of Accounting team.

For SG8V1 web page, we made a simple counter to count on number of downloads and

on number of visits on this page. However, this counter can only be viewed for

authenticated users at the moment.

Next week, we continue monitoring NetApp data-store to get DHCP server and other

system services running again. We will also continue on HTCondor.

11.Verification

1. Hung

Last week, I focused on modifying the VN8E C-model and test environment following

specification changes. Concurrently, I also started delivering tasks of the VN8E project

to my members. Besides, I continued following my members jobs in the PEM and

VN32LPV2 projects.

2. Phuong

Last week, I graded the exam of student. Besides, I also studied how to build UVM

environment for CPU 8 bits

3. Ngan

Last week, I worked on the VN32LP testing project. I adjusted the C-model as latest

change on the core specification. I continued reviewing the code coverage to find the

untested cases and exclude untouchable cases. I ran the benchmark program in layout

mode, and sent the VPD files to Mr. Duong (PD team). I also corrected some failed

testcases which are used to test the full speed transfers in the USB peripheral.

4. Loc

This week, I continue to write the model for the analog module in the PEM project. I

rerun all testcases of the low rate calculator and the calibrations. At the current, sometestcases have errors. Im debugging them. I will complete it in next week. Besides, I

join the progress review of the PEM project.

5. Thinh

This week, I ran some testcases to test VN32v2_Core again as Mr.Quynh requested

after fixing one bug in UL2 Stage of VN32v2_Core. I found out one code-bug and Mr.

Quynh also fixed it. Besides, I continued running testcases for testing SSPI with the

newest layout version.

6. Toan

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This week, I continue to test the PEM(Power Energy Measurement) chip. I get a Matlab

model from analog design. I rerun testcases to evaluate the model. Besides, I run the

coverage of DUT.7. Tien

I reran all the testcases of VN32 chip because there were some chances in the RTL code.

The chipstress testcase was being failed at Ethernet IP and I had Mr.Dung help me to fix

them.

8. Man

This week, I kept checking for the PEM project. I modified some test-cases of Mr.Toan

to test in the system mode. I also upgrade the checking environment to support the

functional coverage. When run testcases to get the coverage report, I detect a problem in

V/I Peak calculation, I asked Mr.Khanh to fix.

9. Dung

Last week, I modified the setting of Ethernet module in stress test for the latest revision

of RTL. I also updated the Gate Simulation environment for layout revision r1134. Im

debugging the failed cases. The revised version of Gate Level environment will be

released next week.

10. Linh

This week, I continued to investigate the JTAG documents. I finished investigating the

JTAG architechture, the boundary scan. I also started making the deep investigation

about the main parts of JTAG, such as : The TAP controller, the Instruction Register,

Test Data Register, ... Im going to finish this task in next week.

11. Giang

This week, I finished collecting the result of DFT simulation for VN32 CORE and

continuing to investigate DFT Compiler TetraMAX in case of SCAN insertion and

STIL generation. Besides, I did some VMM labs from Synopsys.

12.Education

This week, we focus on preparing the phase 1 dossier finalization of project training forthe Department of Information and Communications. Besides, we also construct

training project from 2015 to 2019. In addition, we have worked with companies

Lunanexus about curriculum to designing IPs on FPGA, cooperation in outsourcing

PCB and building a PCB design team for their company.

Last Thursday , I also have visited and worked with SmartPro company. Headquarter of

SmartPro in District 3. They invested infrastructure and had marketing team. They want

to cooperate with ICDREC implement training programs to recruit candidates and

support facilities and place for training courses.

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Device design. Next week, I will finish the spec.

Hien Nhan

This week, I continue writing test case to test Timer, Suspend, Detect Speed and SendFeedback block and correcting timing of some block on USB Host project. Besides, I

attend meeting about USB Hub project and previewing of USB Device Verification.

Nam

This week, I continued reading documents on operational amplifiers. Next week, I will

give a present about it.

Thien

I designed completely the Decryption block of the AES design using the Verilog HDL.

Besides, I reviewed the specification of the AES IP core and fixed some errors of the

design. Next week, I will write some parts of the specification document for the design.

14.Analog

Ho Quang Tay

This week, I explained some comments of the RFID committee regarding the second

and third projects. Besides, I also arranged some meetings to review the GPS receiver,

the switching regulator, the HV comparator, the 10-bit SAR ADC, 32Khz and 8Mhz

oscillators and the modulator in the PEM. Meanwhile, the LED project is reviewed for

the features and planned for the schedule.

Nguyen An Hoa

This week, I modeled a 10-bit ADC and a 10-bit DAC by using the verilog-A. The

purpose of the model is used to debug the design of the 10-bit SAR ADC. Besides, the

10-bit DAC model is also used to measure the INL and DNL for my real circuit. I have

problem in my design of 10-bit SAR ADC. It regenerates waveforms which are

incorrect comparedwith the ideal 10-bit ADC. Next week, I will continue this task.

Tran Hoang Thuong

This week, I focused on fixing my drawing in layout to seperate the IO pins, inputs on

the letf and outputs on the right. It is easier to combine them with IO Pads and theController.

About the 4S conference, I joined to the sessions: Data Converter II (A Delta Sigma

DAC, FPGA, 10 Bit Pipelined Cyclic ADC), RF Circuit Design (A 1.2V Fully

Integrated Voltage Controlled Oscillator in 130 nm CMOS for GPS Receiver),

Semiconductor Devices I (Schottky diode fabrication). On the whole, I got the new

solutions in my fields (at least, methods). Furthermore, I reached the knowledge to build

a structure of a scientific research as well. Additionally, I also knew "where we have

been standing". It is an effort to study, research.... more in my thinking.

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Dang Duy

Regading the 4S conference, I was very impressed by the efficiency improvement of

switching power circuit. I am reading some switching papers to figure out the idea.Besides, this was the first time that I had touched the wafer by my hand and I can see

clearly the trends of semiconductor industry in future.

Nguyen Tuan Khanh

This week, I continue studying the sleep and wake up mode for GPS project. Besides, I

started researching the Quadrature VCO - QVCO for matching with LO input of Mixer

which was designed by Mr. Dinh. Next week, I will continue these tasks.

Nguyen Dinh Thuc

This week, I continued estimating the total amount of noise power to calculate the

different capacitor sizes. Besides, I am researching a method on a structured way set the

requirements on an OTA, which should be used in a SC-Integrator. The parameters

which are unity gain bandwidth, slew rate, phase margin, DC-gain and output range.