Work Package 3 On-detector Power Management Schemes

ESR Michal Bochenek

ACEOLE Twelve Month Meeting1st October 2009WPL Jan Kaplon

Aim of work

Development of new, efficient power distribution schemes allowing for major reduction of amount of material inside the particle detectors

• DC-DC conversion technique• serial powering schemeObjective; development of radiation-tolerant

ASIC building blocks for upgraded front end electronics for ATLAS SCT

ABCN, a prototype chip for Si strip readout in Upgrade Inner Tracker

Binary readout

Front-end optimised for short strips

Positive or negative input charge

Readout clock up to 160 Mbits/sec

250 nm CMOS (IBM) technology

Compatible with serial powering scheme and DC/DC converters (high filtering efficiency of Linear Regulator)

Analogue supply (2.2V) obtained from 2.5V digital power rail (shunt in case of serial powering or DC-DC converter) by means of Linear Voltage Regulator

Next step; ABCN in 130 or 90nm• Motivation; lowering power consumption

(lower voltage supply, better noise power figure)

• Change in overall voltage supply from 2.5V to 1.2V, digital part supply with 0.9V (further reduction of power reduction) this imply the change in the currently adopted power distribution schemes (both DC-DC and serial approach)

Possible power schemes for ABCN in 130nm, serial powering

vddd

gndd

Vdd(a)

gnda

Fully integrated Shunt Regulator

ABCN Digital

ABCN Analoge

0.9 V

1.2VVoltageRegulator

DC-DCCharge pump

1.5V

Designed by M. Bochenek ABCN

Possible power schemes for ABCN in 130nm, DC-DC approach

2.8V

gnd

DC/DC buck

converter on module

ABCN Digital

0.9 V

VoltageRegulator

1.2 V

ABCN Analog

DC-DCStep-

down /2

2V

gnd

DC/DC buck

converter on module

DC-DCStep-

down /2

1.4 V

10V

10V

Designed by M. Bochenek

ABCN

Architecture of a step-down DC-DC converter

The core of the DC-DC step-down converter is built of four transistors (one PMOS and three NMOS) and threeexternal SMD capacitors. The whole circuit is suppliedwith 2.0 V. Due to the better driving capability of switches, workingwith lower output voltage, there is no need to use any level shifters.The output voltage is as high as 920 mV for a nominal current, whichis 60 mA, but the converter can operate at 100 mA with powerefficiency up to 88 %.

480um

200u

m

Step-up charge pumpThe switched capacitor step-up charge pump shown is based on the voltage

doubler circuit. The main part of the circuit consist of two cross-coupled NMOS transistors (M1 and M2), four PMOS transistors working as serial switches (M3 – M6), three external SMD capacitors (CPUMPX and CLOAD) and one capacitor integrated on the chip (C pol).

The optimized working frequency is around 500kHz.Due to the poor driving capability of the PMOS serial switches, two level

shifters are needed. Those voltage shifters require two voltage supplies, the input signal voltage supply (0.9 V) and the output signal voltage

supply (VOUT = 1.6 V) taken from the output of the charge pump.

Minimum efficiency 84% over a full corner sweep

To be done

• Implementation of the fully integrated shunt design from ABCN (250nm) in the 130 nm technology (3 possible architectures).

• Implementation of the serial regulator in 130 nm.

• Integration of a complete power management blocks (DC/DC, shunt, linear regulator) on the front-end prototype chip.

Summary of on-the-job training • Training in schematic, simulation and layout tools

(CADENCE/SPICE)• Courses;

– Advanced Engineering Course OPERATIONAL AMPLIFIERS: Theory & Design (10.11.2008 - 13.11.2008, Delft University of Technology, Delft, The Netherlands)

– Adaptive Power Management Course (8.02.2009, ISSCC, San Francisco, CA, United States)

– Low-voltage and Mixed Signal CMOS Circuit Design Course (12.02.2009, ISSCC, San Francisco, CA, United States)

– EIROforum School of Instrumentation (ESI) (11.05.2009 - 15.05.2009, CERN, Geneva, Switzerland)

– Low-Power, Low Voltage Analog IC Design (22.06.2009 - 26.06.2009, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland)

Deliverables• TC31 (month 6), Training courses in microelectronics design methods,

CAD tools, design of circuits for regulators, etc (completed)– Advanced Engineering Course OPERATIONAL AMPLIFIERS: Theory & Design

(10.11.2008 - 13.11.2008, Delft University of Technology, Delft, The Netherlands)

– Adaptive Power Management Course (8.02.2009, ISSCC, San Francisco, CA, United States)

– Low-voltage and Mixed Signal CMOS Circuit Design Course (12.02.2009, ISSCC, San Francisco, CA, United States)

– Low-Power, Low Voltage Analog IC Design (22.06.2009 - 26.06.2009, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland)

• W31 Participation in TWEPP workshop (completed)– Paper “An integrated DC-DC step-up charge pump and step-down converter in

130 nm technology” presented on Topical Workshop on Electronics for Particle Physics (TWEPP09) (21.09.2009 – 25.09.2009, Paris, France)

Secondment • The secondment is planned at AGH, University of Science and

Technology, Krakow; • Preferred duration of the secondment is 3 months at the end of the

ESR contract• Plan of activities anticipated for the secondment:

– Participation in preliminary tests of full ATLAS SCT readout chips integrated with the power distribution system designed by the ESR during his contract at CERN,

– Preparation of the final report on milestones and deliverables for the European Union Committee,

– Passing final obligatory exams before a defence of a doctoral thesis.

Training by Visitor Scientist

A visit of senior scientist from AGH University of Science and Technology, Krakow is to be organised.