Wir schaffen Wissen – heute für morgen 8. Januar 2014PSI,8. Januar 2014PSI, Paul Scherrer...

Wir schaffen Wissen – heute für morgen

10. April 2023PSI, 10. April 2023PSI,

Paul Scherrer Institut

Status of CAVITY BPM RFFE & ADC

June 24, 2010

Markus Stadler

Talk agenda

M. Stadler Cavity BPM RFFE & ADC - Status Seite 2

•RFFE overview

•Mesurement results

•Redesign measures

•Performance expectation of BPM system

•Outlook

24.6.2010

Front-End redesig: RF section

LO generator

mixer

Range switch

3.3GHz BPF

IF amp. / filter

M. Stadler Cavity BPM RFFE & ADC - Status 24.6.2010 Seite 3

Prototype RFFE: System overview

Seite 4

• direct downconversion to (near) zero IF• tunable (in steps) LO frequency• tunable LO phase• on-board conversion clock generation for ADC

M. Stadler Cavity BPM RFFE & ADC - Status 24.6.2010

Pulse response

Seite 5

ADC output (ref-Q)

-14000

-12000

-10000

-8000

-6000

-4000

-2000

0

2000

4000

0 100 200 300 400 500 600

time (ns)

AD

C v

alu

es

• Baseline=ADC-offset


Distance measurement principle

Seite 6

0

2000

4000

6000

8000

10000

12000

14000

16000

0 200 400 600 800 1000 1200

time (ns)

AD

C v

alu

es

mag(REF)

mag(Y)

R

Y

)( mR

YkD YY Basic distance calculation:

R and Y are in ADC-LSB, ky is in μm


Jitter estimation (1)

Seite 7

Estimating position jitter from equivalent ADC input noise

)( 2

2

2

2

mYRR

Yk YRYDY Position jitter:

kY: proportionality constant (≈meas.range/2)

Y,R: Y- and Reference channel peak amplitudes (ADC LSB or volts)

σR, σY: ADC equivalent input noise (LSB rms or volts rms)

Estimation (rather than calculation) because only additive noise is considered !


Jitter estimation

Seite 8

RFFE / ADC total noise (ADC equivalent input noise)

CH RFFE 1 (μV-rms) RFFE 2 (μV-rms)

I_REF 172.5933 164.7761

Q_REF 163.8715 158.8132

I_Y 165.9212 177.2467

Q_Y 166.2281 163.8363

I_Z 163.6221 164.2646

Q_Z 160.906 166.5494

ADC (LTC2206) high gain mode (FS=1.5Vpp)

Measurement:

Calculation: System noise (figure) calculation yields 169 μV-rms


BPM Prototype Resolution Measurement (SLS-Linac)

Seite 9

:5SLS Reference

500 MHz

R FFE2

100 M H z R eference

REF (m onopole) cavityre f

z

y6

Virtex Eva l-B .

V irtex Eva l-B .

AD C6

SC LK

AD C -Input

M L550

AD C

SC LK

AD C -Input

M L550

Y (dipole) cavity

R FFE1

100 M H z R eference

ref

z

y

Measurement principle:

Measure of identical signals with two independend BPM Systems and correlate measured distances

measured D2 (μm)

measured D1 (μm)

Assuming identical distributions of measurements D1 and D2:

2

2121

DDVarDD


Example measurement series (1)

Seite 10

-3

-2

-1

0

1

2

3

0 50 100 150 200

bunch no.

measu

red

dif

fern

ce (

μm

)

Settings: 0.15nC / 400μm

ADC: High-Gain mode (FS=1.5Vpp)

jitter: 0.61 μm-rms (measured)0.62 μm (calculated)


Example measurement series (2)

Seite 11

Settings: 0.3nC / 500μm

ADC: High-Gain mode (FS=1.5Vpp)

-1.5

-1.0

-0.5

0.0

0.5

1.0

0 20 40 60 80 100 120 140 160

meas no.

measu

rem

en

t d

iffe

rnece (

μm

)

jitter: 0.33 μm-rms (measured)0.28 μm (calculated)


RFFE Pulse Linearity Measurements

Seite 12

-4 -3 -2 -1 0 1 2 3 4-3

-2

-1

0

1

2

3

4

RFFE input peak voltage (Vp)

AD

C d

iffer

etia

l inp

ut v

olta

ge (

V)

ADC FS

Prototype System pulse linearity:


Front-End redesig: Local temperature control

• Prototype RFFE temperature dependence suggests that temperature should be stabilized to better than 0.5 ºC

• In redesigned RFFE several local temperature control loops applied

Measured amplitude temperature dependence of prototype RFFE

20

22

24

26

28

30

32

0 20 40 60 80 100 120 140

time (min)

Tem

p (

°C)

0.47

0.472

0.474

0.476

0.478

0.48

0.482

0.484

0.486

0.488

0.49

0 20 40 60 80 100 120 140

time (min)C

H1,

CH

2 am

plit

ud

es (

Vp

)

1.011

1.012

1.013

1.014

1.015

1.016

1.017

1.018

0 20 40 60 80 100 120 140

time (min)

CH

2/C

H1

Temperature:

Absolute amplitude drift (incl. switch-on drift):

Drift of amplitude ratio:

Ca. 0.1% per deg-C


Conclusion from Measurements

Seite 14

• Measurement jitter is < 1 μm

• Measured jitter in good agreement with calculation

• Temperature sensitivity needs improvement

• Linearity is within 2%

• Additive noise sources in signal chain dominate the jitter performance

• Synthesizer phase noise / timing jitter do not significantly degrade performance

→Redefinition of charge ranges improves resolution

→local temperature control

Measurements on prototype system suggest the following conclusions:

→not much margin ! Difficult to measure

→simple and cheap PLL-synthesizers can be retained


Front-End Redesign (1)

Seite 15

• RFFE control via single I2C-bus• Temperature controlled critical circuit parts• 216 MHz machine reference (previously 81MHz)• IF-amplifier redesigned providing gain control (Pick-up tolerances)• Redefinition of charge ranges• Hot-Swap controlling

Main RFFE design changes:


Front-End redesign (2)

• RF Phase Control (360 deg)

• RF frequency control (9MHz steps)

• Conversion Clock Phase Control

• 12 Local Temperature Stabilizaiton areas on the PCB (analog or digital) around sensitive circuit parts

• Charge Range control (3 ranges from 0.1 to 1nC, 1 low charge range)

• 160MHz / +12dBm ADC clock output

Main RFFE design changes:


Front-End redesig: Local temperature control

Local temperature control circuit:

•Temperature sensitive circuits are locally heathed at 2-5ºC above their free-running steady state temperature.

•This will consume about 300mA of extra current (whole RFFE)

• Temperature stabilization: analog or digital control

• Temperature readout resolution 0.04 ºC


Front-End redesig: RF section

Prototype: 2 charge ranges

Upper range: 0.3-1nC

Lower range: 0.1-0.33nC

→ Charge ratio =3.3

Redesigned: 3+1 charge ranges

Upper range: 0.48-1 nC

Mid range: 0.22-0.48 nC

Low range: 0.1-0.21 nC

(additional range: <0.1 nC)

→ charge ratio =2.1

sp litte rin p u t B P F

S P 4 T S P 4 T

Max position jitter ~ (charge ratio) · (meas. range)


Linearity dictates ≈0dBm at full-scale offset and charge

Minimum pickup sensitivity:

0dBm at mixer RF-port @ max. beam offset and upper bound of lowest charge range

(WITHOUT an RF amplifier)

In our case (2.2dB cable loss for 6m of RF cable and 0.21nC bunch charge):•6 mV/(nC·um) for ±1000 um•3 mV/(nC·um) for ±500 um

Cable loss RF-path loss

Pick-Up sensitivity for lower charge ranges

First priorities to maintain resolution at lower charge ranges (<0.1nC) would be: • Reduce losses in cable and RFFE RF-part• Increase pick-up sensitivity


Redesigned RFFE block diagram


Expected Performance of 2nd Prototype

Seite 21

Single bunch resolution (μm-rms)

Performance estimation based on calculations and measurements on 1st prototype:

Temperature sensitivity <0.3 %/ºC

linearity <2%

Bunch to bunch crosstalk

<1 μm (digital comp.)

For a complete list of performance numbers see project doc.

Charge Range

Charge (nC)

Beam offset (μm)

10 1000

high1.00 0.23 0.25

0.47 0.48 0.54

mid0.47 0.23 0.25

0.22 0.48 0.54

low0.22 0.28 0.31

0.10 0.60 0.67


Outlook

Seite 22

Status Start date End date

Schematic drawing Review

PCB layout Started Jul 2010

Mechanical drawings(shield, front-panel

Aug 2010

PCB assembly Aug 2010

Laboratory tests Sept 2010

Tests (SwisFEL 250MeV injector)

Sept 2010 (?)

Tests FLASH Nov 2010 (?)


Seite 23

Thanks !


Wir schaffen Wissen – heute für morgen 8. Januar 2014PSI,8. Januar 2014PSI, Paul Scherrer...

Documents

Transcript of Wir schaffen Wissen – heute für morgen 8. Januar 2014PSI,8. Januar 2014PSI, Paul Scherrer...