What is µP?

• “An integrated circuit containing … a central processing unit (CPU) and a means to access external memory” -- (Ball 2000)

Memory

• Memory types– RAM– ROM, PROM– EPROM, EEPROM, Flash

• RAM Memory Cellinactive read write

0 x 1

0

xx 1

1

yx y

Bus• Collection of signal lines -- uni(bi)directional • Operation represented using timing diagrams• Clocked vs Asynchronous separate data and address buses

System Bus Control Signals

• Multiple users?– arbitration

– sender/reciever id

• Multiplexed?– data ready

– clock

• Block Transfer– busy

PCI Bus -- Read

CPU Architecture

VonNeumann– code can be modified

(accidentally)

CPU

CPUDataCodeDataCodeData

Data Code

Harvard– data access does not

slow code access

– instruction and data widths unrelated

CPU Internals

Registers: Storagefor data

Control Unit:issues control path signals

(micro-operations)to other parts of

CPU

ALU:manipulates

data in responseto signals fromthe control unit

Bus:Transports databetween ALU and registers

CPU Architecture

Accumulator Stack Register

w=1;w=w+2;

Ra=1;Rb=2;Ra=Ra+Rb;

2 3

1 1

0 0

0 1

1 30

21 31

Push 1Push 2Add

Instruction vs. Micro-operation

Write

Add Instruction - FetchAddress Pnemonic Value1100 load 1 00 00011101 add 5 10 01011110 jmp 1100 ……….

CUPC

IR

12

3

11011110

00 000110 0101

1101 10 0101

1

3

0001

Add Instruction - Indirect (Decode)

CU

IR

1 ALU operation0 add

0 bit 31 bit 20 bit 11 bit 0

0101

Control signals

Add Instruction - Execute

CU

1

2 3

0101

1 3

0001

ALU

1 1

0110

Status flags

add

RISC vs. CISC

• Single-cycle instruction execution– Simple, fixed instruction

format

– few instructions and addressing modes

– Hardwired micro-operations

• Memory Access– Load/Store design

– High-performance memory (registers/cache).

• Predictable Speed/Performance

• Multi-cycle instruction execution– Variable size instruction

format

– Micro-programmed instruction set

• Smaller program size (# of instructions)

• Memory Access– Multiple addressing modes

• Optimization Complexity

Pipelining

Fetch1 Indirect1 Execute1 Write1 Fetch2 Indirect2 Execute2 Write2

Fetch1 Indirect1 Execute1 Write1

Fetch4 Indirect4 Execute4 Write4

Fetch2 Indirect2 Execute2 Write2

Fetch3 Indirect3 Execute3 Write3

Fetch5 Indirect5 Execute5 Write5

• Assumptions:– stages all have same duration

– no branching

– consecutive instructions are independent

Architecture vs. Organisation

– Bit Widths

– Instruction set

• CPU components– bus operations

– parallel/replicated functions?

– Pipelining

– RISC/CISC

– Control signals

– Micro-operation set

• external interface– access times

– RAM: static vs. dynamic

• physical layout – manufacturing process

– logic family

– track length

– power/heat considerations

Move register register

Store register memory

Load memory register

Exchange register register

Swap lo-nibble hi-nibble

Clear 00000000 register

Set 11111111 register

Push register stack

Pop stack register

Machine Instructions Data transfer

Machine Instructions Arithmetic/Logical

increment, decrement, not

absolute, negate,

two’s-complement

add, subtract, multiply, divide

and, or, exclusive-or

register

register

registerOP register

register

Machine Instructions:Bit--Logical

···

···

···

···

x

== x?

x y ?==

Bit-set, Bit-clear

Bit-test

Bit-compare

Shift Rotate

Machine Instructions Control transfer/Special purpose • Program flow

– skip [PC]=[PC]+1

– branch [PC]=?

– call push [PC]; [PC]=?

– return pop [PC]

• Processing pause– nop 1 cycle delay

– sleep wait for event

– wait ? cycle delay

• Special: – input/output

– data conversion

– system operation

• Compound– conditional branch

IF BIT-TST BRANCH

– return with valueLOAD VALUE

RETURN

Machine Instruction Examples

Add

Load

Branch

• Arithmetic• Data Transfer• Control Transfer

Address Mnemonic Value1100 load 1 00 00011101 add 5 10 01011110 jmp 12 01 1110

Operand4 bits

Op-code2 bits

Addressing Modes

Displacement VariantsRelative

Base RegisterIndexing

Post-IndexingPre-Indexing

How Many Operands?0-operand

PUSH 5PUSH 6ADD

1-operand

LOAD 5ADD 6

2-operand

LOAD R1,5ADD R1, 6

3-operandLOAD R2, 5ADD R1, R1, R2

Stack Accumulator Register

Var

iabl

e le

ngth

inst

ruct

ions

,O

pera

nd S

peci

fied

A

ddre

ssin

g M

odes

System Reset / Program Launch

Branch 01000000

Load 5

Add 2

…...

0100

0101

0110

End1110

Operating System

Start

Halt

Development Software Tool Chain

IDE

DownloadProgram

Compiler

Linker Simulator

In-circuit Debugger

Editor

Live