What I do.

1Nanotechnology Stuff…

The College of ComputingGeorgia Institute of Technology

What I do.

Mike Niemier (a.k.a. Mike)[email protected]: 404-894-1704 (w)Phone: 404-843-9511 (h)



My research goals…• Introduce a systems-level research component to

computing at the nano-scale– In my case with a device called “QCA”

• Advance coupling b/t nano-scale devices & computer architecture

• Define operational regions for systems of QCA cells• Combine advances in nano-scale devices and

computer architecture– (to get to real systems sooner & more productively)

• Makes physicists work more with systems people– Help them understand everything else that’s

involved to get to computation– (and make them LIKE IT)



Architects & nanotechnology1st devices…

• Quantum transistors, RTDs, SETs, computing w/molecules, nanotubearrays, quantum computing, DNA-based computation, …

Nano-tubes and Nano-wires:(Fuhrer, Goldstein, Dehon)

• Applications• Interconnect, SETs, levers• Structures

• Arrays, crossbars, FPGAs, fabrics• Challenges• Alignment, defects, micro/nanointerfacing, gain/signal

restorationcustomization• Hot: compile to space• Not: compile to time

Quantum computing:(Oskin, Chong, Chuang)

• Only small devices built, lots of error correction, dataflow?



An intro. to QCA• Conceptual Quantum-dot Cellular Automata (QCA)

– Binary information encoded in charge configuration

• QCA, CMOS, and Zuse’s paradigm:

QCA: molecules = charge containers, not current switches

Cell 1Cell 2

Cell 1Cell 2

Cell-cell response function• A cell with 4 dots• 2 extra electrons

• Tunneling between dots

• Bi-stable, nonlinear

• Restoration of signal

• Robustness against

cell-to-cell response

levels

disorder

Paradigm shiftto molecularelectronics

Similar propertiescross implementation!



Why My Work (Part 1)• CMOS provides faster devices, clocks, more

computation– …but architects provide smarter computation

• Moore’s Law trends may be continued w/nano-scale devices– A particular focus: molecular nanoelectronics…

• High functional density: 1011-1013 devices/cm2 (ideally 1014)

• Ultimate limit of device scaling…

• Most nano-scale devices targeted for computational systems– Architects understand them best– To complete the picture, we must answer:

• Can we “compute” within different device paradigms?• Can system-level research help drive device research?



Why my work? (part 2)• ISCA: International Symposium

of Computer Architecture– Only 2 papers on emergent

technologies to date…• …but that session in 2001• …and this work part of it

• Bob Colwell’s “3rd Prediction”:– CMOS-based Moore’s Law ends– Other technologies will be

looked at, needed; ISCA will too

• NSF NIRT grantee conference:– Question: “What’s missing?”– Answer: “Architecture”

ISCA paper by topics

Source: Bob Colwell, ISCA 2002 keynote



My Old Work

Progressed to simplecircuits, architectures

Systems work…

Design rulesbridge the gap

q2 = 0oq1ey

ey

1

4 23

3 3

2 43

1

1

1

1

4 23

3 3

2 43

1

1

1

1

1

mP, generic architecturesnext logical step

Early work:devicesDevice physics work…

Molecular devicework

Custom work setsthe stage for

buildable designsAlgorithms to assist w/constraints

of QCA routing/layout

D FC EBA

4 63 521



A bit of background

ClockingZone 5

ClockingZone 4

ClockingZone 3

ClockingZone 2

Wire Position

TimeStep 1

TimeStep 2

TimeStep 3

TimeStep 4

TimeStep 5

Tim

e ClockingZone 1Fixed

“driver”cell

“Schematic”

SwitchHoldReleaseRelaxSwitch

HoldReleaseRelaxSwitchHold

ReleaseRelaxSwitchHoldRelease

RelaxSwitchHoldReleaseRelax

HoldReleaseRelaxSwitch Switch



Affecting device development1 2 3 4 1

12341

(input)

(input)

(input) (output)

(device)

Logic on topof wires

Device physicists/EEs studying howto build/implement/test/simulate

our floorplan functionality

This floorplanfunctionality seen

here…

Cou

rtesy

of

Cra

ig L

en

t



JMP ADD

A bit more of my old workInstruction/

StateRead/

Write AccRead/Write

PCRead/

Write IRBmuc Select

New Mux Select

B-Invert (AND/OR)

Carry-in Zero A Logic / Adder

Mem write engable

PC/IR = Mem. Add.

P+G+F+B+S+C

Hold P+G+F+B+S

Hold P+G P P+G+F P+G+F P+G+F P+G+F Disable D.C.

M+H+E+N+G+F+B+R+A

M+H+E+N+G+F+B

+R

Hold Hold M+H+E+N+

G

M+H+E+N

M+H+E+N+G+F

M+H+E+N+G+

F

M+H+E+N+G+

F

M+H+E+N+G+

F

Disable M

Select PC/IR asmemory addr.

A B

ProgramCounter

InstructionRegister

Acc

Memory

NewMux

B Mux

PC/IR

ALU

AB

C

D

E

F

G

H

I

J

K

L

M

N

P

Q

RS

PC-to-Bmux feedback

Acc-to-ALU feedback

Acc-to-memory feedback (for STORE instruction)

PC-to-memory path

IR-to-memory path

Data from memory (for LOAD/arith. instruction)

IR-to-ALU(loads P

C for JM

P)

Memory-to-IR(loads in

st. into IR

)

Read/Write IR

Bmux select

Memory writeenableB-invert (AND/OR)

Carry-in

Logic/AdderZero A

Read/WritePC

Read/WriteACC

Shows consequences“pipelining provides”:Computation ballistic!

Before: processing iswhat’s possible in 1time step

Now, coordinatesignal arrival times toensure processing will

occur at all



A roadmap for new work…

start

Gather basic information – Ek,

required clock strength, etc.

1

Do a logical circuit layout in QCA

2

Simulate for logical correctness

3Are defectstolerable?

Yes

No

Yes

No

NoNo

Yes

Investigate thicker wires, stronger clocks,

etc.6

stop

Design CMOS clock structure to produce

E-field9

Calculate # of cells allowed per clock

window7

Is environmental quality < Ek? 8

Is therea “race”? 12

Study race cond., calculate critical path

length11

Introduce defects into logical layouts

(use stats from physical experiments)4

Yes

NoCan changein clock help?

YesCan clock be built? 10

Re-simulate for logical correctness

5



CAD

A B

C D

B A

C D

no crossingeliminate

d

B A B

C D

buildability constraints

metby duplicating

a node

We can rearrange nodes to eliminate crosses

4 5 6 45 6

1 2 3 1 2 3

Because of QCA’s clock, only certain # of cells are active (able to compute) at any one time. If it takes too long for a value to propagate, the wrong answer will appear at the output.

CAD can address this problem by optimizing for path length – or, as the clock moves from left to right, reducing the vertical height of wires (i.e. length x is shorter than length y).

This is the first cut of an ALU; it is much less dense than equivalent designs.

Input A

Input B

Input C

Input A

Input B

Input C

Majority Gate

Window of computation

x y

M

MM

1 (or)A

B

0 (and)

0 (and)

XOR: (A and B’) or (A’ and B)(there is an inherent crossing)

xor

xor

xor

AB

B

A

A “logical” wire crossing

AB

Using planar XOR made of NANDgates, circuit at left can be built

Duplicate to eliminate crossesRearrange to eliminate crosses

Minimize clock skew Improve circuit density

Logical crossings are alsopossible…

Buildability ConstraintsThe building blocks that currently make up our “parts library” are restricted to the DNA-based substrates (Fig. 9a), circuits that use only 1 type of cell (i.e. only 90-degree cells), and circuits that have no wire crossings.



Systolic Architectures…It’s also possible to design a similar circuit without the requirement that all signals will have to arrive simultaneously. This circuit is shown below. This circuit will take longer to process the output. Also, x values will have to be asserted for two clock cycles as opposed to 1. Thus, an input pattern would be x1, x1, x2, x2, x3, x3, …

Aout Ay By CyBout Cout

xin Ax Bx

A B C

w3 = 1 w2 = 0 w1 = 1

YinYout

XoutXin

Wbased on…

w3=1

xin

A

Aout Ay

Ax

w2=0

B

Bout By

Bx

w1=1

C

Cout Cy

Cx



Systolic Processing (and errors)

….

a

b

c

The top part of this figure shows a DNA tile with four schematic QCA molecules attached to specific sites in the major groove of one DNA helix (a). This DNA tile is one of nine tiles which would form a diamond-shaped raft 60 nm long by 12 nm wide. After ligation to prevent disassembly, six of these rafts would assemble (b) into a functional pattern matching circuit in an area of less than 0.01 square microns. Part (c) shows how the DNA circuit board could self-assemble on a surface with buried clocking wires; the wires are about 25 nm in diameter on a 75 nm pitch. This circuit would be capable of matching a specific string of 1s and 0s to an input stream of 1s and 0s – hardware that could be used in internet search engines to locate items in a database, to find an address in a computer’s memory, etc.

w3(1)

xin xout

w2(0)

xin xout

The QCA circuit in terms oflogic gates

Sources of error

d

Possible sources of error in systems of molecular QCA cells. Missing cells (a), wrong distance between cells (b), offcenter cells (c), rotated cells (d), and offcenter cells in the “y”-dimension (e).

a b

c d e



Detailed design rules

2B

ndisordered = # cells

How is disorder affected by Ekink?

Ekink ~ (1/r5)(cos4). As increases, Ekink decreases.

r

ndisordered = # cells Ekink ~ (1/r5)(cos2(1+ 2)). As 1 or 2 increases, Ekink decreases.

2 = 0o1

Rule 2B: Disorder

Why they are important:

• Successful binary value transmission dependent on no external energy greater than the smallest kink energy



Me• Name:

– Michael Niemier (a.k.a. “Mike”)

• Contact:– E-mail: [email protected]– Phone: (404) 894-1704 – My office: 219



End of talk…

What I do.

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