Wed. Aug 23 Announcements - Purdue Engineering · 2017-08-23 · B.Instruction Set Overview ......

Wed.Aug23Announcements

• ProfessorOfficeHours1:30to2:30Wed/Fri• EE326A

• Youshouldallbesignedupforpiazza• Mostlabsdoneindividually(ifnot– calledoutinthedoc)• Makesuretoregisteryourclickeronblackboard• WewillhavesomequestionsFriday– willcountfornothing,butcanyoucanusethemtoverifythateverythingisregistered.

• Reallabsstartnextweek• Intrototools/assembly• StartlookingatHW(someformattingissueswillbefixedtoday)

Module1MicrocontrollerProgrammingTechniques

TimRogers2017

LearningOutcome#1

“Anabilitytoprogramamicrocontrollertoperformvarioustasks”Why?

IoTEmbeddedsystemsincars

LearningOutcome#1

“Anabilitytoprogramamicrocontrollertoperformvarioustasks”

How?

A. ArchitectureandProgrammingModelB. InstructionSetOverviewC. AssemblyControlStructuresD. ControlStructureApplicationsE. TableLookupF. ParameterPassingG. MacrosandStructuredProgramming

WhatmakesaMicrocontroller?

GeneralPurpose Embedded

IBMPower8Microprocessor

FocusonProgrammability

Whole-SystemNon-User-

Programmable

DifferentObjectives

GeneralPurpose Embedded• High-performance• Needtorun“anything”

relativelywell• Lessenergyconstrained• “Limitless”Memory• Silicondevotedto

computeandcaches

• Limitedability• Inexpensive• Limitedmemory• Low-energy• Silicondevotedtomany

peripherals(althoughcorestillconsumesalot)

Characteristicsofgeneral-purposeprocessors• Virtualmemory(PageTables,TLBs)• Deepcachehierarchy• Largenumberofregisters• Hardwarefloatingpoint• DeepPipelines/OutofOrderExec.• ComplexPredictionMechanisms• Multicore

Interruptsmostlygetintheway

TakeECE437!

Characteristicsofembeddedprocessors• Liveanddiebyinterrupts!• Fewregisters(needtoswitchcontextsfast)• Circuitrydevotedtoanalog• Oftenrelyonhand-tunedassemblycode

InstructionSetArchitectures(ISAs)

• Setofoperationsvisibletotheprogrammer• ISAisthecontractbetweentheSWandHW

• Examples:CPU12,x86,PowerPC,ARM,SPARC,etc…

DifferentTypesofISAs

• CISC(ComplexInstructionSetComputer)• RISC(ReducedInstructionSetComputer)• DSPs(DigitalSignalProcessors)

9S12(ECE362)16-bits

ISAdefinesInteractionbetweenprocessorandmemory

??

SomecommonArchitectures

Accumulator

LoadA XAddA YStoreA Z

Reg/Reg

Load R1,XLoad R2,YAdd R3,R1,R2Store R3,Z

How to compute “Z = X + Y”:

9S12(ECE362)

WhyFreescale68HC(s)12??(AKA9S12)

• “Relatively”Simple• Introducesbasicinstructionsetconcepts• Caneasilyanalyzememorybustiming• Actuallyusedintherealworld• Comesfromtheautomotiveindustry

YouDevKit

MicrocontrollerModule

BDMconnector

9S12C32

DockingBoard

Switch/LEDinput/output COM

port

D.C.power

Boot/RunSwitch

Overviewof9S12C32

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Severalthingstonote…..

TheHCS12CPUhasthesamearchitectureandprogrammingmodelastheHC12

Overviewof9S12C32

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The9S12C32modulehas2KofSRAMand32KofFlash(noEEROM)


Overviewof9S12C32

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The48-pinversionofthechiponthismoduledoesnot havePortsA&Bpaddedout

Overviewof9S12C32


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ExternalinterruptpinsareonPortE

Overviewof9S12C32


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Real-timeinterrupt(RTI)module

Overviewof9S12C32


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Analog-to-digital(ATD)convertermodule– inputsareonPortPAD

Overviewof9S12C32


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Timer(TIM)module– I/OonPortT

Overviewof9S12C32


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Pulsewidthmodulator(PWM)–here,I/OsharedwithTIMmoduleonPortT

MODRRregistersettingdetermineswhetherthesePortTpinsaremappedtotheTIMorPWM

Overviewof9S12C32


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Asynchronousserialcommunicationsinterface(SCI)onPortS

Overviewof9S12C32


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Controllerareanetwork(MSCAN)onPortM

Overviewof9S12C32


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Synchronousperipheralinterface(SPI)onPortM

Overviewof9S12C32


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MemoryUses

SRAM(StaticRandomAccessMemory)• Volatile• Variables• Stack• Buffers• TestCode

FlashMemory• Non-Volatile• AppCode• StaticData• Vectors(resetand

interrupts)

9S12C32MemoryMap

firmware(applicationcode)

interruptvectors

testcode,data,variables,stack2K SRAM

(mappable)

30K Flash8000-F7FF

Default(reset)locationis800-FFF

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Overview of 68HC(S)12 Architecture

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ProgrammingModel

7 0 7 0A B

15 0X

15 0Y

15 0SP

15 0PC

D

Accumulators

Index Registers

Stack Pointer

Program Counter

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9S12Registers

8-bits 8-bits

16-bits

Arithmetic/Logic

16-bits

16-bits

16-bits

Pointerstomemory

16-bits

Canaddconstant/registerAuto+/-

PointertotopofstackPSH/PULInstructions

Pointertonextinstruction

ConditionCodeRegister

SS XX H II N Z V C Condition Code Register (CCR)

Carry/Borrow FlagOverflow FlagZero FlagNegative FlagIRQ MaskHalf-CarryXIRQ MaskStop Disable

7 6 5 4 3 2 1 0

ALUConditionCodes• “C”– “carry/borrow” flag(carryoutofthesignpositionforaddition,complement ofcarryoutofsignpositionfor subtraction)• “V”– “overflow”flag(setiftwo’scomplementoverflowhasoccurred)• “Z”– “zero”flag(setifresultofcomputationiszero)• “N”– “negative”flag(mostsignificantbit(sign)ofcomputation)• “H”– “halfcarry”flag(carryoutofthelower4-bits(nibble),onlyvalidafterADD)

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MachineControlConditionCodes• “ I”– “IRQinterruptmask”

Ø“0”– IRQisnotmasked(enabled)Ø“1”– IRQismasked(disabled)

• “X”– “XIRQinterruptmask”Ø“0”– XIRQisnotmasked(enabled)Ø“1”– XIRQismasked(disabled)

• “S”– “STOPinstructiondisable”Ø“0”– STOPinstructionisenabledØ“1”– STOPinstructionisdisabled

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InstructionRepresentation

• Justabunchofbits• Remember?SimpleComputer?

InstructionFormatsandDataTypes

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Length:1Bto6B

opcode(2B)

Opcode(1B)

Opcode(1B)

Post-byte

Offset(2B)– canalsobe

1B

Opcode(1B)

Post-byte

Immediate(2B) – canalsobe

1B

Example

DEX

DAA

ADDAaddr

BRSEToprx16,xysp,msk8,rel8

*Therearedifferentwaystomix/matchthese

InstructionFormatsandDataTypes

• Bit• Byte(8-bit)• Word(16-bit)• DoubleWord(32-bit)• PackedBinaryCodedDecimal• UnsignedFractions

AddressingModes

• Purpose:• Needtoaccessmemory• NeedanADDRESS

ADDAaddr??

255

0

270

69

ValueAddr0

1

2

65535

Valuenotpossible

Memory

AddressingModes• Definition:TheCPUusesanaddressingmode todeterminetheeffectiveaddress ofwhereanoperandisstoredinmemory• Commonlyusedaddressingmodes

Ø“immediate”(dataimmediatelyfollowsopcode,i.e.,ispartoftheinstruction)DOESNOTGOTOMEMORY

Ø“extended /absolute”(absoluteaddressofwhereoperandisstoredinmemory)

Ø“relative”(desiredlocationiscalculatedrelativetothecurrentvalueinthePC)

Ø“indexed”(anindexregisterisusedtopointtotheoperand– manyvariationswithoffset)

Ø“indirect”(theoperandpointerisinmemory)

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IllustrativeInstructions

LDAA addr “load accumulatorA withthecontentsofmemorylocationaddr”

STAA addr “store thecontentsofaccumulatorA atmemorylocationaddr”

addr representstheeffectiveaddress39

LDversusStore

255

0

69

0

1

65535

LDAA1Registers

77

56

A

B

CoreValueAddr

Memory

56

0

Wed. Aug 23 Announcements - Purdue Engineering · 2017-08-23 · B.Instruction Set Overview ......

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