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August 2010 Bachelor of Science in Information Technology (BScIT) – Semester 1/ Diploma in Information Technology (DIT) – Semester 1 BT0064 – Logic Design – 4 Credits (Book ID: B0948) Assignment Set – 1 (60 Marks) Answer all questions 10 x 6 = 60 1. Convert the following octal numbers to base 10. a. 273 b. 1021 Answer: 187 Answer: 529 2. What is a logic gate? Answer:- A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic is called Boolean logic and is most commonly found in digital circuits. Logic gates are primarily implemented electronically using diodes or transistors, but can also be constructed using electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. A truth table is a table that describes the behaviour of a logic gate or any combination of logic gates. It lists the value of the output for every possible combination of the inputs and can be used to simplify the number of logic gates and level of nesting in an electronic circuit. In general the truth table does not lead to an efficient implementation; a minimization procedure, using Karnaugh maps, the Quine–McCluskey algorithm or an heuristic algorithm is required for reducing the circuit complexity. All other types of Boolean logic gates (i.e., AND, OR, NOT, XOR, XNOR) can be created from a suitable network of NAND gates. Similarly all gates can be created from a network of NOR gates. Historically, NAND gates were easier to construct from MOS technology and thus NAND gates served as the first pillar of Boolean logic in electronic computation.

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August 2010Bachelor of Science in Information Technology (BScIT) – Semester 1/

Diploma in Information Technology (DIT) – Semester 1BT0064 – Logic Design – 4 Credits

(Book ID: B0948)Assignment Set – 1 (60 Marks)

Answer all questions 10 x 6 = 601. Convert the following octal numbers to base 10.

a. 273b. 1021

Answer: 187Answer: 5292. What is a logic gate?

Answer:- A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic is called Boolean logic and is most commonly found in digital circuits. Logic gates are primarily implemented electronically using diodes or transistors, but can also be constructed using electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. A truth table is a table that describes the behaviour of a logic gate or any combination of logic gates. It lists the value of the output for every possible combination of the inputs and can be used to simplify the number of logic gates and level of nesting in an electronic circuit. In general the truth table does not lead to an efficient implementation; a minimization procedure, using Karnaugh maps, the Quine–McCluskey algorithm or an heuristic algorithm is required for reducing the circuit complexity.

All other types of Boolean logic gates (i.e., AND, OR, NOT, XOR, XNOR) can be created from a suitable network of NAND gates. Similarly all gates can be created from a network of NOR gates. Historically, NAND gates were easier to construct from MOS technology and thus NAND gates served as the first pillar of Boolean logic in electronic computation.

For an input of 2 variables, there are 16 possible boolean algebraic functions. These 16 functions are enumerated below, together with their outputs for each combination of inputs variables.

3. Minimize the following functions using Quine-McCluskey tabular method:a.b.

(with don’t care terms 2,7,13,22,23)Answer:

a. F =  A'B'C' + B'D + BCD' + AC + ABD'b. F =  ACD + B'CE + A'B'D'E + A'C'D'E' + AB'D'E' + BC'DE + BCE' + ABC'E

4. Design 2-bit comparator using gates.

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Answer:

5. Define Sequential Circuits.

Answer:- Sequential CircuitsWe said that the output of a combinational circuit depends solely upon the input. The implication is that combinational circuits have no memory. In order to build sophisticated digital logic circuits, including computers, we need more a powerful model. We need circuits whose

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output depends upon both the input of the circuit and its previous state. In other words, we need circuits that have memory.

For a device to serve as a memory, it must have three characteristics:

the device must have two stable states there must be a way to read the state of the device there must be a way to set the state at least once.

It is possible to produce circuits with memory using the digital logic gates we've already seen. To do that, we need to introduce the concept of feedback. So far, the logical flow in the circuits we've studied has been from input to output. Such a circuit is called acyclic. Now we will introduce a circuit in which the output is fed back to the input, giving the circuit memory.

(There are other memory technologies that store electric charges or magnetic fields; these do not depend on feedback.)  

The S-R LatchThe output of a NOR gate is true only when both inputs are false. Consider the circuit in Figure 1. The output of each NOR gate is fed back to the input of the other.

This means that if the output of one NOR gate is true, the output of the other must be false. Study the circuit for a moment before you push any buttons and convince yourself that this is the case. The output of the upper NOR gate, is true, or one. This means that one of the inputs of the lower NOR gate, is true and the output of the lower NOR must be false.

For the output neither of the upper NOR to be true, both its inputs have to be false. Examine the circuit and you will see that this is also correct.

Now press the S button. The output of the upper NOR gate, is forced to false, allowing the output of the lower NOR to become true.

Press S again to turn it off. The output of the circuit is unchanged. Examine the circuit to understand why. What has happened is that we have stored the value of S.

Turning S on and off again does not change the output.

With S off, turn R on, then off again. What happens? Why.

Figure 1. The S-R Latch. S sets the latch, causing Q to become true. R resets the latch. 

Figure 1-B. The symbol for the S-R latch.

 

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This circuit is an S-R latch. An S-R latch is also called a set-reset latch. An input on S sets the latch, making true and false. An input on R resets the latch; becomes false and becomes true. The output of the circuit is stable in either state with the inputs removed. We can remove the input that caused a particular output and the output will be unchanged. The state, and so the output, will only change when the complementary input is applied. Such a circuit is said to be bistable because it has two stable states.

The symbol for the S-R latch is shown in Figure 1-B. Whether the output is available depends upon how the latch is packaged and whether an extra pin is available.

The input S=R=1 is not allowed. If both inputs are true, both outputs must be false. This implies = =0, which is logically inconsistent. Further, the circuit is unstable in this state; when one of the inputs returns to the false state, the remaining input determines the stable state and the output changes.

We use the word latch here to mean a circuit that can store one bit. A register that supplies data to the inputs of a combinational circuit is also called a latch; we will encounter this second meaning of the word later.

Note: The circuits above have been drawn with S and at the top to be consistent with Tanenbaum. Most other textbooks place R and at the top. Since the circuit is symmetrical, exchanging the labels makes no difference so long as both the input and output labels are exchanged.  

Timing ConsiderationsBefore we go further, we need to consider what happens when the outputs of two or more gates are combined to form the output of a combinational circuit. We have discussed the fact that the switching time of a transistor is a few nanoseconds, but we haven't emphasized the fact that this switching time causes a finite time delay between a change in the inputs of a gate and any change in the output. This time is called gate delay. So far, we have ignored gate delay, and so do simple circuit simulators.

Figure 2 shows a combinational circuit adapted from [MURD00]; in ordinary circumstances, the three inputs A, B, and C would come from other circuits. We've wired them all to one pushbutton to make a point. If you study the circuit, you will see that the output should be zero or false regardless of the input. If the input is zero, both A and BC will be zero and the XOR gate will produce a zero. If the input is a one, A and BC will be ones, and the

XOR gate will still produce an output of zero or false. Let's look at what happens in reality.

  Figure 2. This circuit can produce a glitch.  

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With all inputs off, the AND gate produces an output of false, both inputs to the XOR gate are false, and the output of the circuit is false. Press the pushbutton and observe carefully what happens. (Cycle from off to on and back a few times if you need to.) The A input to the XOR gate becomes true, and the BC inputs to the AND gate also become true. However, the output of the AND gate remains false for a time equal to one gate delay. The XOR gate has inputs of true-false, and will produce an output of true one gate delay later.

After one gate delay has passed, the output of the AND gate is true and the input of the XOR gate is true-true. However, the output of the XOR gate remains true for one gate delay time. After the second gate delay time, the output of the XOR gate attains the correct value of false. The process reverses itself when the pushbutton is turned off. Experiment with the circuit until you are sure you understand what is happening.

A circumstance where timing dependencies can briefly cause incorrect output is called a hazard. Now consider what would happen if the output of Figure 2 were connected to the S input of an S-R latch. The latch could be set to true when it should not be. Storing an incorrect value in this way is called a glitch.  

ClockingIn order to avoid glitches, we want to design storage elements that only accept input when ordered to so. We will give the order only after the combinational circuits that compute the input to the storage device have had a chance to settle to their correct values. One way to do that is to interpose AND gates between the S and R inputs and the latch circuit. The control signal drives the other input of each AND gate. When the control signal is false, the output of the two AND gates is always low and changes to S and R do not affect the bit stored by the latch.

When the control signal is true, the S and R signals are propagated through the AND gates and the stored value can change.

Because the control input is generally driven by a regular train of pulses, it is often called a clock input.

  Figure 4. A clocked S-R latch. The latch can change only when C is true.  

Figure 4-B. The symbol for the clocked S-R latch.

 

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The circuit of Figure 4 is a clocked S-R latch. With the C input false, experiment with the S and R inputs. Now make the C input true by pressing the button and experiment again with S and R. Note that clocking does not help with the problem of S=R=1. In fact, it makes the problem worse. With S and R both true, turn C on and off several times. You cannot predict whether the latch will store or . When the S and R inputs are removed simultaneously, the

latch settles into one of its two stable states at

The Clocked D-LatchOnce we have applied the idea of clocking to our S-R latch, we can get rid of the problem of what to do with S=R=1 and also simplify the input to our circuit.

Usually what we want to do with a storage device is store one bit of information. The need for explicitly setting and resetting the latch is added complexity.

What we would really like is a circuit that has a data input D and a data output Q. When the clock signal is high, whatever appears on D should be stored in Q.

The circuit of Figure 5 is such a circuit. It has a data input, D, and a control input, C. The data input is connected through an AND gate to the S input of an S-R latch. It is also connected through an inverter and an AND gate to the R input. The other inputs of the two AND gates are connected to the C input of the circuit. If C is false, no signals reach the latch and its state remains unchanged. If C is true and D is true, the S input of the latch is true and the

latch stores a value of true, which is equal to D. If C is true and D is false, the R input of the latch is driven through the inverter and a value of false, which is equal to D, is stored. Experiment with the circuit and observe what happens.

Here is something to think about: The concept of a D latch, where

the bit to be stored is applied to the S input of a latch, and through an inverter to the R input, can only be made to work when the latch is clocked. Why is that?

The clocked D-latch stores whatever is on the D input when C is true. If C is asserted (made true) only after the input circuits have settled, this circuit will

 Figure 5. A clocked D-latch. When C (control) is true, the value at D (data) is stored in Q.

 

Figure 5-B. The symbol for the clocked D latch.

 

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store the correct value of D. Because there is only one data input, the case of S=R=1 cannot occur.

Make C true by operating the pushbutton, then change the value of D and watch what happens. As long as the C input is true, changes to D are reflected in the output of the circuit. The clocked D-latch is a level triggered device. Whether it stores data depends upon level at C.  

Master-Slave Flip-FlopsThe clocked D-latch solves several of the problems of storing output from a combinational circuit, but not all of them. Particularly, if D changes while C is true, the new value of D will appear at the output. Generally this is not what is wanted. If the stored value can change state more than once during a single clock pulse, the result is a hazard that might introduce a glitch later in the circuit. We must design the circuit so that the state can change only once per clock cycle. This can be accomplished by connecting two latches together as shown in Figure 6. The left half of the circuit is the clocked D-latch from the previous section. The right half of the circuit is a clocked S-R latch; however, the clock signal for the output section is the input clock signal inverted. The output of this device can only change once per clock cycle. The change occurs shortly after the falling edge of the clock cycle.

Here's why: Starting with the clock low, the left half of the circuit cannot change state because the inputs are inhibited by the low clock. The AND gates prevent the inputs from reaching the latch. The right half of the circuit could change because it "sees" a high clock, but its inputs come from the latch on the left, and they can't change.

When the clock signal goes high, the D input can change the state of the left latch. One gate delay later, the clock input of the right latch goes low. Since there are at least two gate delays through the D latch that is the left half of the circuit, the right latch cannot change state before its clock signal goes low. With the clock signal high, D can change, and the left latch will change also. However, the output will not change.

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When the clock returns low, the R and S inputs of the output latch will be driven by whatever value is stored by the first latch at that moment. The output of the circuit will change to reflect the value of D at the moment when the clock makes its high-to-low transition. Experiment with the circuit and observe that the output changes at most once per clock cycle.

The output of a master-slave flip-flop can change only at the falling (or rising, if designed that way) edge of the clock pulse. That's why we call it a flip-flop instead of a latch.

Tanenbaum [TANE99] is careful to call level-triggered devices latches and edge-triggered devices flip-flops. Not all authors are as exacting in this distinction.

The symbol for the D flop-flop is shown in Figure 6-B. The triangle at the clock input indicates that this device changes state only on clock transitions. The negation bubble indicates that the change is on the "negative" or falling edge of the clock.

The master-slave flip-flop is an adequate design for a D flip-flop. There are other types of flip-flops, not studied here, for which it doesn't work. The J-K flop-flop, for example, exhibits a phenomenon known as ones-catching in the

master-slave configuration. A spurious one on the input will be latched and propagated to the output even if the input returns to zero before the end of the clock period.  

Edge Triggered DevicesWe could solve the problems of hazards and ones-catching if we could design a memory that would both sample its inputs and store data based on the transition of a clock pulse. If the combinational parts of a circuit could settle during the time the clock signal was true, and the storage part of the circuit sampled the input and saved the result when the clock changed from true to false, we would have no problems with hazards at the output nor with ones catching. A storage circuit like that is called a negative edge-triggered flip-flop. A circuit that stores a result on transition of the clock from false to true is a positive edge-triggered flip-flop.

  Figure 6. A Master-Slave D Flip-Flop. The output of this device does not change until the clock signal goes low.  

Figure 6-B. The symbol for the D flip-flop.

 

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The circuit in Figure 7 is a negative edge-triggered flip-flop. This circuit was adapted from Murdocca [MURD00]. It is effectively three S-R latches. Latch W-X stores D, and latch U-V stores the complement of D. Latch Y-Z prevents the output from changing except on a true-to-false transition of the clock.

Here is how it works: When the clock is true, the S input of latch U-V and the R input of latch W-X are also true. This forces the S and R inputs of latch Y-Z to false, and the circuit cannot change state. When the clock changes from true to false, D appears on the S input of latch Y-Z and the complement of D appears on the R input. Output Q reflects the value of D.

When the clock is false, one of the inputs to Y-Z is true and the other is false. Latches U-V and W-X are stable in this state regardless of changes in D. Latch Y-Z, and therefore the output of the circuit, can only change on the true-to-false clock transition.

Let's examine the assertion that the latches U-V and W-X are stable when the clock is low. At the falling edge of the clock, either Y's R must be true or Z's S, but not both. Consider the case that Y's R is true. This means V's inputs must both be false. That the clock is false is given. V's other input comes from U; U's lower input comes from V and is true from the assumption that Y's R is true. Therefore, U's output must be zero and the output of latch U-V is stable regardless of changes in D.

The alternative assumption is that Z's S is true, meaning that the ouptut of W is true. All three of W's inputs must be false. Clock is false by assumption.The upper input of W is false given the assumption that the output of V is false. If the output of W is true, the upper input of X is true, the output of X is false, and the lower input of W is false. The output of W is stable when the clock is low regardless of changes in D.

By experimenting with the circuit, verify that changing D has no effect on the output regardless of whether the clock is high or low. The output changes to reflect the current state of D only when the clock changes from high to low.

6. Give any two applications of shift register.

  Figure 7. This circuit is triggered by the falling edge of the clock.  

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Answer:- A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It is different in that it makes all the internal stages available as outputs. Therefore, a serial-in/parallel-out shift register converts data from serial format to parallel format. If four data bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes available simultaneously on the four Outputs QA to QD after the fourth clock pulse.

The practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires. Perhaps, we will illuminate four LEDs (Light Emitting Diodes) with the four outputs (QA QB QC QD ).

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The above details of the serial-in/parallel-out shift register are fairly simple. It looks like a serial-in/ serial-out shift register with taps added to each stage output. Serial data shifts in at SI (Serial Input). After a number of clocks equal to the number of stages, the first data bit in appears at SO (QD) in the above figure. In general, there is no SO pin. The last stage (QD

above) serves as SO and is cascaded to the next package if it exists.

7. Explain the working principle of 4 bit Johnson counter with a neat diagram.

Answer:- In the 4-bit counter to the right, we are using edge-triggered master-slave flip-flops similar to those in the Sequential portion of these pages. The output of each flip-flop changes state on the falling edge (1-to-0 transistion) of the T input.

The count held by this counter is read in the reverse order from the order in which the flip-flops are triggered. Thus, output D is the high order of the count, while output A is the low order. The binary count held by the counter is then DCBA, and runs from 0000 (decimal 0) to 1111 (decimal 15). The next clock pulse will cause the counter to try to increment to 10000 (decimal 16). However, that 1 bit is not held by any flip-flop and is therefore lost. As a result, the counter actually reverts to 0000, and the count begins again.

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In future pages on counters, we will use a different input scheme, as shown to the left. Instead of changing the state of the input clock with each click, you will send one complete clock pulse to the counter when you click the input button. The button image will reflect the state of the clock pulse, and the counter image will be updated at the end of the pulse. For a clear view without taking excessive time, each clock pulse has a duration or pulse width of 300 ms (0.3 second). The demonstration system will ignore any clicks that occur within the duration of the pulse.

A major problem with the counters shown on this page is that the individual flip-flops do not all change state at the same time. Rather, each flip-flop is used to trigger the next one in the series. Thus, in switching from all 1s (count = 15) to all 0s (count wraps back to 0), we don't see a smooth transition. Instead, output A falls first, changing the apparent count to 14. This triggers output B to fall, changing the apparent count to 12. This in turn triggers output C, which leaves a count of 8 while triggering output D to fall. This last action finally leaves us with the correct output count of zero. We say that the change of state "ripples" through the counter from one flip-flop to the next. Therefore, this circuit is known as a "ripple counter."

This causes no problem if the output is only to be read by human eyes; the ripple effect is too fast for us to see it. However, if the count is to be used as a selector by other digital circuits (such as a multiplexer or demultiplexer), the ripple effect can easily allow signals to get mixed together in an undesirable fashion. To prevent this, we need to devise a method of causing all of the flip-flops to change state at the same moment. That would be known as a "synchronous counter" because the flip-flops would be synchronized to operate in unison. That is the subject of the next page in this series.

8. Explain temperature and weather forecast system with a neat circuit diagram.Answer:-

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9. Explain the functioning of digital multimeter.

Answer:- Digital multimeters

Multimeters are designed and mass produced for electronics engineers. Even the simplest and cheapest types may include features which you are not likely to use. Digital meters give an output in numbers, usually on a liquid crystal display.

The diagram below shows a switched range multimeter:

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Switched range multimeter

The central knob has lots of positions and you must choose which one is appropriate for the measurement you want to make. If the meter is switched to 20 V DC, for example, then 20 V is the maximum voltage which can be measured, This is sometimes called 20 V fsd, where fsd is short for full scale deflection.

For circuits with power supplies of up to 20 V, which includes all the circuits you are likely to

build, the 20 V DC voltage range is the most useful. DC ranges are indicated by on the meter. Sometimes, you will want to measure smaller voltages, and in this case, the 2 V or 200 mV ranges are used.

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What does DC mean? DC means direct current. In any circuit which operates from a steady voltage source, such as a battery, current flow is always in the same direction. Every constructional project descirbed in Design Electronics works in this way.

AC means alternating current. In an electric lamp connected to the domestic mains electricity, current flows first one way, then the other. That is, the current reverses, or alternates, in direction. With UK mains, the current reverses 50 times per second.

10. Write a short note on ADC.

Answer:- An analog-to-digital converter is an electronic integrated circuit, which converters continuous signals to discrete digital numbers. The reverse operation is performed by a digital-to-analog converter.Typically, an adc is an electronic device that converter an input analog voltage to a digital number. The digital output may be using different coding schemes, such as binary, gray code or two’s complement binary. However, some non electronic or only partiay electronic devices, such as rotary encoders, can also be considered ADCs.Resolution can also be defined electrically, and expressed in volts. The voltage resolution of an ADC is equal to it’s over all voltage measurement range divided by the number of discrete intervals as in the formula:Q = EFSR = EFSR 2M NWhere:Q is resolution in volts per step (volts per output code),EFSR is the fu scale voltage = VRefHi – Vreflo and M is the ADC’s resolution in bits.The number of intervals is given by the number of available levels (output code), Which is: N = 2M Some example may help:Example 1:Full scale measurement range = 0 to 10 voltsADC resolution is 12 bits: 212 = 4096 quantization level (codes)ADC voltage resolution is: (10V – 0V) / 4096 codes = 10V / 4096 codes 0.00244 volts/code 2.44 mV/code.

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August 2010Bachelor of Science in Information Technology (BScIT) – Semester 1/

Diploma in Information Technology (DIT) – Semester 1BT0064 – Logic Design – 4 Credits

(Book ID: B0948)Assignment Set – 2 (60 Marks)

Answer all questions 10 x 6 = 601. Convert the following hexadecimal numbers to base 10:

a. 145b. A2C1

Answer:- 145A2C1(Hex) = 21340865 (10).2. What are universal gates? Why they are called so?Answer: The NAND gate is a digital gate that behaves in a manner that corresponds to the truth table to the left. A low output result only if both the inputs to the gat are HIGH. If one or both inputs are low, a HIGH output result the nand gate is a universal gate in the sense that any Boolean function can be implemented by nand gates.Digital system employing certain logic circuits takes advantage of NAND’s functional completeness. In complicated logical expressions, normally written in terms of other logic functions such as AND, OR, and NOT, writing these in terms of NAND saves on cost, because implementing such circuits using NAND gate yields a more compact result than the alternatives.NAND gates can also be made with more than two inputs, yielding an output of low if all of the inputs are HIGH, and an output of HIGH if any of the inputs is low. These kinds of gates therefore operate as n-ary operators instead of a simple binary operator. Algebraically, these can be expressed as the function NAND (a, b,…….., n), which is logically equivalent to NOT (a AND b AND … AND n). There are two symbols for NAND gates: the ‘distinctive’ symbols and the ‘rectangular’ symbol. So they are called universal gate. 3. Expand the following Boolean functions into their canonical form:

a.b.

4. Implement a 8:1 MUX using 4:1 MUX.Answer:- Function Implementation using an 8:1 MuxThe MUX inputs can be read directly from the truth table.

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Function Implementation using a 4:1 MuxImplement the same function below using a 4:1 MUX + an inverter. By manipulating the truth table, we can write F = 0, 1, C, and NOT C in a four-row truth table. Then, we can use a 4:1 MUX and a single inverter to implement the function

5. Draw and explain the working of JK, S-R, and D flip flops.Answer:- Each flip-flop stores a single bit of data, which is emitted through the Q output on the east side. Normally, the value can be controlled via the inputs to the west side. In particular, the value changes when the clock input, marked by a triangle on each flip-flop, rises from 0 to 1; on this rising edge, the value changes according to the corresponding table below.

D Flip-Flop J-K Flip-Flop S-R Flip-FlopD Q0 01 1

J K Q0 0 Q0 1 01 0 11 1 Q'

S R Q0 0 Q0 1 01 0 11 1 ??

Another way of describing the different behavior of the flip-flops is in English text.

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D Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop becomes the value of the D input (Data) at that instant.

J-K Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop toggles if the J and K inputs are both 1, remains the same if they are both 0, and changes to the K input value if J and K are not equal. (The names J and K do not stand for anything.)

R-S Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop remains unchanged if R and S are both 0, becomes 0 if the R input (Reset) is 1, and becomes 1 if the S input (Set) is 1. The behavior in unspecified if both inputs are 1. (In Logisim, the value in the flip-flop remains unchanged.)

6. Draw and explain the operation of 4-bit serial-in parallel-out shift register.Answer: For this kind of register, data bits are entered serially in the same manner as discussed in the last section. The difference is the way in which the data bits are taken out of the register. Once the data are stored, each bit appears on its respective output line, and all bits are available simultaneously. A construction of a four-bit serial in - parallel out register is shown below.

A 4-bit serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It is different in that it makes all the internal stages available as outputs. Therefore, a serial-in/parallel-out shift register converts data from serial format to parallel format. If four data bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes available simultaneously on the four Outputs QA to QD after the fourth clock pulse.

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The practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires. Perhaps, we will illuminate four LEDs (Light Emitting Diodes) with the four outputs (QA QB QC QD ).

7. Explain the working of 8-bit ring counter. Draw the timing diagram.

Answer: Let's take a closer look at Serial-in/ parallel-out shift registers available as integrated circuits, courtesy of Texas Instruments. For complete device data sheets follow the links.

SN74ALS164A serial-in/ parallel-out 8-bit shift register SN74AHC594 serial-in/ parallel-out 8-bit shift register with output register SN74AHC595 serial-in/ parallel-out 8-bit shift register with output register CD4094 serial-in/ parallel-out 8-bit shift register with output register

A real-world application of the serial-in/ parallel-out shift register is to output data from a microprocessor to a remote panel indicator. Or, another remote output device which accepts serial format data.

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The figure "Alarm with remote key pad" is repeated here from the parallel-in/ serial-out section with the addition of the remote display. Thus, we can display, for example, the status of the alarm loops connected to the main alarm box. If the Alarm detects an open window, it can send serial data to the remote display to let us know. Both the keypad and the display would likely be contained within the same remote enclosure, separate from the main alarm box. However, we will only look at the display panel in this section.

If the display were on the same board as the Alarm, we could just run eight wires to the eight LEDs along with two wires for power and ground. These eight wires are much less desirable on a long run to a remote panel. Using shift registers, we only need to run five wires- clock, serial data, a strobe, power, and ground. If the panel were just a few inches away from the main board, it might still be desirable to cut down on the number of wires in a connecting cable to improve reliability. Also, we sometimes use up most of the available pins on a microprocessor and need to use serial techniques to expand the number of outputs. Some integrated circuit output devices, such as Digital to Analog converters contain serial-in/ parallel-out shift registers to receive data from microprocessors. The techniques illustrated here are applicable to those parts.

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8. Explain traffic light signaling with a neat circuit diagram.Answer: Traffic Signal Systems

This automated traffic signal controller can be made by suitably programming a GAL device. Its main features are:

1. The controller assumes equal traffic density on all the roads.

2. In most automated traffic signals the free left-turn condition is provided throughout the entire signal period, which poses difficulties to the pedestrians in crossing the road, especially when the traffic density is high. This controller allows the pedestrians to safely cross the road during certain periods.

3. The controller uses digital logic, which can be easily implemented by using logic gates.

4. The controller is a generalized one and can be used for different roads with slight modification.

5. The control can also be exercised manually when desired.

The time period for which green, yellow, and red traffic signals remain ‘on’ (and then repeat) for the straight moving traffic is divided into eight units of 8 seconds (or multiples thereof) each. Fig.1 shows the flow of traffic in all permissible directions during the eight time units of 8 seconds each. For the left- and right turning traffic

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and pedestrians crossing from north to south, south to north, east to west, and west to east, only green and red signals are used.

Table I shows the simultaneous states of the signals for all the traffic. Each row represents the status of a signal for 8 seconds. As can be observed from the table, the ratio of green, yellow, and red signals is 16:8:40 (=2:1:5) for the straight moving traffic. For the turning traffic the ratio of green and red signals is 8:56 (=1:7), while for pedestrians crossing the road the ratio of green and red signals is 16:48 (=2:6).

In Table II (as well as Table I) X, Y, and Z are used as binary variables to depict the eight states of 8 seconds each. Letters A through H indicate the left and right halves of the roads in four directions as shown in Fig. 1. Two letters with a dash in between indicate the direction of permissible movement from a road. Straight direction is indicated by St, while left and right turns are indicated by Lt and Rt, respectively.

The Boolean functions for all the signal conditions are shown in Table II.

The left- and the right-turn signals for the traffic have the same state, i.e. both are red or green for the same duration, so their Boolean functions are identical and they should be connected to the same control output.

The circuit diagram for realizing these Boolean functions is shown in Fig. 2.

Timer 555 (IC1) is wired as an a stable multivibrator to generate clock signal for the 4-bit counter 74160 (IC2). The time duration of IC1 can be adjusted by varying the value of resistor R1, resistor R2, or capacitor C2 of the clock circuit. The ‘on’ time duration T is given by the following relationship:

T = 0.695C2(R1+R2)

IC2 is wired as a 3-bit binary counter by connecting its Q3 output to reset pin 1 via inverter N1. Binary outputs Q2, Q1, and Q0 form variables X, Y, and Z, respectively.

These outputs, along with their complimentary outputs X’, Y’, and Z’, respectively, are used as inputs to the rest of the logic circuit to realize various outputs satisfying Table I.

You can simulate various traffic lights using green, yellow, and red LEDs and feed the outputs of the circuit to respective

LEDs via current-limiting resistors of 470 ohms each to check the working of the circuit. Here, for turning traffic and pedestrians crossing the road, only green signal is made available. It means that for the remaining period these signals have to be treated as ‘red’. In practice, the outputs of Fig. 2 should be connected to solid state relays to operate high-power bulbs.

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Further, if a particular signal condition (such as turning signal) is not applicable to a given road, the output of that signal condition should be connected to green signal of the next state (refer Table I).

The traffic signals can also be controlled manually, if desired. Any signal state can be established by entering the binary value corresponding to that particular state into the parallel input pins of the 3-bit counter. Similarly, the signal can be reset at any time by providing logic 0 at the reset pin (pin 1) of the counter using an external switch. A software program to verify the functioning of the circuit using a PC is given below. When executing the program, keep pressing Enter key to get the next row of results. The test results on execution of the program are shown in Table III.

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9. Write a short note on Digital Versatile Disk.

Answer: DVD, also known as Digital Video Disc or Digital Versatile Disc, is an optical disc storage media format, and was invented and developed by Philips, Sony, Toshiba, and Time Warner in 1995. Its main uses are video and data storage. DVDs are of the same dimensions as compact discs (CDs), but are capable of storing almost seven times as much data.

Variations of the term DVD often indicate the way data is stored on the discs: DVD-ROM (read only memory) has data that can only be read and not written; DVD-R and DVD+R (recordable) can record data only once, and then function as a DVD-ROM; DVD-RW (re-writable), DVD+RW, and DVD-RAM (random access memory) can all record and erase data multiple times. The wavelength used by standard DVD lasers is 650 nm;[4] thus, the light has a red color.

DVD-Video and DVD-Audio discs refer to properly formatted and structured video and audio content, respectively. Other types of DVDs, including those with video content, may be referred to as DVD Data discs.

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In 1993, two optical disc storage formats were being developed. One was the MultiMedia Compact Disc (MMCD) also called CDi, backed by Philips and Sony, and the other was the Super Density (SD) disc, supported by Toshiba, Time Warner, Matsushita Electric, Hitachi, Mitsubishi Electric, Pioneer, Thomson, and JVC.

Representatives of the SD camp approached IBM, asking for advice on the file system to use for their disc as well as seeking support for their format for storing computer data. Alan E. Bell, a researcher from IBM's Almaden Research Center received that request and also learned of the MMCD development project. Wary of being caught in a repeat of the costly videotape format war between VHS and Betamax in the 1980s, he convened a group of computer industry experts, including representatives from Apple, Microsoft, Sun, Dell, and many others. This group was referred to as the Technical Working Group, or TWG.

The TWG voted to boycott both formats unless the two camps agreed on a single, converged standard. Lou Gerstner, president of IBM, was recruited to apply pressure on the executives of the warring factions. Eventually, the computer companies won the day, and a single format, now called DVD, was agreed upon. The TWG also collaborated with the Optical Storage Technology Association (OSTA) on the use of their implementation of the ISO-13346 file system (known as Universal Disc Format [UDF]) for use on the new DVDs.

Philips and Sony decided it was in their best interest to avoid another format war over their MultiMedia Compact Disc, and agreed to unify with companies backing the Super Density Disc to release a single format with technologies from both. The specification was mostly similar to Toshiba and Matsushita's Super Density Disc, except for the dual-layer option (MMCD was single-sided and optionally dual-layer, whereas SD was single-layer but optionally double-sided) and EFMPlus modulation.

EFMPlus was chosen because of its great resilience to disc damage, such as scratches and fingerprints. EFMPlus, created by Kees Immink (who also designed EFM), is 6% less efficient than the modulation technique originally used by Toshiba, which resulted in a capacity of 4.7 GB, as opposed to the original 5 GB. The result was the DVD specification, finalized for the DVD movie player and DVD-ROM computer applications in December 1995.

The DVD Video format was first introduced by Toshiba in Japan in November 1996, in the United States in March 1997 (test marketed), in Europe in October 1998, and in Australia in February 1999.

In May 1997, the DVD Consortium was replaced by the DVD Forum, which is open to all other companies. DVD specifications created and updated by the DVD Forum are published as so-called DVD Books (e.g

10. Explain practical concepts and applications of DAC.

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Answer: In electronics, a digital-to-analog converter (DAC or D-to-A) is a device that converts a digital (usually binary) code to an analog signal (current, voltage, or electric charge). An analog-to-digital converter (ADC) performs the reverse operation.

nstead of impulses, usually the sequence of numbers update the analogue voltage at uniform sampling intervals.

These numbers are written to the DAC, typically with a clock signal that causes each number to be latched in sequence, at which time the DAC output voltage changes rapidly from the previous value to the value represented by the currently latched number. The effect of this is that the output voltage is held in time at the current value until the next input number is latched resulting in a piecewise constant or 'staircase' shaped output. This is equivalent to a zero-order hold operation and has an effect on the frequency response of the reconstructed signal.

Piecewise constant output of a conventional practical DAC.

The fact that practical DACs output a sequence of piecewise constant values or rectangular pulses would cause multiple harmonics above the Nyquist frequency. These are typically removed with a low pass filter acting as a reconstruction filter.

However, this filter means that there is an inherent effect of the zero-order hold on the effective frequency response of the DAC resulting in a mild roll-off of gain at the higher frequencies (often a 3.9224 dB loss at the Nyquist frequency) and depending on the filter, phase distortion. Not all DACs have a zero order response however. This high-frequency roll-off is the output characteristic of the DAC, and is not an inherent property of the sampled data.

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A simplified functional diagram of an 8-bit DAC

Some vocabulary

DAC: Digital to Analog converter

D0, D1, D..: Data lines

Analog: Continuous electrical signals

Digital: Method of representing information using "1" and "0" (usually 5v and 0V)

LSB: Least significant bit.

MSB: Most significant bi

Applications

Audio

Most modern audio signals are stored in digital form (for example MP3s and CDs) and in order to be heard through speakers they must be converted into an analog signal. DACs are therefore found in CD players, digital music players, and PC sound cards.

Specialist standalone DACs can also be found in high-end hi-fi systems. These normally take the digital output of a CD player (or dedicated transport) and convert the signal into a line-level output that can then be fed into a pre-amplifier stage.

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Similar digital-to-analog converters can be found in digital speakers such as USB speakers, and in sound cards.

VOIP (Voice over IP) Phone, Data transmission over the Internet is done digitally so in order for voice to be transmitted it must be converted to digital using an Analog-to-Digital_Converter and be converted into analog again using a DAC so the voice it can be heard on the other end.

Video

Video signals from a digital source, such as a computer, must be converted to analog form if they are to be displayed on an analog monitor. As of 2007, analog inputs are more commonly used than digital, but this may change as flat panel displays with DVI and/or HDMI connections become more widespread. A video DAC is, however, incorporated in any digital video player with analog outputs. The DAC is usually integrated with some memory (RAM), which contains conversion tables for gamma correction, contrast and brightness, to make a device called a RAMDAC.

A device that is distantly related to the DAC is the digitally controlled potentiometer, used to control an analog signal digitally.