Washington WASHINGTON UNIVERSITY IN ST LOUIS 1 DTI Visit - John DeHart- 4/25/2001 Agenda l WU/ARL...

WashingtonWASHINGTON UNIVERSITY IN ST LOUIS

1DTI Visit - John DeHart- 4/25/2001

Agenda

WU/ARL Background – John DeHart (15 minutes)

DTI Background – DTI (15 minutes)

Block Diagram of SPC II – Dave Richard (20 minutes)

Review of DTI Proposal – DTI (20 minutes)

Q & A – Tom Chaney, Dave Richard, … (20 minutes)

DTI Visit - John DeHart – 4/25/2001


2

Washington UniversityApplied Research Laboratory

and theWU Active Router

John DeHart

Washington University, Applied Research Labhttp://www.arl.wustl.edu/arl/



Applied Research LaboratoryCurrent Staff

»2 Full time faculty»1 Research faculty»3 Part time faculty»10 Full time staff»About 20 students

Current Projects»WUGS 160»Burst Switch»Multi-Service Router»Active Network Node»Network Monitoring Visualization and Control»Gigabit Network Technology Distribution Program»…

• Licensed Technology» ATM Switch (SynOptics)» MMX (STS: local startup)» ATM Software (3-4 companies)

» ATM Circuits/Designs (GNI)» …



Switch Fabric

IPP

OP

P

SPC

TI

IPP

OP

P

SPC

TI

IPP

OP

P

SPC

TIIP

P

OP

P

SPC

TI

IPP

OP

P

SPC

TI

IPP

OP

PSPC

TI

ControlProcessor

Input Port Processor

VCI VCI OUT

Control Processor

• global coordination & control

• routing protocols

• build routing tables and other information needed by SPCsand FPXs

• first level code server

Washington University Active Router

Smart Port Card

Sys.FPGA

64MB

Pentium

Cache

NorthBridge APIC



Switch Fabric

IPP

OP

P

SPC

TI

IPP

OP

P

SPC

TI

IPP

OP

P

SPC

TIIP

P

OP

P

SPC

TI

IPP

OP

P

SPC

TI

IPP

OP

PSPC

TI

ControlProcessor

Cell Processing

3 6

6 5

Input Port Processor

3 6 5



Switch Fabric

IPP

OP

P

SPC

TI

IPP

OP

P

SPC

TI

IPP

OP

P

SPC

TIIP

P

OP

P

SPC

TI

IPP

OP

P

SPC

TI

IPP

OP

PSPC

TI

ControlProcessor

Active Packet Processing

333 666

Smart Port CardSys.FPGA

32-64MB

Pentium

Cache

NorthBridge APIC

6 56 5 6 5



Principal Data Flows Through SPC Kernel

PacketClassificationand Routing

Dri

ver

IPv4/6Header

Processing

Packet +Flow Id

Pac

ket

Sche

dule

r

ActiveFunction

Dispatcher

IP Packets

Dri

ver

Active Packets

Plain Packets

Kernel Plugins

. . .

. . .. . .

Standard processing for “plain” IP packets.»classification and routing, header processing, output queueing

Active packets move through configured kernel plugins.»active function dispatcher passes packets to instances of plugin objects» instantiates objects or triggers download of plugin class, as needed

HWInterruptContext

HWInterruptContext

SWInterruptContext



Throughput (Forward)

0

5000

10000

15000

20000

25000

30000

35000

44 332

620

908

1196

1484

1772

2060

2348

2636

2924

3212

3500

3788

4076

4364

4652

4940

5228

5516

5804

6092

6380

6668

6956

7244

7532

7820

8108

packet size

pac

kets

per

sec

on

d

SPC

450 MHz PII



MSR: h Phase 1.0

SW Interrupt

Exa

ct M

atch

C

lass

ifie

r

AP

ICin

terr

up

t

AN Framework

X.1

Y.1

Z.1

W.1

IP options

X.2 Y.1Z.2

...O

utp

ut 1

Ou

tpu

t 2

Ou

tpu

t N

APIC

Nex

t HopH M LH M LH M L

User

Kernel

akintr

Manage Queues and Memory

AN

N K

ern

elS

W I

nte

rru

pt

Default Input port path

...

Input 1

Input 2

Input N

Prev Hop

HM

LH

ML

HM

L

Packet schedulers

PS

1

PS

2

PS

N

PS

out ...

DefaultOutput pathto Next Hop

To

CP

Bas

ic I

P P

roce

ssin

g(T

TL

, ver

sion

, add

r,

opti

ons

chk)

SPC

APIC Driver

Standard IP ProcessingActive Processing



Input Port Forwarding Rate

0

50

100

150

200

250

0 50 100 150 200 250 300

Input Rate (Kpps)

Fo

rwar

ded

Rat

e (K

pp

s)

600 MHz PIII

200 MHz PPro

Packet size == 1 Cell



Switch Fabric

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TIIP

P

OP

P

FPX

SPC

TI

IPP

OP

PFPX

SPC

TI

ControlProcessor

Hardware Support for Active Routing

Smart Port Card

Sys.FPGA

64MB

Pentium

Cache

NorthBridge APIC

Field Programmable Port Ext.

NetworkInterfaceDevice

ReprogrammableApplication

Device

SDRAM128 MB

SRAM4 MB



Switch Fabric

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

PFPX

SPC

TI

ControlProcessor

“Vanilla” IP Packet Processing

333


NIDRAD

6 56 5 6 5


NIDRAD

666



Switch Fabric

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

P

FPX

SPC

TI

IPP

OP

PFPX

SPC

TI

ControlProcessor

Active Packet Processing

333 666

Smart Port CardSys.FPGA

32-64MB

Pentium

Cache

NorthBridge APIC

6 56 5 6 5


NIDRAD



Sample Applications

Application Specific Congestion Control»Video: dropping high frequency portions of image first»Application specific»Small fixed portion of payload gets processed

Reserved Flow Setup»Low overhead soft-state bandwidth reservations»Application independent»Header processing only

Networked Vision»Image processing in the network, close to the camera»Application specific»Possibly full payload processing



Active Congestion Control for Video

Based on wavelet-based encoding method (WaveVideo)» up to hundreds of distinct frequency subbands (33)» low frequencies: general image definition» high frequencies: image details

Active WaveVideo plugin» detects congestion» discards packets in high frequency subbands first

Better performance than layered multicast» requires large number of multicast groups» reacts too slowly to congestion ( several seconds)



WaveVideo Scaling

33011 bytes (33) 25239 bytes (30) 17179 bytes (27) 9265 bytes (24)



Washington WASHINGTON UNIVERSITY IN ST LOUIS 1 DTI Visit - John DeHart- 4/25/2001 Agenda l WU/ARL...

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Transcript of Washington WASHINGTON UNIVERSITY IN ST LOUIS 1 DTI Visit - John DeHart- 4/25/2001 Agenda l WU/ARL...