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October 199814 EJ

The War on NoiseNew tools are needed to attack the noise problem in deep-submicron design

by

Robert

Patton

I C D A T E C H N O L O G YElectronics

Journal

Though noise has posed aproblem for analog cir-cuit designers ever since

the early days of crystal radios,designers of digital integrated cir-cuits have never had to worryuntil now. One big advantage ofdigital circuits, after all, is a highdegree of noise immunity. Not

only has that changed, but theproblem of noise has assumedsuch importance that some indus-try experts believe that electricaleffects such as noise, not the limitsof optical lithography, will posethe earliest threat to continuedgrowth in circuit density andperformance.

Ken Shepard, who has a footon each coast as both an assistantprofessor in the EE department

of New Yorks Columbia Univer-sity and the chief technologyofficer of CadMOS Design Tech-nology in San Jose, is working tosolve that problem. Digital cir-cuits are very noisy, he says,because, within the chip, certainvoltage values are going from highto lowfrom Vdd to groundthen switching back up again,from ground to Vdd.

Until recently the noise

immunity [of digital circuits] hasbeen more than enough to over-

come the noisiness and the onlydesigners who had a problem[with digital noise] were thosewho tried to mix digital and ana-log, who took the noisy digitalenvironment and inserted verynoise-sensitive analog circuits.Now, with technology scaling,with the jamming together of

interconnect wires, with the scal-ing of threshold voltages, with themore aggressive use of circuitsthat are more noise sensitive togain performance advantages,the noise immunity of digitalcircuits is no longer sufficient toprotect them against their [own]inherent noisiness.

Noisy Neighbors

Noise has become a problem

because as design rules reach the0.25-m level and below, inter-connect is becoming an increas-ingly dominant factor in design.Technology scaling has causedcoupling capacitance betweenon-chip signals to become a largerand larger fraction of total capac-itance. At the same time, becausetransistors are shrinking and thenumber of long interconnects areincreasing, the amount of inter-

connect-related capacitance isbecoming much larger and more

significant than the amount ofcapacitance in gates.

As circuit densities continueto increase, interconnect capaci-tance will continue to be a grow-ing fraction of the total capaci-tance of advanced devices. Moreand more, the improbable andunanticipated has become an

everyday and expected part of thedesign job. Problems once asso-ciated only with interconnectionsbetween devices on a board arenow invading chips themselves.And the microscopic metallicslivers that interconnect deviceson the chip are now, almostunbelievably, behaving liketransmission lines.

John MacDonald, a staff engi-neer working on UltraSPARC

development at Sun Microsys-tems, Inc. of Palo Alto, CA, pointsto the dramatic change that hasoccurred in the way metal linesbehave. If you backed up a cou-ple of generations, he explains,and took a cross-section of themetal layer, you would find that ametal line was wider than it wasthick. And the typical separationbetween different metal layers wasless than the width of a metal line.

So most of the capacitance wasbetween metal layers. Since then,he continues,lateral dimensionshave scaled more rapidly thanvertical dimensions. So now if youtake a cross-section, the metallines look more like two-by-foursstanding on edge.

MacDonalds graphic meta-phor emphasizes the dramaticchange in circuit aspect ratiothe shrinking width of intercon-

nects with respect to height. In

In the latest submicron designs, both line width and line

spacing are less than line thickness, and are even less than the

separation between lines on different layers. As a result, line-

to-line capacitance on the same layer has become dominant.

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A1B1C1

O1O2

A1

A1 B1 C1

O1 O2

B1

A2

A2 B2

n1

B2

C1

Charge sharing betweennodes O1 and n1in thepresence of other noisesources can lead tofunctional failures at adownstream latch

Charge-sharingnoise at node Dcauses node Lto change state

Static Logic Gate

Dynamic Logic Gate

CLK

CLK

S1, S2, S3, S4

D

O

LCLK

CLK

CLK

CLK

D O

LS2 S3 S4S1

D2 D3 D4D1

Capacitive coupling and charge sharing can move

a gate voltage beyond a threshold, causing that

gate to make and unwanted transition. (Source:

CadMOS)

Figure 1

Charge Sharing

addition to this, lines are alsomuch closer together. In the latestsubmicron designs, both linewidth and line spacing are lessthan line thickness, and are evenless than the separation betweenlines on different layers. As aresult, line-to-line capacitanceon the same layer has become

dominant.When layer-to-layer capaci-tance was the dominant factor,signals would rarely interact in away that induced current into ametal line. But now that line-to-line capacitance is greater, it iscommon to find problems createdby unwanted coupling betweenindividual signals where one lineacts as an aggressor, inducingenough current into an adjacent

victimline to cause a functionalfailure by destroying logical infor-mation and causing a latch tostore an incorrect machine state.One way to decrease line-to-linecoupling is to increase spacing.Another is to reduce the crosstalkcapacitance between wires byaltering the routing pattern. Alonger-term solution might uselower-dielectric-constant materi-als between troublesome lines.

This kind of coupling-inducednoise problem is probably themost significant noise issue indeep-submicron design, but it isnot the only one. Noise can alsoaffect switching circuits by alter-ing delay and causing timinginaccuracy. If an aggressor lineinduces current into a victimwhile the victim line is changingstates, the extra current can helpor hinder the change, thus alter-

ing the timing. This introducesan unexpected parameter.

Instead of the delay and timingdepending only on load, drive,and the characteristics of theinterconnect, designers mustnow concern themselves withwhat is happening elsewhere inthe neighborhood.

Turning Down the Volume

Any solution to these problemsmust deal with noise from anumber of sources. In additionto noise coupled between metallines on the interconnect, noisecan move from a switching lineto a static one, or even originatein the power supply. From a toolperspective, says Shepard, theproblem is to verify functionalityin the presence of the noise. Hecites two basic approaches.

The first, he explains, is rule-based. You set up rules in yourdesign. Rules about data ratios,circuit rules, rules about inter-connects. You come up with a setof rules which, if followed, willhopefully avoid a problem.

But Shepard sees major draw-backs to rule-based approaches.No rule set is likely to cover allcases and catch everything. Even ifit could, the rule-based approach

is inherently conservative.Noise,he argues,is always trading offagainst performance, against area,against power. Whenever you tryto get more noise immunity inyour design, it always costs some-thing. If not performance, thenarea, or power, or something. Itsnever free. Building more noiseimmunity into designs throughconservative rules, he concludes,is inevitably going to hamstring

your ability to optimize othermetrics in the design.

The second approach, whichgoes beyond rule checking, is todo static noise analysis. Staticnoise analysis is to noise whatstatic timing analysis is to timing.

Static noise analysis asks whethera design will function in thepresence of noise. It actually cal-culates the noise appearing onevery net and, in the worst-casescenario, how much noise canappear on the net. At the sametime it evaluates the noise immu-nity of every net, flagging thoseplaces where there are potentialfailures. Static noise analysisinvolves looking at the circuits,

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looking at the interconnects, andanalyzing the [entire] designwith much the same sort of rigorapplied to static timing analysis.

This technique underlies thetools now under development atCadMOS, which was co-foundedby Shepard. The fledgling com-pany, which launched last sum-

mer and only formally announcedits formation in May of this year,is now building both its initialproduct line and marketingstrategy solely on its approach tosolving the growing problem ofcombating noise effects in thedesign of advanced circuits.Although CadMOS has not yet

released a commercial product, itis now beta testing its first designtool, PacifIC, a static noise ana-lyzer for large digital ICs.

Noise at the Head Office

The noise problem is particularlyvexing to designers of advancedmicroprocessors, because they are,

by necessity, the first to break newground and because the standardtools developed by the EDA indus-try are, for economic reasons,aimed at the largest marketsthedesigners of application-specificdevices. Meanwhile, at companieslike Sun,Compaq, Motorola, IBM,and, of course, Intel, designingin-house tools to meet the chal-lenge of noise in next-generationmicroprocessors is as important

as designing the chips themselves.At Houston, TX-based Com-

paq Computer Corp.s recentlyacquired Alpha EngineeringGroup, Chris Houghton is a front-line soldier in the battle againstnoise in deep-submicron designs.A recent Alpha microprocessordesign, says Houghton, had over15 million transistors with mil-lions of signal nets to verify. Tim-ing and coupling verification was

a monumental effort for thisdevice. This process directlyaccounted only for parasitic resis-tance and capacitance, but nothigh-frequency effects (HFEs).The Alpha design team, whilerecognizing that these effectswhich include the inductanceand resistance in a signal/signal-return loopcan be a problem,did not make quantifying HFEsa part of the verification process.

Indeed, the sheer size of theseproblems hampers designers intheir efforts to obtain accuratenoise analyses. The Alpha groupuses a plethora of tools, some ofwhich do very large scale simula-tions that do not necessarily pro-vide definitive answers, whileother, more accurate tools per-

form smaller-scale simulations.Still other tools work for struc-tures that are most easily repre-sented in two dimensions, whilemuch slower and more cumber-some tools handle structuresthat must be represented in threedimensions.

At Sun, John MacDonald isattacking the noise problemlargely with tools and methodsdeveloped in-house.The objec-

tive, says MacDonald, is toreduce the [degree of] couplingbetween signals with respect tothe overall capacitanceincreasethe space between lines, put inshielding, make sure a linesneighbor is stable and isnt goingto switch and induce currentthrough the coupling capacitance.One approach is minimizing therange of rise and fall times thatoccur in the design so that you

dont have some that switch fastand some that switch slow.Youtry to keep all the transitiontimesthe rise and fall timeswithin certain bounds.

But applying such constraintsdoes not necessarily involve sig-nificant tradeoffs. In high-per-formance design, MacDonaldargues, if you design thingswell, the rise and fall times tendto be all about the same anyway.

Rather than paying a price, heemphasizes, good designs will

PackageDecouplingCapacitance

DecouplingCapacitance

SwitchingCircuits

On ChipPackage

Vdd

Gnd

DC IR Drop (Voltage Drop)Variations in the DC power supply levels on-chip due toIR drops in the power/ground distribution

Delta-I Noise (Ground Bounce)The simultaneous switching of off-chip drivers and internalcircuits causes periodic variations in the supply and groundrails due to inductance on the chip and package supply andground wires

The static voltage drop across package and chip

resistance reduces the supply voltage available to

the circuitry. The change in ground reference due to

changes in ground current further reduces the voltage

available to the circuit. (Source: CadMOS)

Figure 2

Changes in Supply and Ground

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A1

A1 B1 C1

O1 O2

B1

A2

A2 B2

B2

C1

Beta noisecan be tunedto trade offone noisemargin againstthe other

Disallows singleNFET or PFET passgates because ofVtvoltage drop

Weaken devices toreduce charge sharing

Static Logic Gate

Dynamic Logic Gate

A1 B1 C1

A2

A2

B2

Add baby-sitdeviceto reduce charge sharing

Tune up length toreduce noise dueto leakage current

Increase size offeedback device

The effects of charge sharing can be reduced by

changes in circuit topologies. (Source: CadMOS)

Figure 3

Noise Reduction

minimize noise while improvingperformance. Large variations inrise and fall times that can causeproblems arise generally in less-than-optimum designs. If youreminimizing noise problems, hesays, youre generally also help-ing performance.

Another method is to put in

repeaters or insert a CMOS gatewith a single input and no logicfunction as a buffer somewherealong the line, to divide it up intotwo nets. Here, MacDonald con-cedes, there is a price to pay interms of lost area, but, by usingthese strategies judiciously onlines that are particularly sensi-tive, designers can solve noiseproblems at reasonable cost.

Sun Microsystems, he says,

primarily uses [CAD] tools thathave been developed in-house,but not by preference. Internaltool development is the price forbeing on the cutting edge of tech-nology.People designing high-performance microprocessors,says MacDonald,tend to run intoproblems before the EDA indus-try is ready to address them. Wetend to push the edge of what wecan do. We may be working one

technology ahead of what theASIC designer does.

Any Port in a Thunderstorm

The tools developed on an ad hocbasis by microprocessor designteams may do the job, but theyoffer little to other deep-submi-cron designers as a general solu-tion to the noise problem.Ourin-house solutions, says Mac-Donald,are very highly inte-

grated into our [unique] designmethodologies, and that just

doesnt translate very well. Werenot in the tool business and wedont do a great job of buildingtools. Often, he quips,werehappy to put something togetherwith bailing wire and chewinggum as long as it helps us get thechip out.

MacDonald believes that the

industry has, so far, made moreprogress identifying these prob-lems than solving them. Peopleare just starting to put togetherverification tools that can lookfor potential noise problems ineach net in a designtools thatcan verify every interconnect.

These tools, often cobbledtogether by microprocessor designteams, dont meet ASIC needs fora number of reasons. For one

thing, the modeling primitive isdifferent. Where the microproces-sor design and analysis paradigmis transistor-based analysis, ASICdesign is gate-based. For ASICdesigners, the problem promisesto grow more acute.Where micro-processor designers have the rela-tive luxury of working on nextyears advanced devices, the ASICworld needs to turn things aroundin a matter of months or less.

The EDA industry is justbeginning to come to grips withthe noise problem. At least half adozen companies are working todevelop the new physical designtools that will determine the per-formance of tomorrows chips.The new breed of tools mustinclude powerful electrical analy-sis capabilitiesif not to over-come, then to at least postponethe barrier presented by noise.

Its not yet clear how the EDAindustry and the designers of

advanced devices will meet thechallenge of noise in the future.Will large EDA firms eventuallydevelop highly automated toolsthat reduce the problem to a moremanageable scale, or will smallerstart-ups break the new ground?Will microprocessor designerseventually possess fully-automatednoise analysis tools or will they

continue to outrun progress intool development? What is certainis that noise will not go away, theproblem will expand as circuitelements shrink in size, and theneed for better and better noiseanalysis tools and methodologieswill remain.

Robert Patton is a freelance

technology writer in Newport,

VT.