Wafer Preparation Challenge in epitaxial growth : - Achieving defect free films at low temperate....
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![Page 1: Wafer Preparation Challenge in epitaxial growth : - Achieving defect free films at low temperate. More than half of the yield loss is due to contamination.](https://reader035.fdocuments.us/reader035/viewer/2022062713/56649cf75503460f949c72c5/html5/thumbnails/1.jpg)
Wafer Preparation
Challenge in epitaxial growth : - Achieving defect free films at low temperate.
More than half of the yield loss is due to contamination such as organic and metallic impurities.
-------------- surface preparation is important
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Wafer Preparation
Surface preparation prior to epi growth generally consist of 2 part :
(1) ex-situ clean : RCA cleaning
(2) in-situ clean : high temperature H2 annealing
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RCA and HF dip
RCA Clean :
(1)Removing the organic and metallic impurities from the silicon surface by oxidizing the silicon surface
(2) Forming complexes with the contaminants,which
become water-soluble.
.
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RCA Clean 標準步驟
1. GP4 振 10~15 分鐘 (GP : H2O = 1 : 15 )
( 此步驟通常不做 )
2. ACE 振 10~15 分鐘 , 沖 DI water 5 分鐘 3. H2SO4 : H2O2 = 2 : 1 泡 15~20 分鐘 , 沖 DI
water 5 分鐘 (H2SO4 can remove organic.)
4.Dip HF 至不沾水 , 沖 DI water 5 分鐘
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RCA Clean 標準步驟
(SC1) 5. NH4OH : H2O2 : H2O = 0.05 : 1 : 5 煮 ( 先煮水 ) 15~20 分鐘 , 沖 DI water 5 分鐘
(remove particle by forming chemical oxide)
(SC2) 6. HCL : H2O2 : H2O = 1 : 1 : 6 , 煮 15~20 分鐘 ( 先煮水 ) , 沖 DI water 5 分鐘
(remove metal )
7. Dip HF 至不沖水 , 沖 DI water 數秒
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RCA after with HF last
After the RCA clean - the silicon surface is left passivated with a
chemical oxide ,which protect the surface against recontamination
HF dip : Removing the chemical oxide and the native oxide to achieve the atomically clean silicon surface
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RCA after with HF last
To accomplish low temperature epitaxy, one must have an atomically clean Si surface
HF clean
1.The Si surface is Si-H terminated
2.Highly resistant to oxidation
3.May be exposed to room air for several minutes without significant oxidation
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After HF Dip
HF : DI =1 : 100
H H H H H H H O H H H
213 /100.1 cmatmmonolayer
100
1
H passivation
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H2 Prebake
If the temp. of H2 bake is higher than 1000°C
--------no HF etch is necessary
And
------surface is better than HF dip followed by a H2 pre-bakes at 900°C or less.
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High Temp. Effect of H2 Prebake
But high temp. may causes
n+
Out-diffusion
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Low Temp. Bake
The commercial UHCVD systems that are capable of bake temperature (EpiGress) usually require 20 minutes at 800ºC to have an O & C free interface.
but the problem is :
The EpiGress takes a lot time to ramp up to 800ºC then cool to a deposition temperature of 550-650ºC ------- Not too good for throughput
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Low Temp. Bake
ASM has developed a novel hydrogen prebake that has the potential lower the bake temperatures (below 700ºC).
If this novel technique is combined with plasma NF3
chamber cleaning at say the benefits to throughput would also be significant
C450
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Water Vapor and Bake Conditions
Water vapor is the most persistent contaminate in any vacuum system
The effectiveness of the bake at a given temperature is directly proportional to the water and oxygen background in a given system
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222 22 HSiOSiOH
Surface Oxide Formation by MoistureSurface Oxide Formation by Moisture
6.4 7.2 8.0 8.8 9.6 10.4 11.21E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
0.01
0.1
1
10
clean Si
SiO2 covered
Par
tial H
2O p
ress
ure
(tor
r)
1/T(10-4 K-1)
1200 1100 1000 900 800 700 600 C
torrC
torrC6
4
10900
101050
:freeoxideFor
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SiGe Epitaxial growth
Choosing a Growth Temperature :
- tc (critical thickness) is the most important factor
- IF the critical layer thickness for a given Ge fraction is exceeded , misfit dislocation injection occurs.
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Critical Thickness
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Metastable state
thermal equil. state
metastable state
Tota
l ene
rgy
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Metastable state
Growth conditions
At low Temp. (625ºC)
Surface reaction limited
Nonthermal equil.
Fewer dislocations than expected ,when t>tc
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a
Si substrate
SiGegl i di ng
Ti me
Top vi ew
Propagati on
Si de vi ew
nucl eati on and propagati on
From metastabl e to thermal equi l .
Nucl eati on and Propagati on
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Misfit dislocation
The thickness of SiGe growth >tc
The film relaxs
Misfit dislocation
This relaxation is catastrophic for SiGe HBT application
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dislocation line
nucleation site
W
L/2
L - dislocation length
W - width of area interested
(a) nonselective area
Selective epitaxy
Area nucleation
Edge nucleation
Field oxide
(b) selective area
Schematic diagram illustrating concept of selective growth
3333
Oxide defect
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Dislocation number
The number of dislocation in non-selective area
)2(: 2WLW
sites nucleation ofdensity areal:α
lengthn dislocatio average : L
holes oxide of width :W
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Dislocation number
The number of dislocation in the selective area
βWαW 4: 2
edgeoxidetheonsitesnucleationofdensitylinear:β
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Enhancement Factor (EF)
WW
WL
2
areaselectiveinNumber
areaselectivenoninNumberEF
area
edgeW
4,
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1En
hanc
emen
t fa
ctor
1
Enha
ncem
ent
factor
W0 L
W0 L
(a) W0 <2L , edge nucleation not so severe
2L/W0
(b) W0>2L, serious edge nucleation
Square width , W
Square width , W
areaedgeWo
4
Schematic plot of enhancement factor as a function of area width
2L/W0
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Si0.8Ge0.2
Two samples were studied
(A) 150nm with hole edge aligned with {100} direction
(B) 200nm with hole edge aligned with {100}
direction
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Si0.8Ge0.2
{110} {100}
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The dislocation networks of Si 0.8 Ge 0.2 with different sidewall orientation
(a) {110}
(b) {100}
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Threading dislocation
Threading dislocation in HBT
SiGe
Si
misfit
threading dislocation
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Threading dislocation
Threading dislocation
Misfit dislocation
Misfit dislocation interact to form threading dislocation
Multiplication of dislocations
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Gradual relaxed buffer
-210 cm10T.D
265 cm10~10T.D
Misfit dislocation40% SiGe
Si substrate
7%13%
20%
25%
30%
35%
40%
Si substrate
800 2000Thickness in nm
growth direction
SiGe
growth direction
Gradual relaxed bufferMisfit dislocation do not concentrate in one interfaceTo reduce misfit dislocation interactionTo reduce the threading dislocation density
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(a) as - grown
(b) 5min.
(c) 60min
The dislocation networks of 200nm Si .87 Ge .13 with various annealing time
at 900 C
The
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Strain after anneal
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SiGe
Si
d
nd sin2
θd ,strain More
θ
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Deposition temperature
Once this critical thickness guideline is satisfied :
Deposition temperature(T)
The film quality for the epitaxial film
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Film Quality
when T decrease, the silane flow must decrease also.
ex:
T : 700ºC ; 100% silane : 50sccm------will deposit a specular high quality film.
but T : 600°C ; 100% silane :50sccm-----the film beome hazy
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Film Quality
Faceting/Conformality
- Lower temperature and the resultant lower growth rates result in less faceting and improved conformality
Poly/Si growth ratio ----- for customers who use a field oxide, depending on temp, this ratio can vary.
- Low T favors Si(single crystal) growth
- High T favors poly growth
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Dichlorosilane(DCS)
Dcs(SiH2Cl2 )is the only one that has been applied to the growth of SiGe epitaxial layers
- SiCl2 on the surface is then thought to react with hydrogen to form HCL and a silicon adatom
2222 HSiClClSiH
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Advantage of DCS over silane
Specular defect free surface
-----Superior surfaces are evident with DCS even when processing at extremely low temperatures as a result of the HCL released in the decomposition.
Temperature : DCS : 700C , silane : 600C.
Safety -----silane is explosive and highly pyrophoric