W8 Modern CMOS front-end I - AGH University of Science and...
Transcript of W8 Modern CMOS front-end I - AGH University of Science and...
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MOS Front-End
Front-end-of-line includes substrate, isolation, wells, transistor, silicide
n-wellp-well
STI
Transistor Contact
Front-end
Back-end
Field effect transistor
MOSFET: Metal-Oxide-Semiconductor Field Effect TransistorInvented: Lilienfeld 1926. First made: Kahng, Attala 1960
Properties of a MOSFET:• Small area• Low power• Simple technology• Lower switching speed than bipolar device
CMOS: Complementary MOS: NMOS + PMOS
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Free electronFree hole
NMOS
+ + +
PMOS
- - -
Conducts at +VG
NMOS + PMOS = CMOS: why?
Conducts at -VG
NMOS and PMOS transistors
CMOS - inverter layout
Circuit schematic Silicon cross section
NMOSB = pwell
PMOS
B = nwell
Vdd
Vin Vout
p-substrate
n-well
Vss Vdd
Vin
Vout
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From NMOS to CMOS
HighLow
LowHigh
GND
Vdd
HighLow
LowHigh
NMOS logic: high power during ‘low’ output.NMOS inverter slowly switches to ‘high’ output.(Same effects in PMOS logic.)
NMOS inverter CMOS inverter
Capacitiveload
Present CMOS
0.18 µm CMOS is now produced by all major manufacturers.
This process features:
• 0.12-0.18 µm gate length, 0.4-0.5 µm pitch• 3-3.5 nm gate oxide (regular SiO2)• 5-6 levels of metal interconnect
• About 107 transistors on a 1 cm2 chip• 1.2 GHz on-chip clock frequency
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1960 1965 1970 1975100
101
102
103
104
105
Year
Gordon Moore 1965
Num
ber
of c
ompo
nent
s pe
r ch
ip
(Prediction)
Tra
nsis
tors
per
chi
p
103
104
105
106
107
108 INTEL microprocessorsSource: Intel website
1970197519801985199019952000
Year
Moore’s LawPentium 4
Brews’ Law
Lmin = 0.4 [ xj tox (Ws + Wd)2 ]1/3
• Lmin: minimum gate length without short channel effects
• xj: junction depth (µm)• tox: oxide thickness (Å)
• Ws, Wd: depletion widths of source and drain junctions (µm)
Moore’s law implies gate length scalingBrews’ law implies: many other dimensions scale with it
L
tox
xj
Ws
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ITRS “roadblocks” in CMOS front-end
ITRS 2000 topics with “no known solution”:• 90 nm node:
– Shallow junctions with xj 20-30 nm, Rs 250-600 Ω/• 60 nm node:
– Gate dielectric thickness < 1.2 nm– Gate tunnel current < 20 A/cm2
– Gate doping > 4x1020 cm-3
In other words: the MOS transistor requires several research breakthroughs to continue scaling beyond the 100 nm node!
• http://public.itrs.net
Outline
• Introduction to CMOS (why CMOS?)• CMOS process flow• CMOS process modules (step by step)
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STI (Shallow Trench Insolation) formation (field isolation)
Sacrificial oxide (warstwa protekcyjna) on top of silicon:To avoid contamination
Retrograde (wsteczne) n-well formation
n-well
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Retrograde p-well formation
p-well n-well
Gate oxide growth + poly deposition
poly
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After polysilicon deposition
Pho
to: P
hilip
s R
esea
rch
After gate etch - S/D formation
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PMOS S/D extension implant(and NMOS extension implant)
Spacer formation
thin oxide + nitride
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NMOS - S/D implant
Simultaneous source, drain and gate doping, and well contact doping
PMOS - S/D implant
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After S/D implants
Silicidation
TiSi2 or CoSi2 (sub-0.18 µm technologies)
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Spacer
TiSi2
TiSi2
Polygate
TEM cross-section after silicidation
Pho
to: I
ntel
Contact formation
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CMOS inverter after first metal
input input
0.25 µm CMOS after Metal 6
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Outline
• Introduction to CMOS (why CMOS?)• CMOS process flow• CMOS process modules (step by step)
CMOS process modules
• Field isolation• Wells• Gate dielectric• Gate conductor• Shallow junctions• Pocket implants• Spacers• Source, drain and gate doping• (Silicide)
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Field isolation
• Purpose: to electrically isolate adjacent MOSFETs• Traditional in bipolar and MOS: LOCOS isolation
• sub-0.35 µm CMOS: always Shallow Trench Isolation
LOCOS field isolation
Stack deposition
Stack etch
LOCal Oxidation
of Silicon
Stack removal
Si3N4
SiO2
Si
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Shallow trench isolation (STI)
Stack deposition
Trench etch
Oxidation Trench fill
(deposition & CMP)
Stack removal
Transistor well formationPurpose of the well:
• opposite-type to S/D:
– to give isolation between S/D and wafer (reverse-biased diodes)
– inversion gives channel conductivityIssues:
• Doping level determines VT and short channel effects
• Diode leakage, capacitance, parasites
• Deep doping (~ 1 µm)• Vertical and lateral grading
– super steep retrograde well
– pockets
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Conventional well
Standard Technology in > 0.5 µm CMOS generations+ Low cost - standard equipment- Large temperature budget: long time - high T- Large lateral diffusion- Highest doping concentration at surface
1D depth profiles 2D cross section
P-substrate
As implanted
After 6h 1150ºC in N2
n-well
Con
cent
ratio
n
Depth
Retrograde well
Standard in (sub) 0.25 µm CMOS technologies+ Buried peak doping concentration (channel stop, latch up, ...)+ Low temperature budget- Dedicated high energy ion implanter needed for n-well- Higher junction capacitance
n-well
As implanted
n-well
Con
cent
ratio
n
Depth
P-substrate
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Super steep retrograde well
• < 0.25 µm CMOS: high channel doping to control short channel effects• low VT necessarySSR well:
• low surface doping (giving low VT and high mobility)
• high doping at 50-200 nm depth (reduces short channel effects)
Gate
SSR peak
Well
IdealRealistic
SSR
Well
Source Drain
Con
cent
ratio
n
Depth
Gate oxide + gate polysilicon
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Gate oxide formation
• Remove the existing SiO2 that screens the silicon
• Clean the wafer• Oxidize the wafer at high temperature• Post-anneal (N2, N2O, NO…)• Immediately deposit polysilicon gate on top
Thin oxide growth
Wet (diluted H2O) - low temperature (600-700ºC)
Furnace
Dry (diluted) O2 ( + nitridation N2O, NO)
Temperature: 800 - 900ºC
+ Standard method, excellent uniformity, batch process
- Run takes several hours. Very difficult for tox < 2.5 nm
Rapid Thermal Oxidation: Dry O2 ( + nitridation N2O, NO)
+ Growth at higher temperature → more nitrogen incorporation
+ Only a few minutes per wafer
- Uniformity, reproducibility
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TEM cross section thin oxide
G. T
imp
et a
l., IE
DM
199
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ITRS roadmap: oxide thickness
0
0.5
1
1.5
2
2.5
0.18 0.13 0.1 0.07 0.05 0.03
CMOS generation (µm)
(Equivalent) Oxide
Thickness (nm)
1999
20042007
20102014
2001
Leakage current through SiO2 increases exponentially
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Tunnel current
‘Thick’ oxide (> 4 nm):triangular tunnel barrier
Fowler-Nordheim tunneling
Thin oxide (< 4 nm):Trapezoidal barrier
Direct tunneling
3.1 eV
p-substrateSiO2
n-gate
qVG
p-substrateSiO2
n-gate
(band diagrams at negative gate voltage)
Tunnel current - very thin oxide
Leakage current exceeds 1A/cm2 (!) at 100 nm CMOS generation
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
0 0.5 1 1.5
V GS (V)
JG (
A/c
m2 )
MeasurementModel
t ox = 2.2nm
t ox = 1.7nm
t ox = 1.4nm
Van
Lang
evel
de, I
ED
M 2
001
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ITRS: gate dielectric will change
SiO2 High k
0
0.5
1
1.5
2
2.5
0.18 0.13 0.1 0.07 0.05 0.03
But: no high-K dielectric yet fulfills all requirements!
CMOS generation (µm)
EO
T (
nm)
Candidate high-K gate dielectrics
10 20 30 40
SiO2
vacuum
Al2O3Si3N4
TiO2HfO2ZrO2
Ta2O5
BST
K:
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Gate electrode formation
• Dual-flavor gate technology in CMOS• n+ and p+ doping of polysilicon• Gate depletion• Boron penetration
Dual-flavor polysilicon gates
n+ poly for the NMOS transistor, p+ poly for the PMOS• Symmetric: given same oxide thickness and doping
levels, VTNMOS = -VT
PMOS
• Excellent work functions• Convenient processing: self-aligned source, gate,
drain and well contact implant; all activated together.Issues:• how to achieve high gate doping• connection between n+ poly and p+ poly• (inter-diffusion of impurities between n+ and p+ poly)
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Doping of polysilicon
n+ gate doping with S/D implant
• Phosphorus gives the best gate doping: very high solubility, high diffusion, high activationbut: too high diffusion for source/drain implant
• Arsenic more complicated:– lower diffusion constant, lower activation– getters at the Si/SiO2 interface; evaporates– de-activates in 700-800ºC thermal treatments
• Antimony: too low solubility (4x1019 cm-3 at 1000ºC)
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p+ gate doping with S/D implant
• Indium:– Too low solubility (< 1019 cm-3)– Diffuses through gate oxide (‘indium penetration’)
• Boron:– The only option (either with B or BF2 implant)
– Risk of boron penetration (since 0.25 µm CMOS)– Clustering above solubility limit: problematic– de-activates in 700-800ºC thermal treatments
Gate depletion
chan
nel
n+ga
te
VG = VFB VG > VFB VG >> VFB VG >>> VFB
Ionized (activated) As atom
Free electron
n+ poly gate for NMOS:
gate depletion is inevitable
Lower capacitance → less current
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1021
1019
1018
1017
1020
Gate oxide
polysilicon monosilicon[B
] (cm
-3)
depth
Boron penetration
as-implanted
boron penetrationproper activation
Gate doping > 1020 cm-3
Channel doping << 1019 cm-3
Slight boron penetration → dramatic VT shift
Solutions: reduce thermal steps, replace gate oxide...
PMOS S/D extension implant
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Extensions: purpose and requirements
• Suppress short channel effects
• Add series resistance (good for 0.25 - 0.8 µm technology, LDDs)
Brews’ Law: Lmin ∝ [ xj tox (Ws + Wd)2 ]1/3
Criteria for shallow junctions:
• Junction depth
• Sheet resistance
• Good diode operation• Junction profile steepness
• Uniformity, reproducibility
• Low defect density (residual crystal damage)
• CMOS compatible (materials, thermal budget)
Treated in the following slides
ITRS scaling of shallow junctions
0
10
20
30
40
50
60
70
0.18 0.13 0.09 0.06
Junc
tion
dept
h (n
m)
CMOS generation (µm)
0
100
200
300
400
500
600
700
800
0.18 0.13 0.09 0.06
CMOS generation (µm)
She
et r
esis
tanc
e (Ω
/) PMOS
NMOS
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Sheet resistance
Depth profile
Rs = 1 / q ∫ C(x) µ(C) dxx=0
x=xj
Sheet resistance Rs depends on theconcentration of free carriers C(x) and on the mobility of these carriers µ(C):
(approximation for not-too-steep profiles)
Aim for high concentration;junction depth is imposed by generation.
Steep tail at fixed xj → lower resistivity!
xjDepth
Source/drain
Channel
Impu
rity
conc
entr
atio
n
Junction depth
Definition: junction depth (xj) = metallurgical junction: the depth where the n-type concentration equals the p-type concentration.
Determination of junction depth: SIMS (or SRP).
xjDepth
Source/drain
Channel
Impu
rity
conc
entr
atio
n
Steepness is important; but also the proper activation of the peak (should be below the solubility limit at the anneal temperature)
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B and As diffusion - example
High T pushes junction - much stronger effect for Boron
B c
once
ntra
tion
(cm
-3)
Depth (nm)
As
conc
entr
atio
n (c
m-3
)
Depth (nm)
Data: Philips Research
Shallow junction annealing
• Furnace anneals:typically 2+-hour runs,slow ramp up and down– too much TED– too much diffusion
• Rapid thermal anneals• Spike RTA anneals• Laser anneals
> 0.25 µm
0.13 - 0.25 µm
< 0.13 µm
Pho
to: S
emat
ech
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Rapid thermal anneal cycle
time
tem
pera
ture
Stabilisation500-700°C
First ramp-up
Ramp-up (50ºC/s)
Anneal (0-60 seconds)
Ramp-down (25ºC/s)
Pockets“Large Angle Tilt Punch Through Stopper”
• Punch through stopper implanted under tilt angle after gate formation
• Reduces depletion regions of source and drain• Angle, dose and energy are critical parameters
+ low channel doping, low VT possible (low voltage technology)
- Process control, more expensive implanter
well
Also called:HALOlatips
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Spacer formation
Spacer process flowsStandard:TEOS or Si3N4 depositionPlasma etch
Two-layer deposition (e.g. SiO2 + Si3N4)Plasma etch of top layerOptional etch of layer 2
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PMOS - S/D implant
Source/drain implantPurpose:• S/D implant adds impurities to the shallow junctions:
– lower sheet resistance – deeper junction (convenient for salicidation)
• Gate doping• Doping of the well contactsOptimization:• Low sheet resistance of junctions and poly• Low gate depletion - no boron penetration• Good diodes; suppression of junction spiking• Low salicide contact resistance
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Activation anneal
• Last step of the MOS front-end fabrication• Activation of: gate, source and drain implants• High temperature required for good activation• Short time required for suppression of diffusion
Therefore: again, Rapid Thermal Anneal
• Optimization of this step is truly “process integration”• Fabrication after this anneal can influence activation:
– de-activation– further diffusion (dr. R.A.M. Wolters…)
MOS front-endFurther reading
• S. Wolf - The submicron MOSFET
• F. Pierret - Field effect devices
• A. S. Grove: Physics and technology of semiconductor devices, John Wiley & sons
• The Technology roadmap for semiconductors:
http://public.itrs.net
• A dictionary of semiconductors:
http://www.sematech.org/public/publications/dict/index.htm
• Nice 3D view of transistor fabrication and operation:http://www.micro.magnet.fsu.edu/electromag/java/transistor/index.htmlhttp://entcweb.tamu.edu/zoghi/semiprog/INDEX1.HTM
• Many interesting links at www.casetechnology.com/links.html
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Closing remarks
• MOS technology changed a lot over the years• CMOS front-end-of-line technology gets complex
– many new materials– tight process windows– incredible pace of innovation
• Scaling down to 30 nm feasible• Many challenges for research!