W. Hofle LIU-SPS Meeting - 26.08.2014 1 SPS BA2 Damper LS1 Progress and plans reported by W. Hofle...

W. Hofle LIU-SPS Meeting - 26.08.2014

1

SPS BA2 DamperLS1 Progress and plans

reported by W. Hofle

LIU-SPS Meeting 26.08.2014

G. KotzianT. LevensD. Valuch

Acknowledgements: BE-RF-PM, BE-RF-CSU. Wehrle, T. Bohl


2

Reminder of reasons for upgrade

• sharing pick-ups with BI in future not possible due to MOPOS upgrade

• requirements for single bunch damping for protons used for LHC p-ion Physics (closer spaced proton bunches, 100 ns)

• ions injection damping with fixed frequency scheme, closer spaced batches

• individual bunch damping for crab cavity studies not possible with present system (sampling currently not synchronous with bunch)

• LHC doublet scrubbing beam incompatible with present system• controls with G64 chassis and MIL-1553 are obsolete (MMI) new

controls for power system and LLRF, new RF function generators

Operation during slip stacking not investigated yet (this concerns ions for HiLumi)


3

Dismantling at start of LS1


4

Dismantling at start of LS1

• Removed all equipment in damper LLRF racks• Shutdown of G64 RF-MMI controls• Removal of cable delay loops under false floor• Obsolete cables identified, re-arrangement


5

Dedicated pick-ups

BPCR.214

BPCR.221

• 2 BPCR (H/V) for LHC type beams (couplers)• 2 BPH electrostatic PU (pFT)• 2 BPV electrostatic PU (pFT)

BDH / BDV kickers unchanged

installed and cabled


6

Dedicated electrostatic PUs

BPH.202

BPV.205 BPV.207

BPH.204

installed and cabled


7

Pick-up electronics moved

Electro-static PUswith high impedance preamplifiers in tunnel

Electronics moved from208,209,210,211To newly installed Pusat 202,204,205,207all checked and repaired(R. Louwerse/G. Kotzian)

Spare electronics remainsIn tunnel (hot spares)@212,213,214,215 Pit equipped with Damper electronics

for fixed target beam, very reliable & robust (20+ years)(future renovation envisaged, outside LIU scope)


8

New fiber links BA2BA3 and clock distribution

RF RX D(TRR)

EDA-01382FREV SPS

SynchronousRF Divider(MASTER)[120MHz]

80..420MHzDistributionEDA-01335

Clk DistriEDA-00594[380MHz]

ADCCLK/DACCLK (PFT)

ADCCLK/DACCLK (LHC)

ADCCLK/DACCLK (SCRUB)

Clk DistriEDA-00594

[FREV]

RF RX D(SRX24)

EDA-0138210MHZ REF 5..100MHzDistributionEDA-01334

Clk DistriEDA-00594

[10MHz]

LO 200 MHz pLHC H

LO 200 MHz pLHC V

FREVDistributionEDA-01336

FRF SHIFTED

RF RX D(SRX24)

EDA-01382

~2usFiber Delay + Distribution

LO 200 MHz (IONS PU214.H)

SynchronousRF Divider(IONS-A)[120MHz]


LO 200 MHz (IONS PU221.H)

SynchronousRF Divider(IONS-B)[120MHz]



SynchronousRF Divider(IONS-C)[120MHz]

SynchronousRF Divider(IONS-D)[120MHz]

LO 200 MHz (IONS PU214.V)

LO 200 MHz (IONS PU221.V)

ADCCLK (IONS PU221.V)

ADCCLK (IONS PU221.H)

ADCCLK (IONS PU214.V)

ADCCLK (IONS PU214.H)

DACCLK (IONS H2)

DACCLK (IONS H1)

DACCLK (IONS V1)

DACCLK (IONS V2)

RF TX D(STX03)

EDA-01380

RF TX D(STX03)

EDA-01380

RF TX D(STX24)

EDA-01380

RF Phase Shifter

EDA-01618FRF SPS

BA2BA3

cfv-ba3-allfo1 cfv-ba2-allfo1



cfv-ba3-allsync1

5

5

4

SynchronousRF Divider(MASTER)[40MHz]

LO 40 MHz (SCRUB H)

LO 40 MHz (SCRUB V)

2

BPF200MHz

BPF10MHz

Clk DistriEDA-00594[400MHz]2

2

cfv-ba2-allclkgen

cfv-ba2-allclkgen

cfv-ba2-allclkgen

cfv-ba2-allclkgen

cfv-ba2-allclkgen

cfv-ba2-allclkgen

5x

4x

2x

5x

Stable phase (ppm)

Frequency program (ppm)

Ions for implementationIn 2015)

200 MHz RF

frev

10 MHz ref

+ inj. Pulse (copy of SPSCPS)

200 MHz LO

40/80 MHz LO

120 MHzADC/DAC

expect over year20 degreesdrift @200MHz


9

pLHC electronics

Hybrid H9

Ga

uss

ian

typ

e lo

w

pa

ss,

f c=

40

MH

z

I+

I-

Su

m IF

to

dig

ital b

oard

Comb filterfcenter = 200MHZ4 pulses (20ns)

Delay equalization

D

SA

B

Coax lineTunnel-BA2

(300m, 7/8" Flexwell)

Stripline pickupfcenter = 200MHz

beam

4-way

4-way

0°

90°

Q+

Q-

ADC driverGain

Dip

lexer

<400MHz

>400MHz

Dip

lexer

<400MHz

LO1200MHz/

IF -

3 (

0)

dB

m

ADC

Dual 16bit ADCVin 1-2Vpp

Vcm = 0.7-1.25VDDR CMOS out

ADC

- 16 bit data- 1 bit ovf- 1x ENC clock- 1x /CS- 2x SCK+SDI

I+

I-

Del

ta I

F to

d

igita

l boa

rd

Gain control

0°

90°

Q+

Q-

LO1200MHz

ADC

ADC

- 16 bit data- 1 bit ovf- 1x ENC clock- 1x /CS

Hybrid H9

Ga

uss

ian

typ

e lo

w

pa

ss,

f c=

40

MH

z

I+

I-

Su

m IF

to

dig

ital b

oard

Comb filterfcenter = 200MHZ4 pulses (20ns)

Delay equalization

D

SA

B

Coax lineTunnel-BA2

(300m, 7/8" Flexwell)

Stripline pickupfcenter = 200MHz

beam

4-w

ay

4-w

ay

4-way

4-way

Gain control

0°

90°

Q+

Q-

ADC driverGain

Dip

lexer

<400MHz

>400MHz

Dip

lexer

<400MHz

LO2200MHz

IF -

3 (

0)

dB

m

ADC

ADC


I+

I-

Del

ta I

F to

d

igita

l boa

rd

Gain control

0°

90°

Q+

Q-

LO2200MHz

ADC

ADC


- 10 bit data- 1 bit WR

- 1 bit WR

- 1 bit WR

- 1 bit WR

200MHz LO2 in

Firmware

t

t

t

t

- 1 bit /CS

- 1 bit /CS

- 1 bit /CS

DAC1- 16 bit data

- 1x /CS- 2x SCK+SDI

t

DAC2- 16 bit data

- 1x /CS

t

- 1 bit WR

- 1 bit switch

120 MHz clocks

DA

C Gain control

- 1 bit switch

DA

C

- 1x /CS- 2x SCK+SDI

Module 1 outputH1 (or V1)

Module 2 outputH2 (or V2)

4-w

ay

4-w

ay

Gain control

200MHz LO1 in

ADC1 ADC2 DAC1 DAC2

ADC2 CLK 120 MHz

ADC1 CLK 120 MHz

DAC2 CLK 120 MHz

DAC1 CLK 120 MHz

Digital Boardanalogue front-end(here for LHC beam)

S

variable delaysfor clocksADC/DAC(120 MHz)

mixing 200 MHz

H1 (V1)

H2 (V2)

BPCR.214 (H/V)

BPCR.221 (H/V)


10

Digital Board

• 12 boards fabricated, eight needed, tested ok for start-up• separate boards for H- and V-plane and beam type (pFT, pLHC, pSCRUB, Ions)• tested up to beyond 120 MHz clock frequency, Xilinix ARTIX 7 FPGA• features ADCs and DACs with four different clock domains for delay adjustment

New development !

8 ADCs4 DACs

outputgain control via DAC a laLHCADT

Board will be usedfor ADT (independent gain control on DACs)


11

BA2 Installation

New Fiber Links

New VME cratesLHC RF style

pFT, pLHC pFT, pLHC

pSCRUB, Ions pSCRUB, Ions

clock generationsignal distribution

H-planeV-plane

test system


12

Test set-up in lab

RF functiongenerator

pFT signalprocessing

pLHC signalprocessing

signal combination/selector

timing

Crate management

clock distr.

CPU

W. Hofl

e LIU-SPS Meeting -

26.08.2014

13

Fixed Target Beam

• pre-amplifiers in tunnel• variable gain control, ADC protection• signal conditioning for direct sampling (S and D)• sampling in baseband @120 MS/s

Reminder: each beam type (we have four !) requires dedicated and differentsignal conditioning or down mixing before digitization

pFT analogueboard before ADCs


14

LHC Beam

200 MHz filters during production in CZ clock generation board (all beams)

• 200 MHz bandpass filters (S and D)• programmable gain/attn• down mixing (I,Q) to base-band• ADC protection• sampling @120 MS/s (on digital board)


15

Scrubbing Beam (SPS)

To be decided and filter to be designed: • baseband (risk of e-cloud perturbing) with 60 MHz anti-aliasing filter• 40 MHz BP: best signal, only small or no gain modulation during splitting• 80 MHz BP: least e-cloud perturbing expected, but gain modulation


16

Firmware and software

• firmware: memory map finished, functionality for beam implemented• no functioning FESA class yet (this is the current bottle neck for testing)• function generator OK, coast not ok yet (software !)• power system up and running after upgrade to PLC system, no CCR software yet• four power amplifiers modified, installed, 2 spare amplifier to be tested

critical path is software to have functioning FESA classes and PPM control

W. Hofle LIU-SPS Meeting - 26.08.2014 1 SPS BA2 Damper LS1 Progress and plans reported by W. Hofle...

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Transcript of W. Hofle LIU-SPS Meeting - 26.08.2014 1 SPS BA2 Damper LS1 Progress and plans reported by W. Hofle...