Vol 06, Article 06597; June 2015 International Journal of...

Vol 06, Article 06597; June 2015 International Journal of VLSI and Embedded Systems-IJVES

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2010-2015 – IJVES

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VLSI HARDWARE MODELING OF DYNAMIC RNS

STRUCTURE FOR HIGHEND COMPUTATIONS GANJI SARIKA YADAV1, V.THRIMURTHULU2, S.ALI ASGAR3

1 2 3 Department of Electronics and Communication Engineering 1II M.TECH (VLSISD),CR Engineering College, Tirupati,Chittor(Dist), A.P., India.

² Professor & HOD.,Dept. of ECE, CR Engineering College, Tirupati,Chittor(Dist), A.P.,INDIA.

³ Assistant Professor, Dept. of ECE, CR Engineering College, Tirupati,Chittor(Dist), A.P.,INDIA. [email protected], [email protected], [email protected]

ABSTRACT

This paper presents a dynamic structure for binary-to-residue number system (RNS) conversion modulo {2n±k}

using macro structures. This structure is based only on adders and constant multipliers. This concise work is

motivated by the existing {2n ± k} binary-to-RNS converters, which are particular inefficient for larger values of

n. The experimental results obtained for 8 X n bits of dynamic range suggest that the projected conversion

structures are able to drastically progress the forward conversion efficiency, with greater successful hardware

modelling. And macro modelling can highly increase proper selection and utilization of the {2n ± k} Moduli for

high end applications like Cryptography. The proposed logistic technique is simulated and verified by Xilinx tools

along with Virtex – 5 FPGA board.

Index Terms — RNS, Macro Modeling, cryptography, Xilinx tools and Virtex -5 FPGA.

1. INTRODUCTION

It is very familiar that the Residue Number System (RNS) has modular nature by means whit offers the prospective

for swift, parallel reckoning since that it is a carry-free calculation system, also it is to be noted that RNS is a non-

weighted number system, which uses remainders to represent numbers [1]. The basic arithmetic operations (add,

subtract, and multiply) are easily implemented in RNS and data computations are implemented over operands that

are extensively shorter than the resulting RNS Dynamic Range. Typical applications for RNS are in VLSI Digital

Signal Processing (DSP), Cryptography, Network Security, High end filtering, convolutions, correlations, and

Fast Fourier Transform computations [2]-[3] etc.

Basically the RNS modulus set is set up by defining the moduli of (mi) relatively positive prime integers. A

number P is represented in RNS by its residues pi = <X>mi, where pi is the remainder of the division of X by mi.

and then to implement complete RNS system Conversion from weighted number system to RNS (binary to-RNS

or forward conversion), and vice versa (RNS-to-binary or reverse conversion) is required. At the very beginning

the development of proposed system on RNS was mainly persistent on the three modulus set {2n − 1, 2n, 2n +

1}[4], but today the research has been extended to dynamic range of prime integers also such as {2n − k, 2n, 2n +

k}[3]-[5], k ɛ Z+ such that the implementation of such method can drastically improves the circuit performance.

The literature survey reveals the fact that various techniques are already proposed [6] like serial method, full

parallel method or serial-parallel technique etc, to reduce the weight representation of the number systems, which

is the root cause of occupying lot of system memory and consumes un wanted power consumption and finally the

architectures for high end process applications becomes much more slower. Therefore a new memory-less

standard [7] forward conversion structure for a DR of m = qn-bit, using {2n ± k} moduli, is proposed, considering

n ≥ 2. The projected approach divides the qn input bits into q input sets[8], and computes the particular residue

value using modular additions and constant multiplications[9] so that the idea of constant multipliers does not

lead to any excess memory consumption[10].

A. DESIGN DEVELOPMENT

To promote low power high performance applications of RNS, Various dynamic macro Techniques are modeled

on VLSI. The VLSI architectures developed as follows. The VLSI architecture proposed with this article for use

of RNS is to reduce on chip memory consumption adopts the macro selection condition which results in to

dynamic implementation of major techniques.

All these techniques are modeled and implemented by targeting the area and power consumption, the next

proceeding section will conclude all about proposed scheme. This proposal is also realized into field

programmable gate array (FPGA) prototyping system using Xilinx Viitex-5 unit. The maximum operating

frequency of this design is more than 500 MHz

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TABLE 1 SUMMARY OF DESIGN CONSIDERATIONS

S.No Design consideration Selection

1 Compiler Xilinix14.4Vivado

2 Programming Language Verilog

3 FPGA Virtex -5

4 Interface USB

2. MODELING OF RNS TECHNIQUES

B. RNS Representation:

An RNS is defined by a set of relatively prime integers called the moduli. The moduli-set is denoted as {m1, m2…

mn} where mk is the kth modulus. Each integer can be represented as a set of smaller integers called the residues.

The residue-set is denoted as {r1, r2 , …,rn } where rk is the kth residue. The residue rk is defined as the least positive

remainder when is divided by the modulus. This relation can be symbolically written based on the congruence: X

mod mk = rk The same congruence can be written in an alternative notation as: │X│ mk = rk The RNS is capable

of uniquely representing all integers that lie in its dynamic range. The dynamic range {m1, m2… mn} is determined

by the moduli-set and denoted as

n

1i imM (1)

The RNS provides exceptional depiction for all integers in the range between 0 and. If the integer is greater than

, the RNS representation repeats itself. Therefore, more than one integer might have the same residue

representation. It is important to accentuate that the moduli have to be relatively prime to be able to exploit the

full dynamic range

C. Mathematical Modelling of RNS conversion:

Allowing for a binary representation of X, with 4n-bit of Dynamic Range, it is required to compute in order to

attain the residue modulo {2n − k} of X.

Kn

20X

1kX

2X

2k

3X

3k

kn

20X

1X

n2

2X

2n2

3X

3n2

kn20]:1[n

Xn]:1[2n

Xn

22n]:1[3n

X2n

23n]:1[4n

X3n

2k

n2

X

(2)

Where X [k: l] represents the bits l to k of the integer X.

Similarly, the residue calculation modulo {2n + k}, is achieved as

Kn

20X

1kX

2X

2k

3X

3k

kn

20X

1X

n2

2X

2n2

3X

3n2

kn20]:1[n

Xn]:1[2n

Xn

22n]:1[3n

X2n

23n]::1[4n

X3n

2k

n2

X

(3)

Taking into deliberation the meticulous cases of modulo {2n − 1} and {2n + 1}, conversion from binary-to-RNS

can be performed as per given calculation.

1n20N1N2N3N1n2X

(4)

1n20N1N2N3N1n2X

(5)

Proposed architecture for modulo {2n ± k} presumptuous conversion is based on a parallel technique. In this

technique partial operation (ki · Xi) is first condensed to modulo {2n ± k}, and only then added to obtain the final

residue value. Thus, computation is performed in two stages: the first step computes the constant multiplication

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vectors and the second step performs the addition of all those vectors. This architecture exhibits the modular

reduction of each calculation, using the modulo {2n ± k} Carry-Save-Adder, instead of adding all terms and

reducing then iteratively at the conclusion. The suggested architecture is as shown below.

Figure 1: Architecture of RNS

The key design of this architecture that the macros are associated in the design description which facilitates the

logic transfer from one stage to other for example one bit length to other bit length can be easily avail without

changing the complete architecture. The implementation of macros lead to this proposed system works in various

bit lengths as 8, 16, 32 and 64.

D. Front-End Modeling:

This phase of implementation contains the following stages simulation using Xilinx 14.4 Vivado suite, synthesis

using Xilinx 14.4 XST and verifying on Virtex – 5 FPGA board.

3. SIMULATION AND SYNTHESIS RESULTS

The Verilog RTL Description of the above article is simulated and synthesized using Xilinx14.4 (ISE-Simulator),

implementation of all the above macro encoding techniques are successfully synthesized and verified on Virtex -

5 FPGA board and the results are shown below.

Figure 2: Simulation output for n = 8 Figure 3: Synthesis output for n = 8

Figure 4: Simulation output for n = 16 Figure 5: Synthesis output for n = 16

RADIX -8 RNS ENCODER

INPUT DATA

CONVERT INTO RNS

FAHA PP

GENERATOR

RCA MACROS CONTROL

RECODING

OUTPUT FILE

DIMENSIONAL

CONTROL

CSLA bank

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Figure 6: Simulation output for n = 32 Figure 7: Synthesized output for n = 32

Figure 8: Simulation output for n = 64 Figure 9: Synthesized output for n = 64

The Synthesized report is summarized in the following Table2.

TABLE 2 SUMMARY OF SYNTHESIS REPORT

S.No Parameter n =8 n =16 n =32 n =64

1 Slice Logic utilization < 5% < 5% <5% < 5%

2 Slice logic Distribution 93% 100 % 100% 100%

3 IO utilization 8% 8 % 14% 27%

4 Specific feature Factor 3% 8 % 14% 27%

5 Total Logic Delay(nS) 33.076 11.521 8.0593 9.156

6 Total Offset Delay(nS) 33.076 11.521 8.0593 9.156

7 Total path Delay(nS) 2.042 6.398 2.594 2.107

8 Real time Compilation(S) 22 8 12 18

9 Total memory (KB) 303664 282732 295080 318960

CONCLUSION

In this paper, we have presented VLSI hardware modelling of macro level implementation set of RNS designed

at reducing the power dissipated by the weighted representation of traditional technique of number systems used

in high end applications. In addition, their part is usual to increase in potential technology of memory usage. This

paper has realized with Xilinx tools along with Virtex -5 FPGA. Such designs are suggested to exhibits a

competitive performance with current work.

ACKNOWLEDGMENT

I express my sincere thanks to my guide and Project Coordinator Mr.S.ALI ASGAR, M.Tech, Assistant

Professor of ECE Dept, and to my HEAD OF DEPARTMENT Dr.V.THRIMURTHULU

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M.E.,Ph.D.,MIETE.,MISTE., Professor & Head of ECE Dept.,CREC,TIRUPATHI, for their valuable

guidance and useful suggestions, which helped me in the project work.

REFERENCES

[1] N. Szabo and R. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New York,

NY, USA: McGraw-Hill, 1967

[2] G. Cardarilli, A. Nannarelli, and M. Re, “Residue number system for low-power DSP applications,” in

Proc. 41st ACSSC, 2007,pp. 1412–1416.

[3] S.Antão, J.-C.Bajard, and L. Sousa, “RNS based elliptic curve point multiplication for massive parallel

architectures,” Comput. J.,vol. 55, no. 5, pp. 629–647, 2011.

[4] F. E. P. D. Gallaher and P. Srinivasan, “The digit parallel method for fast RNS to weighted number

system conversion for specific moduli {2n −1, 2n, 2n +1},” IEEE Trans. Circuits Syst. II, Analog Digit.

Signal Process. vol. 44, no. 1, pp. 53–57, Jan. 1997.

[5] P.Matutino, H. Pettenghi, R. Chaves, and L. Sousa, “RNS arithmetic units for modulo {2n± k},” in Proc.

15th Euromicro Conf. DSD, Sep. 2012, pp. 795–802.

[6] H. Pettenghi, L. Sousa, and J. Ambrose, “Efficient implementation of multi-moduli architectures for

binary-to-RNS conversion,” in Proc. 17th ASP-DAC Asia South Pacific, 2012, pp. 819–824.

[7] J. Low and C.-H. Chang, “A new approach to the design of efficient residue generators for arbitrary

moduli,” IEEE Trans. Circuits Syst., Reg. Papers, vol. 60, no. 9, pp. 2366–2374, Aug. 2013.

[8] A.Premkumar, E. Ang, and E.-K. Lai, “Improved memoryless RNS forward converter based on the

periodicity of residues,” IEEE Trans. Circuits Syst., Exp. Briefs, vol. 53, no. 2, pp. 133–137, Feb. 2006.

[9] P.M.Matutino, R. Chaves, and L. Sousa, “Theoretical analysis of modulo {2n ±k} units,” INESC-ID,

Lisbon, Portugal, Tech. Rep., 2013.

[10] P.M.Matutino, H.Pettenghi, R.Chaves, and L. Sousa, “Multiplier based binary-to-RNS converter modulo

{2n ±k},” in Proc. 26th Conf. DCIS, Nov. 2011, pp. 125–130.

AUTHORS

Ganji Sarika yadav received her B.Tech degree in Electronics & Communication Engineering

from SV Engineering College for Women, Tirupati (A.P), India, in the year 2013.Currently

pursuing her M.Tech degree in VLSI System Design at Chadalawada Ramanamma Engineering

College, Tirupati (A.P), India. Her area of research includes low power VLSI design.

Dr.V.THRIMURTHULU, M.E., Ph.D., MIETE, MISTE. Professor & Head of ECE Dept. He

received his Graduation in Electronics & Communication Engineering AMIETE in 1994 from

Institute of Electronics & Telecommunication Engineering, New Delhi, Post Graduation in

Engineering M.E specialization in Microwaves and Radar Engineering in the year Feb, 2003,

from University College of Engineering, Osmania University, Hyderabad., and his Doctorate

in philosophy Ph.D from central University, in the year 2012. He has done his research work

on Ad-Hoc Networks.

S.Ali Asgar was born in Tirupati, Andhra Pradesh, India. He received B.Tech degree in

Electronics and Instrumentation engineering from Sree Vidyanikethan engineering college,

A.Rangampeta in the year 2007. He did his M. Tech. in Digital Signals in 2012 from SJCET,

yemmiganur (A.P), India. He is currently working as Associate Professor in Chadalawada

Ramanamma Engineering College, Tirupati (A.P), and India.

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