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VME Data Acquisition System:Fundamentals and Beyond
Abhinav Kumar
Bhabha Atomic Research Centre, Mumbai
March 2011
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Chapter 1--------------------------------Introduction to VME
Chapter 2--------------------------------VME Architecture
Chapter 3--------------------------------Data Acquisition Setup under VME
Chapter 4
--------------------------------Data Acquisition with VME Modules using LAMPS
Presentation Outline
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Introduction to VME
VME stands for VERSA-Module Euro card
introduced in 1981 for industrial, commercial and
military applications.
Electrical and mechanical specifications are definedby the standard.
VME bus is a master-slave computer architecture.
The signaling scheme is asynchronous, meaning that
the transfer is not tied to the timing of a bus clock.
VITA (VME International Trade Association) is the
organisation whose purpose is to promote and
develop the VME
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VME Crate
smart fan units
VMEmaster VME slavepower supply
backplane
VME Components
Optical Link
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As the VME is an asynchronous bus, the bandwidth indicated is atheoretical limit. For VME64, It works to around 80 MB/s ofTheoretical maximum bandwidth ; usually the actual transfer rate isless than 50% of the bandwidth
High Readout Speeds
High Density Modules can provide up to 640 Channels (1 controller+ 20 Digitizers) in a single VME crate with 21 slots.
Usage of high bandwidth optical interconnect link makes sure thatthe interconnect technology doesnt become a bottleneck whiletransferring data.
Advantages of VME over CAMAC Standard
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Chapter 2--------------------------------
VME Architecture and
Protocols
/DS0, /DS1
/DTACK
DATA
ADDRESS
/AS
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MASTER
LWO
RD*
D[31
..0]
BER
R*
DTACK*
WRITE*
DS
0*
DS
1*
AS
*
AM[5..0]
IAC
K*
BCLR*
SYS
RESET*
ACFAIL*
SLAVE
BACKPLANE INTERFACE LOGIC
LWO
RD*
A[31
..1]
D[31
..0]
BER
R*
DTA
CK*
WRITE*
DS
0*
DS
1*
AS
*
AM[5..0]
IAC
K*
SYSRESET*
DATA TRANSFER BUS (DTB)
DTB ARBITRATION BUS
PRIORITY INTERRUPT BUS
UTILITY BUS
IRQ[7..1]*
IRQ[7..1]*
A[31
..1]
BBSY*
BG[3..0]IN*
BR[3
..0]*
SYSCLK
BG[3..0
]OUT*
VME Architecture
Electrical Properties
All lines use TTL levels ; Low = 0 .. 0.6 V; High = 2.4 .. 5 V
Address, Address Modifier and data lines are active high; Protocol
lines are active low.
* Active low signals
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Addressing modes - A16, A24, A32, A40, A64
The addressing mode and the access type are defined by the Address
Modifier bus AM[5:0]
AM Code Functions
0x3B A24 block transfer
0x39 A24 single cycle
0x2F CR/CSR space access
0x29 A16 single cycle
0x20 2eVME and 2eSST transfers (+ extended AM)
0x0B A32 block transfer (BLT)
0x09 A32 single cycle
0x08 A32 64-bit block transfer (MBLT)
VME Addressing Modes
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Address=BaseAddress + Offset
The maximum VME address space is made of 264 bytes (although in most
cases only 232 are used, since the A64 mode is very infrequent)
Each slave occupies a portion of this space, depending on its internal
addressing capability
There are 3 ways to allocate the address space of the slaves:
1. by the Base Address of the slaves which is set at hardware level by
means of jumpers or rotary switches
2. by the position of the slave in the crate (Geographical Address)
3. by the content of some registers of the slave programmed by the software(Address Relocation)
modes 2 and 3 are available in the VME64x only
VME Address Space
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Data readout is possible in following modes -
Single cycle
Reads a word from the slave FIFO
BLT/MBLT (Block Transfer/Multiplexed Block Transfer)
Reads a number of events limited to 256 words from any slave module
In MBLT two 32 bit words are multiplexed to read as a single 64-bit word in
VME64 standard
CBLT (Chained Block Transfer)
Most pertinent mode for nuclear physics applications allowing for event-
by-event data acquisition.
Reads the data belonging to the same physical event from several
contiguous boards in a crate limited to 256 words per CBLT cycle
VME Data Readout
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The Chained Block Transfer has been introduced for sparse
data readout across multiple modules.
It consists in reading the data belonging to the same physical
event from several contiguous boards in a crate.
It uses the IACKIN-IACKOUT daisy chain line already
present in any VME backplane to propagate the readout
token.
No additional hardware nor external connections are
required.
The CBLT is handled by the slaves and is transparent to the
master
The use of the Bus Error to terminate the cycle is mandatory.
Chained Block Transfer
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The Multi Cast Write (MCST) is a single write cycle that involves several
slaves in the crate.
The MCST uses the same propagation mechanism as the CBLT
The master initiates the cycle like a normal single write The slaves get the data in sequence and the last one asserts the DTACK
Multi Cast Write
Many VME acquisition boards use FIFO memories to store the data.
This is particularly suitable for physics applications in which the events occur
randomly in time and are readout sequentially
A read access to any address within that range causes the non repeatable
extraction of one word from the FIFO.
CAEN ADC modules are endowed with 32 Events Buffer.
FIFO Memories
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The VME features a 7 level prioritized interrupt architecture; the request
lines IRQ[7:1] are shared between all the slots
The interrupt is initiated by the interrupter(this can be any board in any
slot) that asserts one IRQ.
The interrupt handlers (usually the board in slot 1) monitor the IRQ
lines and generate an interrupt acknowledge cycle in response to the
request
The interrupt handler reads the STATUS/ID of the interrupter from the
data bus
If more interrupters had asserted the same IRQ line, the IACKIN-
IACKOUT daisy chain allows the uppermost left to respond first (priority
given by the position)
Interrupts in VME
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Chapter 3--------------------------------
Setting up a VME acquisition
system
C.A .E .N .
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It makes possible to control the VME bus remotely from a standardPC through a high speed link
The acquisition program (DAQ) runs on the remote PC
The VME board is just hardware (no software runs on it)
Computing power (processors, memories, disks, etc) is on the PC
Unlike the ethernet port of a SBC, the communication link of the bus
adapter must be able to sustain high data transfer rates
VME-PCI/PCIe: usually communicates through an optical link,requires a card inside the PC
Bus Adapter Feature
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HW and SW upgrade on PC side: you can buy a new one at any time
Easy getting started: just install a driver in the PC
Ready at power-up (no boot required)
Lower total cost of ownership Multi-crate interconnection and control
used for datatransfer
C . A . E . N .
Bus Adapter Slaves
USBOptical Link
computingpower ishere!
this is justhardware
access to thebus throughthe adapter
Advantages of Bus Adapter over SBC
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Max throughput rate: 70MB/s
VME64/VME64X (no 2eSST)
PCI 32bit, 33MHz
Optical Link: 1.25 Gb/s Max distance: 300m
FPGA
RAM
buffer
Optical
Link
VMEbus
FPGAOptical
Link
RAM
buffer
PCI bus
A2818
V2718
PCI-int
CONET
~ 70 MB/s
max 300m
VME Controller V2718
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BASE ADDRESS:
which board inside
the crate
OFFSET:
which register inside
the board
A32 mode
A24 mode
C 2 4 8
31 24 23 16 15 0
OFFSET
0 1
4
23
5
8
679
C
AB
DE
F 0 1
4
23
5
8
679
C
AB
DE
F 0 1
4
23
5
8
679
C
AB
DE
F 0 1
4
23
5
8
679
C
AB
DE
F
unused 4 8
31 24 23 16 15 0
OFFSET
0 1
4
23
5
8
679
C
AB
DE
F 0 1
4
23
5
8
679
C
AB
DE
F
Address Space: 16 Kbytesfrom 0xC2480000 to 0xC248FFFF
Address Space: 16 Kbytes
from 0x480000 to 0x48FFFF
VME Base Address ( Hardware Setting)
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Operational Aspects
Controller should beinserted in slot 1 of the
VME Crate.
While setting up the
CBLT Chain, the
modules forming thechain should be
contiguous; last module
should be terminated
with a 50 Ohm
resistance.
Scalars can be inserted
in any empty slot.
MesyTec ADCs, if used
along with CAENModules, should be
inserted first in the
chain.
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Chapter 4--------------------------------
Data Acquisition using VME
Modules through LAMPS software
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Software Installation
Installation of A2818 (PCI CONET Controller) driver
- CAEN A2818 PCI CARD
- Linux kernel Rel. 2.4 or 2.6 with gnu C/C++ compiler
Installation of CAENVMELib Library
Set of functions for the control and the use of CAEN VME
Bridges. Typically, it provides function calls to
Open (Init) and Close the communication and the devices Make single Read/Write cycles
Make Block Transfer Read/Write cycles
Wait for an interrupt and make a IACK cycle
Installation of LAMPS
No changes in the LAMPS installation procedure.
PCICONET
Controller
PCI Slot
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Checking for Basic Connectivity
Post hardware setup and software installation, basic connectivity with the Bus
Adapter can be checked using the Test Feature of the LAMPS software.
Indication of an error at this stage implies an incorrect hardware/software setup.
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Setup Configuration under LAMPS
Bus Adapter needs no Base Address configuration. For other modules, setting
up of Base Address in software is compulsory.
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Setting up Special Properties
Configuring SCALERS
under LAMPS
TDC special settings
QDC special
settings
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Blue Rectangular region VME Controller ; Green Rectangular Region- CBLT
Chain ; Purple rectangular region - Scaler
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Master Gate Blocking
Master Gate blocking is essential to have any meaningful acquisition with VME, failing
which a good number of events could be corrupt depending on the data rate.
Concept:
No master gate should reach VME modules until the current event has been completelydigitized and read out. This statement may look incomplete because it doesnt talk of the
32-event buffer in VME modules. But the solution (see below) is based on BUSY status of
VME modules, hence it covers this complication.
Solution:
Chain the BUSY output from all the modules in use using short Lemo cables and Lemo Tconnectors and veto the master gate of the experiment with this before input to VME
modules.
LAMPS automatically displays the dead time when the blocked and unblocked master
gates are provided on two inputs of CAEN V830 VME scaler module.
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Conclusion
The VME DAQ in the current form provides us with a powerful system
because of the large number of parameters which can be acquired
simultaneously and high event rates.
The zero suppressed readout option along with the availability of variety of
digitizers with higher channel density presents a very good system in front of
users, before we eventually migrate to digital DAQ.