VLSI
-
Upload
vishal-kureel -
Category
Documents
-
view
88 -
download
0
Transcript of VLSI
8
VLSI
PRACTICAL
FILE
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A PMOS TRANSISTOR AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M1 1 4 2 1 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (11 17 13 23)
VDD 2 0 5V
VGG 3 0 0V
VDS 1 0
VGS 4 0
.DC VGS 0V 5V 0.1V
.PRINT DC Id(M1)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A NMOS TRANSISTOR AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M1 1 4 2 1 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (11 -4 13 2)
VSS 2 0 5V
VDD 1 0 0V
VGS 4 0
.DC VGS 0V 5V 0.1V
.include "C:\Tanner\TSpice70\models\ml2_125.md"
.PRINT DC Id(M1)
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A CMOS INVERTOR AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M2 4 1 3 6 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M2 DRAIN GATE SOURCE BULK (11 17 13 23)
M1 4 1 2 5 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (11 -4 13 2)
VDD 3 0 5V
VSS 2 0 0V
VEE 6 0 5V
VFF 5 0 0V
VGS 1 0 0V
.DC VGS 0V 5V 0.1V
.PRINT DC 4
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A TRANSMISSION GATE CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M2 4 1 3 6 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M2 DRAIN GATE SOURCE BULK (11 5 13 11)
M1 4 2 3 5 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (11 -12 13 -6)
VPP 6 0 5V
VNN 5 0 0V
VIN 3 0 BIT({0101})
VAA 2 0 BIT({0011})
VA0 1 0 BIT({1100})
.TRAN 100ns 200ns
.PRINT V(1) V(2) V(3) V(4)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A NAND GATE AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M4 4 1 5 8 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M4 DRAIN GATE SOURCE BULK (8 17 10 23)
M3 4 2 5 8 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M3 DRAIN GATE SOURCE BULK (0 17 2 23)
M2 7 1 3 6 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M2 DRAIN GATE SOURCE BULK (8 -2 10 4)
M1 4 2 7 6 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (0 -2 2 4)
VDD 5 0 5V
VPP 8 0 5V
VNN 6 0 0V
VGG 3 0 0V
VAA 1 0 bit({0011})
VBB 2 0 bit({0101})
.tran 100ns 200ns
.print 4 V(1) V(2)
FILE BY HTTP://TECHBITS.CO.IN/
8
.include "C:\Tanner\TSpice70\models\ml2_125.md"
AIM:
TO DESIGN A NOR GATE AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M4 8 1 4 7 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M4 DRAIN GATE SOURCE BULK (0 17 2 23)
M3 5 2 8 7 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M3 DRAIN GATE SOURCE BULK (8 17 10 23)
M2 5 1 3 6 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M2 DRAIN GATE SOURCE BULK (0 -2 2 4)
M1 5 2 3 6 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M1 DRAIN GATE SOURCE BULK (8 -2 10 4)
VDD 4 0 5V
VPP 7 0 5V
VGG 3 0 0V
VNN 6 0 0V
VAA 1 0 BIT({0011})
VBB 2 0 BIT({0101})
.TRAN 100ns 200ns
.print 5 V(1) V(2)
FILE BY HTTP://TECHBITS.CO.IN/
8
.include "C:\Tanner\TSpice70\models\ml2_125.md"
AIM:
TO DESIGN A XOR GATE AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M8 2 4 1 12 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M8 DRAIN GATE SOURCE BULK (24 17 26 23)
M7 2 5 1 12 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M7 DRAIN GATE SOURCE BULK (16 17 18 23)
M6 1 7 6 12 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M6 DRAIN GATE SOURCE BULK (0 17 2 23)
M5 1 8 6 12 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M5 DRAIN GATE SOURCE BULK (8 17 10 23)
M4 11 4 3 10 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M4 DRAIN GATE SOURCE BULK (24 -14 26 -8)
M3 2 5 11 10 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M3 DRAIN GATE SOURCE BULK (16 -14 18 -8)
M2 9 7 3 10 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
FILE BY HTTP://TECHBITS.CO.IN/
8
* M2 DRAIN GATE SOURCE BULK (0 -14 2 -8)
M1 2 8 9 10 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M1 DRAIN GATE SOURCE BULK (8 -14 10 -8)
VPP 12 0 5V
VDD 6 0 5V
VNN 10 0 0V
VGG 3 0 0V
VBB 7 0 BIT({0101})
VAA 8 0 BIT({0011})
VAO 5 0 BIT({1100})
VBO 4 0 BIT({1010})
.TRAN 100ns 200ns
.PRINT 2 V(7) V(8)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A XNOR GATE AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M8 2 4 1 12 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M8 DRAIN GATE SOURCE BULK (24 17 26 23)
M7 2 5 1 12 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M7 DRAIN GATE SOURCE BULK (16 17 18 23)
M6 1 7 6 12 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M6 DRAIN GATE SOURCE BULK (0 17 2 23)
M5 1 8 6 12 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M5 DRAIN GATE SOURCE BULK (8 17 10 23)
M4 11 4 3 10 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M4 DRAIN GATE SOURCE BULK (24 -14 26 -8)
M3 2 5 11 10 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M3 DRAIN GATE SOURCE BULK (16 -14 18 -8)
M2 9 7 3 10 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
FILE BY HTTP://TECHBITS.CO.IN/
8
* M2 DRAIN GATE SOURCE BULK (0 -14 2 -8)
M1 2 8 9 10 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M1 DRAIN GATE SOURCE BULK (8 -14 10 -8)
VPP 12 0 5V
VDD 6 0 5V
VNN 10 0 0V
VGG 3 0 0V
VBO 7 0 BIT({1010})
VAA 8 0 BIT({0011})
VAO 5 0 BIT({1100})
VBB 4 0 BIT({0101})
.TRAN 100ns 200ns
.PRINT 2 V(4) V(8)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A HALF ADDER CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M12 2 4 1 14 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M12 DRAIN GATE SOURCE BULK (56 17 58 23)
M11 1 5 7 14 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M11 DRAIN GATE SOURCE BULK (48 17 50 23)
M10 2 6 1 14 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M10 DRAIN GATE SOURCE BULK (64 17 66 23)
M9 5 8 7 14 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M9 DRAIN GATE SOURCE BULK (28 17 30 23)
M8 8 9 7 14 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M8 DRAIN GATE SOURCE BULK (8 17 10 23)
M7 8 10 7 14 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M7 DRAIN GATE SOURCE BULK (0 17 2 23)
M6 2 4 13 12 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
FILE BY HTTP://TECHBITS.CO.IN/
8
* M6 DRAIN GATE SOURCE BULK (56 -2 58 4)
M5 2 5 3 12 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M5 DRAIN GATE SOURCE BULK (48 -2 50 4)
M4 13 6 3 12 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M4 DRAIN GATE SOURCE BULK (64 -2 66 4)
M3 5 8 3 12 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M3 DRAIN GATE SOURCE BULK (28 -2 30 4)
M2 11 9 3 12 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M2 DRAIN GATE SOURCE BULK (8 -2 10 4)
M1 8 10 11 12 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (0 -2 2 4)
VPP 14 0 5V
VDD 7 0 5V
VNN 12 0 0V
VGG 3 0 0V
VAA 10 0 BIT({0011})
VBB 9 0 BIT({0101})
VAO 4 0 BIT({1100})
VBO 6 0 BIT({1010})
.TRAN 100ns 200ns
.PRINT V(2) V(5) V(9) V(10)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A HALF SUBTRACTOR CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M14 3 2 1 15 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M14 DRAIN GATE SOURCE BULK (84 17 86 23)
M13 2 6 5 15 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M13 DRAIN GATE SOURCE BULK (56 17 58 23)
M12 5 7 1 15 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M12 DRAIN GATE SOURCE BULK (48 17 50 23)
M11 2 8 5 15 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M11 DRAIN GATE SOURCE BULK (64 17 66 23)
M10 7 9 1 15 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M10 DRAIN GATE SOURCE BULK (28 17 30 23)
M9 9 10 1 15 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M9 DRAIN GATE SOURCE BULK (8 17 10 23)
M8 9 11 1 15 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
FILE BY HTTP://TECHBITS.CO.IN/
8
* M8 DRAIN GATE SOURCE BULK (0 17 2 23)
M7 3 2 4 14 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M7 DRAIN GATE SOURCE BULK (84 -2 86 4)
M6 2 6 13 14 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M6 DRAIN GATE SOURCE BULK (56 -2 58 4)
M5 2 7 4 14 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M5 DRAIN GATE SOURCE BULK (48 -2 50 4)
M4 13 8 4 14 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M4 DRAIN GATE SOURCE BULK (64 -2 66 4)
M3 7 9 4 14 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M3 DRAIN GATE SOURCE BULK (28 -2 30 4)
M2 12 10 4 14 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M2 DRAIN GATE SOURCE BULK (8 -2 10 4)
M1 9 11 12 14 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (0 -2 2 4)
VPP 15 0 5V
VDD 1 0 5V
VNN 14 0 0V
VGG 4 0 0V
VX0 11 0 BIT({1100})
VYY 10 0 BIT({0101})
VYO 8 0 BIT({1010})
VXX 6 0 BIT({0011})
.TRAN 100ns 200ns
.PRINT V(3) V(7) V(6) V(10)
FILE BY HTTP://TECHBITS.CO.IN/
8
.include "C:\Tanner\TSpice70\models\ml2_125.md"
AIM:
TO DESIGN A SR LATCH CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M12 6 3 2 13 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M12 DRAIN GATE SOURCE BULK (0 17 2 23)
M11 3 6 1 13 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M11 DRAIN GATE SOURCE BULK (36 17 38 23)
M10 1 7 5 13 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M10 DRAIN GATE SOURCE BULK (52 17 54 23)
M9 2 7 5 13 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M9 DRAIN GATE SOURCE BULK (16 17 18 23)
M8 1 9 5 13 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M8 DRAIN GATE SOURCE BULK (44 17 46 23)
M7 2 8 5 13 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M7 DRAIN GATE SOURCE BULK (8 17 10 23)
M6 6 3 4 12 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
FILE BY HTTP://TECHBITS.CO.IN/
8
* M6 DRAIN GATE SOURCE BULK (0 -8 2 -2)
M5 3 6 4 12 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M5 DRAIN GATE SOURCE BULK (36 -8 38 -2)
M4 11 7 4 12 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M4 DRAIN GATE SOURCE BULK (52 -8 54 -2)
M3 10 7 4 12 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M3 DRAIN GATE SOURCE BULK (16 -8 18 -2)
M2 3 9 11 12 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M2 DRAIN GATE SOURCE BULK (44 -8 46 -2)
M1 6 8 10 12 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M1 DRAIN GATE SOURCE BULK (8 -8 10 -2)
VPP 13 0 5V
VDD 5 0 5V
VNN 12 0 0V
VGG 4 0 0V
VCK 7 0 BIT({000111})
VSS 9 0 BIT({001001})
VRR 8 0 BIT({010010})
.TRAN 100ns 200ns
.PRINT V(6) V(7) V(8) V(9)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A D LATCH CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M8 4 5 8 11 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M8 DRAIN GATE SOURCE BULK (23.5 48 25.5 54)
M7 3 7 4 10 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M7 DRAIN GATE SOURCE BULK (64 7.5 66 13.5)
M6 3 6 1 11 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M6 DRAIN GATE SOURCE BULK (77.5 48 79.5 54)
M5 6 4 1 11 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M5 DRAIN GATE SOURCE BULK (50.5 48 52.5 54)
M4 3 5 4 9 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M4 DRAIN GATE SOURCE BULK (64 -9.5 66 -3.5)
M3 4 7 8 9 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M3 DRAIN GATE SOURCE BULK (23.5 31 25.5 37)
M2 3 6 2 9 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
FILE BY HTTP://TECHBITS.CO.IN/
8
* M2 DRAIN GATE SOURCE BULK (77.5 31 79.5 37)
M1 6 4 2 9 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (50.5 31 52.5 37)
VP1 11 0 5V
VP2 10 0 5V
VDD 1 0 5V
VNN 9 0 0V
VGG 2 0 0V
VCK 7 0 BIT({0011})
VCB 5 0 BIT({1100})
VDL 8 0 BIT({0101})
.TRAN 100ns 200ns
.PRINT V(3) V(7) V(8)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A FULL ADDER CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M30 1 8 6 23 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M30 DRAIN GATE SOURCE BULK (105 40.5 107 46.5)
M29 5 19 6 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M29 DRAIN GATE SOURCE BULK (53 40.5 55 46.5)
M28 8 13 11 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M28 DRAIN GATE SOURCE BULK (77 40.5 79 46.5)
M27 11 13 4 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M27 DRAIN GATE SOURCE BULK (69 40.5 71 46.5)
M26 8 14 11 23 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M26 DRAIN GATE SOURCE BULK (85 40.5 87 46.5)
M25 4 14 5 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M25 DRAIN GATE SOURCE BULK (61 40.5 63 46.5)
M24 11 12 6 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
FILE BY HTTP://TECHBITS.CO.IN/
8
* M24 DRAIN GATE SOURCE BULK (45 40.5 47 46.5)
M23 1 8 7 17 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M23 DRAIN GATE SOURCE BULK (105 9.5 107 15.5)
M22 8 19 3 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M22 DRAIN GATE SOURCE BULK (53 9.5 55 15.5)
M21 10 13 7 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M21 DRAIN GATE SOURCE BULK (77 9.5 79 15.5)
M20 2 13 7 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M20 DRAIN GATE SOURCE BULK (69 9.5 71 15.5)
M19 10 14 7 17 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M19 DRAIN GATE SOURCE BULK (85 9.5 87 15.5)
M18 2 14 3 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M18 DRAIN GATE SOURCE BULK (61 9.5 63 15.5)
M17 8 12 10 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M17 DRAIN GATE SOURCE BULK (45 9.5 47 15.5)
M16 24 19 6 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M16 DRAIN GATE SOURCE BULK (-21 40.5 -19 46.5)
M15 22 19 21 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M15 DRAIN GATE SOURCE BULK (-37 40.5 -35 46.5)
M14 12 13 20 23 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M14 DRAIN GATE SOURCE BULK (-5 40.5 -3 46.5)
M13 21 13 6 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M13 DRAIN GATE SOURCE BULK (-29 40.5 -27 46.5)
M12 8 19 11 23 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M12 DRAIN GATE SOURCE BULK (37 40.5 39 46.5)
FILE BY HTTP://TECHBITS.CO.IN/
8
M11 20 14 24 23 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M11 DRAIN GATE SOURCE BULK (-13 40.5 -11 46.5)
M10 12 14 22 23 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M10 DRAIN GATE SOURCE BULK (-45 40.5 -43 46.5)
M9 9 12 6 23 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M9 DRAIN GATE SOURCE BULK (17 40.5 19 46.5)
M8 18 19 7 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M8 DRAIN GATE SOURCE BULK (-21 9.5 -19 15.5)
M7 12 19 16 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M7 DRAIN GATE SOURCE BULK (-37 9.5 -35 15.5)
M6 12 13 15 17 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M6 DRAIN GATE SOURCE BULK (-5 9.5 -3 15.5)
M5 12 13 18 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M5 DRAIN GATE SOURCE BULK (-29 9.5 -27 15.5)
M4 10 19 7 17 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M4 DRAIN GATE SOURCE BULK (37 9.5 39 15.5)
M3 15 14 7 17 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M3 DRAIN GATE SOURCE BULK (-13 9.5 -11 15.5)
M2 16 14 7 17 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M2 DRAIN GATE SOURCE BULK (-45 9.5 -43 15.5)
M1 9 12 7 17 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (17 9.5 19 15.5)
VPP 23 0 5V
VDD 6 0 5V
FILE BY HTTP://TECHBITS.CO.IN/
8
VNN 17 0 0V
VGG 7 0 0V
VAA 19 0 BIT({00001111} pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
VBB 14 0 BIT({00110011} pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
VCI 13 0 BIT({01010101} pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
.TRAN 100ns 200ns
.PRINT V(1) V(9) V(13) V(14) V(19)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
AIM:
TO DESIGN A FULL SUBTRACTOR CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER TOOL
PROGRAM:
T-SPICE CODE
M30 14 8 10 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M30 DRAIN GATE SOURCE BULK (45 40.5 47 46.5)
M29 12 1 14 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M29 DRAIN GATE SOURCE BULK (77 40.5 79 46.5)
M28 14 1 7 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M28 DRAIN GATE SOURCE BULK (69 40.5 71 46.5)
M27 12 2 14 27 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M27 DRAIN GATE SOURCE BULK (85 40.5 87 46.5)
M26 7 2 6 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M26 DRAIN GATE SOURCE BULK (61 40.5 63 46.5)
M25 3 12 10 27 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M25 DRAIN GATE SOURCE BULK (105 40.5 107 46.5)
M24 6 9 10 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
FILE BY HTTP://TECHBITS.CO.IN/
8
* M24 DRAIN GATE SOURCE BULK (53 40.5 55 46.5)
M23 12 8 13 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M23 DRAIN GATE SOURCE BULK (45 9.5 47 15.5)
M22 13 1 11 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M22 DRAIN GATE SOURCE BULK (77 9.5 79 15.5)
M21 5 1 11 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M21 DRAIN GATE SOURCE BULK (69 9.5 71 15.5)
M20 13 2 11 22 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M20 DRAIN GATE SOURCE BULK (85 9.5 87 15.5)
M19 4 2 5 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M19 DRAIN GATE SOURCE BULK (61 9.5 63 15.5)
M18 3 12 11 22 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M18 DRAIN GATE SOURCE BULK (105 9.5 107 15.5)
M17 12 9 4 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M17 DRAIN GATE SOURCE BULK (53 9.5 55 15.5)
M16 12 9 14 27 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M16 DRAIN GATE SOURCE BULK (37 40.5 39 46.5)
M15 15 16 26 27 PMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M15 DRAIN GATE SOURCE BULK (-5 40.5 -3 46.5)
M14 25 16 10 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M14 DRAIN GATE SOURCE BULK (-29 40.5 -27 46.5)
M13 26 17 24 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M13 DRAIN GATE SOURCE BULK (-13 40.5 -11 46.5)
M12 15 17 23 27 PMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M12 DRAIN GATE SOURCE BULK (-45 40.5 -43 46.5)
FILE BY HTTP://TECHBITS.CO.IN/
8
M11 24 18 10 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M11 DRAIN GATE SOURCE BULK (-21 40.5 -19 46.5)
M10 23 18 25 27 PMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M10 DRAIN GATE SOURCE BULK (-37 40.5 -35 46.5)
M9 8 15 10 27 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M9 DRAIN GATE SOURCE BULK (17 40.5 19 46.5)
M8 13 9 11 22 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M8 DRAIN GATE SOURCE BULK (37 9.5 39 15.5)
M7 15 16 21 22 NMOS L=2u W=6u AD=36p PD=24u AS=18p PS=12u
* M7 DRAIN GATE SOURCE BULK (-5 9.5 -3 15.5)
M6 15 16 20 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M6 DRAIN GATE SOURCE BULK (-29 9.5 -27 15.5)
M5 21 17 11 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M5 DRAIN GATE SOURCE BULK (-13 9.5 -11 15.5)
M4 19 17 11 22 NMOS L=2u W=6u AD=18p PD=12u AS=36p PS=24u
* M4 DRAIN GATE SOURCE BULK (-45 9.5 -43 15.5)
M3 20 18 11 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M3 DRAIN GATE SOURCE BULK (-21 9.5 -19 15.5)
M2 15 18 19 22 NMOS L=2u W=6u AD=18p PD=12u AS=18p PS=12u
* M2 DRAIN GATE SOURCE BULK (-37 9.5 -35 15.5)
M1 8 15 11 22 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u
* M1 DRAIN GATE SOURCE BULK (17 9.5 19 15.5)
VPP 27 0 5V
VDD 10 0 5V
FILE BY HTTP://TECHBITS.CO.IN/
8
VNN 22 0 0V
VGG 11 0 0V
VXX 9 0 BIT({00001111}pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
VYY 17 0 BIT({00110011}pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
VZZ 16 0 BIT({01010101}pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
VXI 18 0 BIT({11110000}pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
VYI 2 0 BIT({11001100}pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
VZI 1 0 BIT({10101010}pw=20n on=3.0 off=0.0 rt=1.25n ft=1.25n)
.TRAN 100ns 200ns
.PRINT V(3) V(8) V(9) V(16) V(17)
.include "C:\Tanner\TSpice70\models\ml2_125.md"
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF PMOS TRANSISTOR
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR DC CHARACTERISTICS OF PMOS TRANSISTOR
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF NMOS TRANSISTOR
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR DC CHARACTERISTICS OF NMOS TRANSISTOR
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF CMOS INVERTOR
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR DC CHARACTERISTICS OF CMOS INVERTOR
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF TRANSMISSION GATE CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
TRANSMISSION GATE CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF NAND GATE
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
NAND GATE
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF NOR GATE
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
NOR GATE
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF XOR GATE
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
XOR GATE
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF XNOR GATE
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
XNOR GATE
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF HALF ADDER CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
HALF ADDER CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF HALF SUBTRACTOR CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
HALF SUBTRACTOR CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF SR LATCH CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
SR LATCH CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF D LATCH CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
D LATCH CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF FULL ADDER CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
FULL ADDER CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
LAYOUT DESIGN OF FULL SUBTRACTOR CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF
FULL SUBTRACTOR CIRCUIT
FILE BY HTTP://TECHBITS.CO.IN/
8
FILE BY HTTP://TECHBITS.CO.IN/