VLSI Systems and Embedded Architectures
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10/6/99 HPVSA Laboratory, University at Buffalo 1 VLSI Systems and Embedded Architectures Ramalingam Sridhar High Performance VLSI Systems & Architecture Laboratory 215 Furnas Hall Dept of Computer Science & Engineering University at Buffalo Email: [email protected]
Transcript of VLSI Systems and Embedded Architectures
10/6/99 HPVSA Laboratory, University at Buffalo 1
VLSI Systems and EmbeddedArchitectures
Ramalingam SridharHigh Performance VLSI Systems & Architecture Laboratory
215 Furnas Hall
Dept of Computer Science & Engineering
University at Buffalo
Email: [email protected]
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Automation
• Process Automation
• Office Automation
• Home Automation
• Automobile Automation
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Home Automation
• Fully wired environment
• Standards emerging
• Network standard for Home Audio/Visual electronics thatwill connect seemlessly and interoperate
• Appliances control standard (networked appliances)
• Phone line standards & network protocol for multiplecomputers to share peripherals and a single internetconnection
• Set top TV Boxes
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Automobile Automation
• Mobile environment with in-vehicle networks withinternet, wireless links, personal communication devices,entertainment electronics and traditional car systemsconverge
• Integration of GPS into various functions
• Digital systems with 100Mbps network for video will be arequirement.
• Embedded systems have already transformed anautomobile
• Automobile Multimedia Interface Collaboration (AMIC)
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Environment
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Basic Requirements for Software
• Portability (external application software)• Interoperability (remote service, network adaptation)• Processing Architecture Flexibility• Failsafe Operation• Security• Plug and Run(Play)• Upgradeability• Serviceability• Internationalization Support• Functions of API
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Embedded systems
• Embedded processors and control hardware
• Remote diagnostics of appliances anddevices
• Easy access to vast database of knowledge
• Science fiction scenario is now a reality
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Enabling Technologies
• Sensors– Used extensively in automation, in particular in
automobiles
• Integration of Sensors with conventionalelectronics
• Extraordinary computing power on the palmtip is possible by the extraordinary progressin VLSI Technology
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Moore’s Law
• Gordon Moore: co-founder of Intel.
• Predicted that number of transistors per chipwould grow exponentially (double every 18months).
• Exponential improvement in technology is anatural trend: steam engines, dynamos,automobiles.
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Moore’s Law
‘70‘70 ‘74‘74 ‘78 ‘82‘78 ‘82 ‘86‘86 ‘90‘90 ‘94‘94 ‘98 2002 ‘98 2002
1 B1 B
100 M100 M
10 M10 M
1 M1 M
100 K100 K
10 K10 K
1 K1 K
••6800 = 4K6800 = 4K
••8086 = 28K8086 = 28K
••68000 = 68K68000 = 68K
••286 = 134K286 = 134K•• 386DX = 275K 386DX = 275K
••486DX = 1.2M486DX = 1.2M•• Pentium = 3.3M Pentium = 3.3M
••Pentium Pro = 5.5MPentium Pro = 5.5M
••Power PC 620 = 6.9MPower PC 620 = 6.9M
Source: Intel, VLSI Research, Inc.Source: Intel, VLSI Research, Inc.
* In 1965 Gordon Moore predicted that the number of transistors on processors would* In 1965 Gordon Moore predicted that the number of transistors on processors woulddouble every two years. His prediction has proven remarkably accurate so far.double every two years. His prediction has proven remarkably accurate so far.
••“Merced” = 16M“Merced” = 16M
Tra
nsi
sto
rs p
er c
hip
Tra
nsi
sto
rs p
er c
hip
•• 8080 = 6K 8080 = 6K
••UltraSparcUltraSparc III-330 mm III-330 mm sqsq//
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Silicon in 2010
Die Area: 2.5x2.5 cmVoltage: 0.6 VTechnology: 0.07 µµm
Density Access Time(Gbits/cm2) (ns)
DRAM 8.5 10DRAM (Logic) 2.5 10SRAM (Cache) 0.3 1.5
Density Max. Ave. Power Clock Rate(Mgates/cm2) (W/cm2) (GHz)
Custom 25 54 3Std. Cell 10 27 1.5
Gate Array 5 18 1Single-Mask GA 2.5 12.5 0.7
FPGA 0.4 4.5 0.25
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NTRS Adjusted Roadmap
SemaTechSemaTechNTRSNTRS
Supply voltageSupply voltage
Metal layersMetal layers
Short wire pitchShort wire pitch
Clock Clock freqfreq..
InterconnectInterconnectpitchpitch
199519950.350.35µµµµmm
3.3V3.3V
44
0.70 -1.050.70 -1.05µµµµmm
300 MHz300 MHz
1.01.0µµµµmm
199819980.250.25µµµµmm
2.5V2.5V
55
0.65 - 0.900.65 - 0.90µµµµmm
450 MHz450 MHz
0.80.8µµµµmm
200020000.180.18µµµµmm
1.8V1.8V
66
0.50 -0.800.50 -0.80µµµµmm
800 MHz800 MHz
0.60.6µµµµmm
200220020.130.13µµµµmm
1.5V1.5V
66
0.35 - 0.650.35 - 0.65µµµµmm
1 1 GHzGHz
0.420.42µµµµmm
200420040.100.10µµµµmm
1.2V1.2V
77
0.20- 0.500.20- 0.50µµµµmm
1.4 1.4 GHzGHz
0.280.28µµµµmm
Recent announcements (Aug- Sep 98)Recent announcements (Aug- Sep 98)* TI - 0.10-micron CMOS, 400 million * TI - 0.10-micron CMOS, 400 million txtx, Volume , Volume prodnprodn.- .- Yr Yr 20012001* Sun Micro * Sun Micro UltraSparcUltraSparc III - 600MHz, 70W, 300 mm III - 600MHz, 70W, 300 mm sqsq..
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VLSI Chip in Year 2005
• Updated International TechnologyRoadmap:
• Min feature size 0.1micrometer
• Total no. of transistors 200 million
• Number of logic transistors 40 million
• Clock frequency 2.0-3.5GHz
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1998 ITRS Technology Characteristics
1997 1999 2002 2005 2008
Technology Node(nm) 250 180 130 100 70
Memory ( Bit per chip) 256M 1G 4G 16G 64G
Transistors per chip (MPU) 11M 21M 76M 200M 520M
Pins/Balls (ASIC) 1130 1400 1915 2619 3581
Chip Frequency (MHz) 750 1250 2100 3500 6000
Wiring Levels (Max) 6 6-7 7 7-8 ----
Power Supply Voltage (VDD) 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9
Power (W)-High performance 70 90 130 160 170
Power (W)-Hand held 1.2 1.4 2 2.4 2.8
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SIA’s “Design Productivity Crisis”
Source: Semiconductor Industry Association
100,000,000
1,000,000
10,000
100
10,000,000
100,000
1,000
10
1981
1985
1989
1993
1997
2001
2005
2009
Moore’sMoore’sLawLaw
Transistors/chip(without memory)
Transistors designed/staff month
EngineeringEngineeringProductivityProductivity
TrendTrend
Limit to Limit to Adding Skilled Adding Skilled
EngineersEngineers
GapGap
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The International Technology RoadmapFor Semiconductors
The ITRS Identifies Several “Major Roadblocks”
• The ability to continue affordable scaling --• Affordable lithography at and below 100nm --• New materials and structures• Multi-GHz frequency operation on-and off-chip --timing, interconnect, package…• Metrology and test -- broad spectrum of new approaches are required• The research and development challenge -- how to organize, how to fund
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MAJOR ROADBLOCKS
Affordable Device Scaling
•Feature sizes must continue to shrink in order to maintain 25-30% per year productivity increase
•Increasing number of transistors per square centimeter and increasing speed presents design and interconnect problems
•Design, test and interconnect become limiting technologies
•Costs and complexity are escalating rapidly
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Electronics Industry
• Achieved SuccessfulPenetration in DiverseDomains
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High Complexity: Mixed Technologies
• Embed in a single chip:Logic, Analog, DRAMblocks
• Embed advancedtechnology blocks:– FPGA, Flash,
RF/Microwave
• Beyond Electronic– MEMS
– Optical elements
LOGICLOGIC
FPGAFPGA
DRAM
SR
AM
LOGIC
FLASHFLASH
RF
Analog
Logic
ANALOGANALOG
DRAMDRAM
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Electronics Industry
• Met User Quality Requirements– satisfying users to buy products again
Created an UnprecedentedDependency
- market-driven product Users want
ElectronicProduct
Compe
titor
s
Users
“Better, Cheaper, Smaller,Faster ”
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Market-Driven Industry Trends
• Cause emergence of SOC Technology:Greater Complexity
Increased Performance
Higher Density
Lower Power Dissipation
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SoC is Revolutionizing the ElectronicsIndustry
RAM
ROM
DSPCore
µP
Modem &Multimedia
Blocks
Analog/MixedSignal
Software+
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“Real”“Real”ComponentComponent
System System on Boardon Board
ComponentComponentbased designbased design
“Virtual” “Virtual” ComponentComponent
System-System-on-a-Chipon-a-Chip
Courtesy: VSI AllianceCourtesy: VSI Alliance
SOC Definition
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SOC Application Drivers• Boom in communications, multimedia and
consumer electronics
• Examples:– CISCO 700 Router: 32-bit MIPS R5000+
ASICs + 6Mb RAM
– Digital camcorder: 16-bit processor + CCDarray + A/D converter + 4-layer board
– Digital TV, Digital set-top box
– PC add-on cards (Sound blaster)
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System(s)-on-a chip
• SOC introduces reuse of IP blocks
• Due to the complexity of designing theentire chip, the design becomes managingvarious building blocks and building largercomprehensive chips from these blocks.
• More reliance on the software verificationand simulation, than ever before.
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System on chip
• System on chip opens the way for amultitude of electronics products noteconomically feasible before.
• SOC technology holds the key toincreasingly complex applications byenabling high-performance, embeddedprocessing solutions at a low, single-chipcost.
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SIP SecuritySIP Security
• Patents, copyrights, trade secrets, maskworks,trademarks
• Public key cryptography
• License management on networks
• Digital fingerprinting– Digital signature for cores
• Watermarking
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DSM - Shift in Problems and Priorities
Source: Dataquest
1.0 0.8 0.7 0.5 0.35 0.25 0.18
Area
Speed
Power
Metal-Migration
SignalIntegrity
EMI
4444
4444
4444
44444444
l 1.0 Micron - Area, Speedl 0.8 Micron - Speed, Areal 0.7/.6 Micron - Speed, Area, Powerl 0.5 Micron - Speed, Power, Area 44
4444
4444 44
44
44
44
44 44 44
44
44
l 0.35 Micron - Speed, Power, Area metal migrationl 0.25 Micron - Speed, Metal-Migration, Power, Signal-Integrity, Areal 0.18 Micron - Speed, Metal-Migration, Power, Signal-Integrity, EMI
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==
“Today it costs about $100 million, or about $16 pertransistor, to develop a 6 million transistor chip. In 2005chips will contain 300-400 million transistors. Ifproductivity remains flat between now and then,developing such chips will cost in the $6-8 billionrange… the same cost as developing a Boeing 777.
??
Hector J. Ruiz, President Motorola SPS
Design Reuse is Essential
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Virtual Prototyping DirectionsDESIGNDESIGN
Dataquest 998
Embedded
Software
ESL TestESL Test
RTLTest
Bench
FormalAnalysis
Cycle-BasedSimulation
Mixed-SignalSimulation
VHDL & Verilog Sim
VERIFICATIONVERIFICATION
StaticTimingStaticTiming
Hard
ware/S
oftw
areH
ardw
are/So
ftware
Virtu
al Pro
totyp
eV
irtual P
roto
type
FormalVerification
Logic SynthesisEmulation
DFTDFTRTL Floor plannerRTL Floor planner
TimingTiming PowerPowerSignal-IntegritySignal-Integrity EMIEMI Metal-MigrationMetal-Migration
RTL Virtual Prototype
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Design challenges
• Can the Moore’s law hold good in the future.
• Shrinking transistors => testing the physical limits
• Increasing speed results in increased power
• Achieving low power even with increased speed
• Due to System-on-chip, we have powerful functionsincluding computing designed to the size of a postagestamp, which makes useful and extraordinary mobileapplications possible.
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Areas of Research
• Digital Systems, Computer architecture &VLSI Systems– focus on deep sub-micron design, interconnect
issues, silicon IP and low power
– applications to multimedia, communication andDSP
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VLSI Systems
• CMOS Designs– low feature size (0.18micron from 3micron
in’85), moving towards 0.1micron
– input pattern dependence on delays and power
– dependence on previous states of the output
• Deep sub-micron designs– reaching physical limitations
– better modeling & simulations
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Power
• Power consumption in CMOS– Supply voltage; threshold voltage
– speed
– switching
• Power minimization at higher level– instruction reordering
– compiler level optimization & algorithmicmodifications
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Interconnect issues
• Dominance of Interconnect wires indetermining the performance
• logic-based design emphasis to interconnectwire based design
• routing, placement and delays impact theperformance
• Clock distribution networks and skews
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Interconnects
• Architectural design impact due tointerconnect dominance
• Clocking and synchronization issues
• synchronous and asynchronous interface
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Silicon IP
• System on a Chip (SOC)– mobile phones and powerful gadgets
– Example: DSP, processor, communicationmodules; RF circuit blocks all in a cell phone
• Encryption, watermarking methods
• design integration; simulation andapplication of unique design methods forlow power
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Current Projects & Interest
• Circuit techniques and designs for low level high speedpipelining
• clocking & synchronization issues in SIP
• impact of interconnect behavior on clocking; synchronous& asynchronous circuits and their interface
• Embedded cores with special application to multimedia,communication & signal processing
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Project..
• Power minimization– higher level power minimization
– power modeling
– delay modeling
• Hardware semantics to model a processoroperations (at low level) to evaluatearchitectural features
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JOBS
• Intel Corporation
• Sun Microsystems
• Sun Microelectronics
• Lockheed Martin
• IBM
• Allied Signals
• Motorola and more ...
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Ramalingam Sridhar
Email: [email protected]
135 Bell Hall
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“Everything that can be inventedhas been invented.”
(Charles Duell, Commissioner,U.S. Office of Patents, 1899)
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