Vlsi report using latex

AMITY UNIVERSITYRajasthan

VLSI LAB REPORT

SUBMITTED TOMr.Venkatrao Selamneni

SUBMITTED BYPriya Hada

B.tech(ECE)6th sem

April 28, 2014

Contents

1 INTRODUCTION TO VLSI 1

2 EXPERIMENT NO.1(a) 3

3 EXPERIMENT NO.1(b) 6

4 EXPERIMENT NO.2 10










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List of Figures

1 Schematic of NMOS . . . . . . . . . . . . . . . . . . . . . . . 4

2 Waveform of NMOS . . . . . . . . . . . . . . . . . . . . . . . 5

3 Schematic of PMOS . . . . . . . . . . . . . . . . . . . . . . . 8

4 Waveform of PMOS . . . . . . . . . . . . . . . . . . . . . . . 9

5 Inverter truth table . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 CMOS inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7 DC characteristics of CMOS inverter . . . . . . . . . . . . . . . 11

8 Schematic of CMOS inverter . . . . . . . . . . . . . . . . . . . 12

9 DC characteristic waveform of CMOS inverter . . . . . . . . . 13

10 Transient characteristics of CMOS inverter with pulse input. . . 14


12 Waveform of CMOS inverter . . . . . . . . . . . . . . . . . . . 16

13 propagation delay graph . . . . . . . . . . . . . . . . . . . . . 17


15 Waveform of CMOS inverter . . . . . . . . . . . . . . . . . . . 19

16 NOR Gate and its truth table . . . . . . . . . . . . . . . . . . . 20

17 Schematic of NOR Gate . . . . . . . . . . . . . . . . . . . . . 21

18 Symbol of NOR Gate . . . . . . . . . . . . . . . . . . . . . . . 21

19 Waveform of NOR Gate . . . . . . . . . . . . . . . . . . . . . 22

20 NAND gate using CMOS logic and its truth table . . . . . . . . 23

21 Schematic of NAND Gate . . . . . . . . . . . . . . . . . . . . 24

22 Waveform of NAND Gate . . . . . . . . . . . . . . . . . . . . 25

23 XOR Gate and its truth table . . . . . . . . . . . . . . . . . . . 26

24 Schematic of XOR Gate . . . . . . . . . . . . . . . . . . . . . 27

25 Waveform of XOR Gate . . . . . . . . . . . . . . . . . . . . . 28

26 XNOR Gate and its truth table . . . . . . . . . . . . . . . . . . 29

27 Schematic of XNOR Gate . . . . . . . . . . . . . . . . . . . . 30

28 Waveform of XNOR Gate . . . . . . . . . . . . . . . . . . . . 31

29 Two input AND gate with truth table . . . . . . . . . . . . . . . 32

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30 AND gate using CMOS . . . . . . . . . . . . . . . . . . . . . 33

31 Schematic of NAND gate . . . . . . . . . . . . . . . . . . . . . 33

32 Schematic of NOT gate . . . . . . . . . . . . . . . . . . . . . . 34

33 Schematic of AND gate . . . . . . . . . . . . . . . . . . . . . . 35

34 SR latch diagram with Function Table . . . . . . . . . . . . . . 36

35 Schematic of NAND Gate . . . . . . . . . . . . . . . . . . . . 37

36 Schematic of Symbol of NAND Gate . . . . . . . . . . . . . . . 37

37 Waveform of NAND Gate . . . . . . . . . . . . . . . . . . . . 38

38 Schematic of SR Latch . . . . . . . . . . . . . . . . . . . . . . 38

39 Waveform of SR latch . . . . . . . . . . . . . . . . . . . . . . . 39

40 Symbol and Truthtable of D flipflop . . . . . . . . . . . . . . . 40

41 Schematic D flipflop . . . . . . . . . . . . . . . . . . . . . . . 41

42 Waveform of D flipflop . . . . . . . . . . . . . . . . . . . . . . 42

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1 INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating integrated circuitsby combining thousands of transistors into a single chip. Since the inventionof the first Integrated Circuit(IC) by Jack Kilby in 1958, ability to pack moreand more transistors onto a single chip has been very rapid. In the early 1960s,low density fabrication processes classified under Small Scale Integration (SSI)in which transistor count was limited to about 10. This rapidly gave way toMedium Scale Integration (MSI) later in the decade, when around 100 transis-tors could be placed on a single chip. Early 1970s saw the growth of transistorcount to about 1000 per chip called the Large Scale Integration (LSI).

By mid-1980, the transistor count on a single chip exceeded 1000 and hencecame the age of Very Large Scale Integration or VLSI, which is large scaleintegration with a single chip of size as small as 50 millimeters square havingmore than a million transistor and circuits in it.

VLSI chiefly comprises of front end design and back end design. Whilefront end design includes digital design using HDL, design verification throughsimulation and other verification techniques, the design from gates and designfor testability, backend design comprises of complementary metal-oxide semi-conductor (CMOS) design and its characterization.The entire VLSI circuit de-sign procedure follows a step by step approach, where each design step is fol-lowed by simulation before it’s put into the hardware. Most VLSI designs areclassified into three Categories:

1. Analog: Small transistor count precision circuits such as Amplifiers, Dataconverters, filters, Phase Locked Loops, Sensors etc.

2. Application Specific Integrated Circuits (ASICS): Progress in the fabri-cation of internal circuits has enabled faster and more powerful circuits insmaller and smaller devices. ASICS are created for specific purposes andeach device is created to do a particular job, and do it well.

3. Systems on a Chip (SoC): These are highly complex mixed signal circuits,such as a network processor chip or a wireless radio chip.

Advantages offered by VLSI:

1. Integration improves the design

2. Compactness: less area, physically smaller.

3. Higher speed: lower parasitics(reduced interconnection length).

1

4. Lower power consumption.

5. Higher reliability: improved on-chip interconnects.

6. Integration significantly reduces manufacturing cost.

2

2 EXPERIMENT NO.1(a)

AIM

Study the drain and transfer characteristics of NMOS.

SOFTWARE REQUIRED

Design Architect Tool by Mentor Graphics, LINUX operating system.

THEORY

MOSFET is a four terminal device. The voltage applied to the gate terminal de-termines if and how much current flows between the source and the drain ports.The body represents the fourth terminal of the transistor. Its function is sec-ondary as it only serves to modulate the device characteristics and parameters.In N-type MOSFET (NMOS), the body is of p-type. The drain, the source andthe channel between the two are of n-type.

Working of NMOS

Initially, VGS = 0, i.e. when no gate to source voltage is applied, it is similarto two diodes connected back to back between the source and the drain. So,no current flows from source to drain. Also, a depletion layer is formed at thesource-substrate and the drain-substrate junctions. The holes under the gate arerepelled to produce a depletion region and it becomes continuous.

The VGS is then increased above the Threshold Voltage. At this time, minor-ity carriers in p-type substrate (electrons) cross the depletion region and reachesunder the gate. The process is called surface inversion.

Modes of operation

It has three modes of operation:

1. Cut-off mode: When no current flows through transistor i.e. ID = 0occurs when

VGS < VTH

Where VGS: gate to source voltage ; VTH : threshold voltage

3

2. Triode Region: It is a linear region in graph which obeys Ohms law. Itoccurs when

VGS > VTH

andVDS < VGS − VTH

The current equation in triode mode is given as:

ID =W

L.µn.Cox(VGS − VTH − VDS

2).VDS

3. Saturation Mode: When current becomes constant i.e. ID remains con-stant no matter how much we increase VGS . It occurs when

VGS > VTH

andVDS > VGS − VTH

The current equation in saturation mode is given as:

ID =W

2L.µn.Cox.(VGS − VTH)

2(1 + λp.VDS)

Where : modulation index

Schematic

Figure 1: Schematic of NMOS

4

Waveforms

Figure 2: Waveform of NMOS

Result

In V I characteristics of NMOS, we observe that at constant VGS if the value ofVDS will increase, then the drain current is saturated.

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3 EXPERIMENT NO.1(b)

AIM

To study the drain and transfer characteristics of PMOS.

SOFTWARE REQUIRED


THEORY

The structure and operation of a PMOS device is essentially the same, exceptthat wherever there was n-type silicon, there is now p-type silicon. The PMOSchannel is a part of n-type substrate lying between two heavily doped p+ wellsbeneath the source and drain.

Working of PMOS

The operation of PMOS is similar to NMOS. To create an inversion layer in then-type substrate, holes have to be attracted to the gate. As a result, p-type chan-nel will induce between drain and source, the voltage VTH must be sufficientlynegative. The VTH is thus negative, so, channel is induced only if VGS < VTH Ifwe make the voltage VDS sufficiently negative, the p-type induced channel willpinch-off. When VDS will be negative, the drain current will flow from sourceto drain, exactly opposite to that of NMOS device with a positive VDS .

Modes of Operation

It has three modes of operation -

1. Cut-off mode: It is a mode in which channel is not formed and no currentflows through transistor i.e. ID = 0. It occurs when

VGS > VTH

Where VGS: gate to source voltage, VTH : threshold voltage.

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2. Linear/Triode region: It is a mode in which channel formation takes placeand thus, current flows from source to drain. This region of graph followsOhms law due to linear relationship between IDS and VDS . It occurs when

VGS < VTH

andVDS > VGS − VTH

The current equation in triode mode is given as:

ID = −WL.µn.Cox(VGS − VTH − VDS

2).VDS

3. Saturation mode: In this mode the channel pinches off and the VDSat

which the current saturation occurs is called VDSat or pinch-off voltage.In this mode the PMOS acts similar to current source.ID is independentof VDS . It occurs when

VGS < VTH

andVDS < VGS − VTH

The current equation in saturation mode is given as:

ID = −W

2L.µn.Cox.(VGS − VTH)

2(1 + λp.VDS)

Where λp: modulation index

7

Schematic

Figure 3: Schematic of PMOS

8

Waveforms

Figure 4: Waveform of PMOS

Result

The characteristics of PMOS are obtained. All the parameters(voltages andcurrent) are taken in negative side.

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4 EXPERIMENT NO.2

AIM

To study D.C. analysis of CMOS inverter.

SOFTWARE REQUIRED


THEORY

Figure 5: Inverter truth table

Figure 6: CMOS inverter

The inverter is universally accepted as the most basic logic gate doing aBoolean operation on a single input variable.As shown, the simple structureconsists of a combination of an PMOS transistor at the top and a NMOS tran-sistor at the bottom. CMOS is referred to as complementary-symmetry metalox-idesemiconductor. The words ”complementary-symmetry” refer to the fact thatthe typical digital design style with CMOS uses complementary and symmetri-cal pairs of p-type and n-type metal oxide semiconductor field effect transistors

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(MOSFETs) for logic functions. Two important characteristics of CMOS de-vices are high noise immunity and low static power consumption. Significantpower is only drawn while the transistors in the CMOS device are switching be-tween on and off states. Consequently, CMOS devices do not produce as muchwaste heat as other forms of logic.

DC analysis of CMOS inverter

Figure 7: DC characteristics of CMOS inverter

As shown in above figure there are 5 regions of operation which are sum-marized as in the table:

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Schematic

Figure 8: Schematic of CMOS inverter

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Waveforms

Figure 9: DC characteristic waveform of CMOS inverter

RESULT

The DC characteristic of CMOS inverter is obtained successfully.

13

5 EXPERIMENT NO.3

AIM

To study transient analysis of CMOS inverter.

SOFTWARE REQUIRED


THEORY

Figure 10: Transient characteristics of CMOS inverter with pulse input.

Transient analysis tells Vout(t) if Vin(t) changes. It requires solving differ-ential equations. Input is usually considered to be a pulse stream.. It is alsocalled AC analysis or dynamic analysis or switching analysis.The switchingcharacteristic (Vout(t) given Vin(t)) of a logic gate tells the speed at which thegate can operate. The switching speed of a logic gate can be measured in termsof the time required to charge and discharge a capacitive load. Fig.1 shows thedynamic characteristics of a CMOS inverter. The following are some formaldefinitions of temporal parameters of digital circuits. All percentages are of thesteady state values.

1. Rise Time (tr) : Time taken to rise from 10% to 90%

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2. Fall Time (tf ): Time taken to fall from 90% to 10%

3. Edge Rate (trf ): (tr + tf )/2.

4. High-to-Low propagation delay (tpHL): Time taken to fall from VOH to50%.

5. Low-to-High propagation delay (tpLH): Time taken to rise from 50% toVOL.

6. Propagation Delay (tp): (tpHL + tpLH)/2.

7. Contamination Delay (tcd): Minimum time from the input crossing 50%to the output crossing 50%.

Schematic


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Waveforms

Figure 12: Waveform of CMOS inverter

RESULT

The transient characteristics of the CMOS inverter using pulse input is obtainedsuccessfully.

16

6 EXPERIMENT NO.4

AIM

Calculate Rise time, Fall time and Propagation delay of CMOS inverter.

SOFTWARE REQUIRED


THEORY

There are some basic terms that should be known for calculating the transientparameters of a CMOS inverter. Those are:

1. Switching speed : limited by time taken to charge and discharge, CL .

2. Rise time, tr: Waveform to rise from 10% to 90% of its steady state value

3. Fall time tf , : 90% to 10% of steady state value

4. Delay time, td : time difference between input transition (50%) and 50%output level

Figure 13: propagation delay graph

The propagation delay tp of a gate defines how quickly it responds to a change atits inputs, it expresses the delay experienced by a signal when passing through

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a gate. It is measured between the 50% transition points of the input and outputwaveforms as shown in the figure 1 for an inverting gate. The τpLH defines theresponse time of the gate for a low to high output transition, while τpHL refersto a high to low transition. The propagation delay as the average of the two i.e.

tp =1

2(τpLH + τpHL)

Schematic


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Waveforms

Figure 15: Waveform of CMOS inverter

RESULT

Rise time, Fall time and Propagation delay of CMOS inverter are calculated.

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AIM

To design two input NOR gate using CMOS logic.

SOFTWARE REQUIRED


THEORY

The NOR gate is a digital logic gate that implements logical NOR. A HIGHoutput (1) results if both the inputs to the gate are LOW (0); if one or both inputis HIGH (1), a LOW output (0) results. NOR is the result of the negation of theOR operator. It can also be seen as an AND gate with all the inputs inverted.

NOR is a functionally complete operationNOR gates can be combined togenerate any other logical function. NOR gates are so-called ”universal gates”that can be combined to form any other kind of logic gate.

Figure 16: NOR Gate and its truth table

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Schematic

Figure 17: Schematic of NOR Gate

Symbol

Figure 18: Symbol of NOR Gate

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Waveforms

Figure 19: Waveform of NOR Gate

RESULT

The wave forms of two input NOR gate are obtained successfully.

22


AIM

To design two input NAND gate using CMOS logic.

SOFTWARE REQUIRED


THEORY

The two-input NAND gate shown in the figure is built from four transistors. Theseries-connection of the two n-channel transistors between GND and the gate-output ensures that the gate-output is only driven low (logical 0) when bothgate inputs a or b are high (logical 1).The complementary parallel connectionof the two transistors between VCC and gate-output means that the gate-outputis driven high (logical 1) when one or both gate inputs are low (logical 0). Thenet result is the logical NAND function.

Figure 20: NAND gate using CMOS logic and its truth table

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Schematic

Figure 21: Schematic of NAND Gate

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Waveforms

Figure 22: Waveform of NAND Gate

RESULT

The wave forms of two input NAND gate are obtained successfully.

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AIM

To design two input XOR gate using CMOS logic.

SOFTWARE REQUIRED


THEORY

output is ”true” if either, but not both, of the inputs are ”true.” The output is”false” if both inputs are ”false” or if both inputs are ”true.” Another way oflooking at this circuit is to observe that the output is 1 if the inputs are different,but 0 if the inputs are the same. XOR can also be viewed as addition modulo2. As a result, XOR gates are used to implement binary addition The XOR( exclusive-OR ) gate acts in the same way as the logical ”either/or.” The incomputers. The algebraic expressions

A.B + A.B

and(A+B).A.B

both represent the XOR gate with inputs A and B.

Figure 23: XOR Gate and its truth table

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Schematic

Figure 24: Schematic of XOR Gate

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Waveforms

Figure 25: Waveform of XOR Gate

RESULT

The wave forms of two input NAND gate are obtained successfully.

28


AIM

To design two input XNOR gate using CMOS logic.

SOFTWARE REQUIRED


THEORY

The XNOR gate (sometimes spelled ”exnor” or ”enor” and rarely written NXOR)is a digital logic gate whose function is the inverse of the exclusive OR (XOR)gate. The XNOR (exclusive-NOR) gate is a combination XOR gate followedby an inverter.

The two-input version implements logical equality. A HIGH output (1) re-sults if both of the inputs to the gate are the same. If one but not both inputs areHIGH (1), a LOW output (0) results.

Figure 26: XNOR Gate and its truth table

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Schematic

Figure 27: Schematic of XNOR Gate

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Waveforms

Figure 28: Waveform of XNOR Gate

RESULT

The wave forms of two input XNOR gate are obtained successfully.

31

11 EXPERIMENT NO.7

AIM

To design two input AND gate using two input NAND gate and inverter sym-bols.

SOFTWARE REQUIRED


THEORY

Figure 29: Two input AND gate with truth table

A logic gate is an elementary building block of a digital circuit. A LogicAND Gate is a type of digital logic gate that has an output which is normallyat logic level 0 and only goes high to a logic level 1 when all of its inputs areat logic level 1. The output state of a Logic AND Gate only returns low againwhen any of its inputs are at a logic level 0. In other words for a logic ANDgate, any low input will give a low output. The logic or Boolean expressiongiven for a logic AND gate is that for Logical Multiplication which is denotedby a single dot or full stop symbol,( . ) giving us the Boolean expression of:

A.B = Output

Then we can define the operation of a 2-input logic AND gate as being:

If both A and B are true, then Output is true.

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Design

For designing two input AND gate with CMOS logic first we have to designtwo input NAND gate and its output will be fed to a CMOS inverter to give theoutput of AND gate as shown in the figure: Here the output of NAND gate say

Figure 30: AND gate using CMOS

Vz = Vx.Vy Then on passing it through the inverter gives out outputVf = Vx.Vywhich is the expression required for AND gate.

Schematic of NAND

Figure 31: Schematic of NAND gate

33

Schematic of NOT

Figure 32: Schematic of NOT gate

34

Schematic of AND

Figure 33: Schematic of AND gate

RESULT

Two input AND gate using two input NAND gate and Inverter symbols designedsuccessfully.

35

12 EXPERIMENT NO.8

AIM

To design S-R latch using symbol of NAND gate.

SOFTWARE REQUIRED


THEORY

A latch is a device with exactly two stable states. These states are high-outputand low-output. A latch has a feedback path, so information can be retained bythe device. Therefore latches can be memory devices, and can store one bit ofdata for as long as the device is powered. Latches are very similar to flip-flops,but are not synchronous devices, and do not operate on clock edges as flip-flopsdo.

An SR latch (Set/Reset) is an asynchronous device: it works independentlyof control signals and relies only on the state of the S and R inputs. SR latchescan be made from NAND gates. In this case, it is sometimes called an SR latch.

Figure 34: SR latch diagram with Function Table

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Schematic of NAND Gate

Figure 35: Schematic of NAND Gate

Schematic(SYMBOL)

Figure 36: Schematic of Symbol of NAND Gate

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Waveforms of NAND Gate

Figure 37: Waveform of NAND Gate

Schematic of SR Latch

Figure 38: Schematic of SR Latch

38

Waveforms of SR Latch

Figure 39: Waveform of SR latch

RESULT

S-R latch using symbol of NAND gate designed successfully.

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13 EXPERIMENT NO.9

AIM

To design D flip flop using CMOS logic.

SOFTWARE REQUIRED


THEORY

The D flip-flop tracks the input, making transitions with match those of the inputD. The D stands for ”data”; this flip-flop stores the value that is on the data line.It can be thought of as a basic memory cell. A D flip-flop can be made from aset/reset flip-flop by tying the set to the reset through an inverter. D flip-flopsare by far the most common type of flip-flops and some devices (for examplesome FPGAs) are made entirely from D flip-flops. They are also commonlyused for shift-registers and input synchronization.

Figure 40: Symbol and Truthtable of D flipflop

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Schematic

Figure 41: Schematic D flipflop

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Waveforms

Figure 42: Waveform of D flipflop

RESULT

D flip flop using CMOS logic obtained successfully.

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