VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+...
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Transcript of VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+...
![Page 1: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/1.jpg)
VLSI Layout AlgorithmsCSE 6404
A 46
B 65
C 11D 56
E
23
F 8
H 37
G 19
I 12 J 14
K 27
X=(AB*CD)+ (A+D)+(A(B+C))Y = (A(B+C)+AC+ D+A(BC+D))
Dr. Md. Saidur Rahman
![Page 2: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/2.jpg)
AB
F
E
C
D
ELECTRONIC CIRCUIT
Is it possible to lay the circuit on a single layered PCB?
![Page 3: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/3.jpg)
AB
C
DE
F
Is it possible to lay the circuit on a single layered PCB?
POSSIBLE !
![Page 4: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/4.jpg)
AB
F
E
C
D
ELECTRONIC CIRCUIT
Is it possible to lay the circuit on a single layered PCB?
NOT POSSIBLE
![Page 5: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/5.jpg)
A planar graph
planar graph non-planar graph
![Page 6: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/6.jpg)
Kuratowski’s Theorem
A graph is planar if and only if it contains neither a subdivision of K5 nor a subdiision of K3,3.
![Page 7: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/7.jpg)
Kuratowski’s Theorem
A graph is planar if and only if it contains neither a subdivision of K5 nor a subdiision of K3,3.
Planarity testing algorithm based on Kuratowski’s theorem.
Time complexity : exponential.
![Page 8: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/8.jpg)
A polynomial time algorithm
Idea: decompose a graph with respect to a cycle.
C
[AP 61, Gol63, Shi69]
![Page 9: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/9.jpg)
Pieces
C
![Page 10: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/10.jpg)
attachmentPieces
C
![Page 11: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/11.jpg)
Connected components after deleting C
![Page 12: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/12.jpg)
attachment
![Page 13: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/13.jpg)
P1
P2P3
P4 P5 P6
Six pieces
![Page 14: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/14.jpg)
Separating cycle and nonseparating cycle
Separating cycle Nonseparating cycle
![Page 15: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/15.jpg)
Lemma
Let G be a biconnected graph and let C be a nonseparating cycle of G with piece P. If P is not a path, the G has a separating cycle C’ consisting of a subpath of C plus a path of P between two attachmet.
![Page 16: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/16.jpg)
Interlace
Two pieces of G, with respect to C, interlace if they cannot be drawn on the same side of C without violating planarity.
P2P1
P1 and P2 interlace.
![Page 17: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/17.jpg)
Interlacement Graph
The interlacement graph of the pieces of G, with respect to C, is the graph whose vertices are the pieces of G and whose edges are the pairs of pieces that interlace.
P2 P1
P3
P4
P6
P5P1
P2P3
P4
P5
P6
interlacement graph
![Page 18: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/18.jpg)
Theorem
A biconnected graph G with a cycle C is planar if and only if the following two conditions hold.
For each piece P of G with respect to C, the graph obtained by adding P to C is planar.
The interlacement graph of the pieces of G, with respect to C, is bipartite.
The theorem above leads to a recursive algorithm.
![Page 19: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/19.jpg)
Time complexity
Computing pieces O(n)
Construction of Interlacement graph O(n2)
Cheking bipartite graph O(n2)
Depth of recursion O(n)
Overall O(n3)
![Page 20: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/20.jpg)
Linear Algorithms
Hopcroft and tarjan, 1974
Booth and Lueker, 1976Planarity testing
Finding planar embeddingChiba et al, 1985
Shih and Hsu, 1992-1999
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The circuit is not planar.
How many PCB’s are required?
![Page 22: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/22.jpg)
Thickness of a graph t(G)
The thickness t(G) of a graph G is defined to be the smallest number of planar graphs that can be superimposed to form G.
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Euler Theorem
Let G be a connected plane graph, and let n, m, f denote respectively the number of vertices, edges and faces of G. Then
2 fmn
For a planar graph 63 nm
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For a planar graph 63 nm
63)(
n
mGtThickness
![Page 25: VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur.](https://reader035.fdocuments.us/reader035/viewer/2022062313/56649f425503460f94c613b3/html5/thumbnails/25.jpg)