Vlsi ii project presentation
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Transcript of Vlsi ii project presentation
VLSI II PROJECT : DESIGN OF A GENERAL PURPOSE 4 BIT SHIFT
REGISTERPresented by:
Naimul Hassan (1006074)Md. Redwan Islam (1006066)
OBJECTIVE To design a CMOS general purpose n-bit
shift register using Cadence.
Designed shift register would have the capability to load parallel n-bit data and
shift the data serially in both left and right direction.
PROPOSED VIEW OF OUR PROJECT
4 bit shift register
Parallel data
Parallel output
Parallel load control
Parallel output control
Left shift inputLeft shift input control
Left shift outputRight shift input
Right shift input control Right shift outputrefresh
clock
PRINCIPLE FOCUS OF THE DESIGNWe first built a basic shifter cell which had all the capabilities to be cascaded
in left and right direction to create an n-bit shift register
Each basic cell not only has the parallel single bit loading capability but also the ability to shift value to right and left
The shifting, loading and the output operations are controlled by various control inputs which are again fed to the circuit with proper synchronization
with system clock for the smooth operation of the circuit
In addition to loading and transferring data, our shift register also has refreshing capability.
When refreshing command is asserted, all other control inputs are disabled and the circuit refreshed again and again in synchronization with the clock in
order to retain its previously loaded value into its internal capacitances
TOP DOWN DESIGN APPROACH
Synthesized circuit
Encounter RTL Compiler Ultra
NCLaunch & Simvision
Test bench
Verilog HDL
SOURCE CODE OF THE GENERAL PURPOSE SHIFT REGISTER MODULE
module shifterfinal(dp, qp, r,l,dprl, right , left,clk, fb, qprl);
input dprl, right, left,clk, fb, r, l, qprl;
input [3:0]dp;
output reg [3:0]qp;
reg [3:0]w;
reg rs;
always @(dp or qp or r or l or dprl or right or left or clk or fb or qprl)
begin
if (fb | ~dprl & ~right &~left)
rs= 1'b1;
else if (~(fb | ~dprl & ~right &~left))
rs= 1'b0;
if(dprl & ~right & ~left & clk & ~fb )
w = dp;
else if(left & ~right & ~dprl & clk & ~fb)
begin
w[3]=w[2];
w[2]=w[1];
w[1]=w[0];
w[0]=l;
end
else if(right & ~left & ~dprl & clk & ~fb)
begin
w[0]=w[1];
w[1]=w[2];
w[2]=w[3];
w[3]=r;
end
else if(rs & clk)
w=w;
if(qprl & ~clk)
qp=w;
end
endmodule
SOURCE CODE OF THE GENERAL PURPOSE SHIFT REGISTER TESTBENCH MODULE
module stimulus_shifterfinal;
reg dprl, right, left,clk, fb, r, l,qprl;
reg [3:0]dp;
wire [3:0]qp;
shifterfinal shifterfinal1(dp, qp, r,l,dprl, right , left, clk, fb,qprl);
initial
begin
clk= 1'b1;
forever begin #10 clk =~clk;
$display("At Time: %d hifter Output=%d",$time,qp);
end
end
initial
begin
dp = 4'b1010;
forever begin #20 dp = ~dp;
$display("At Time: %d Shifter Output=%d",$time,qp); end
end
initial
begin
$shm_open("shm.db",1); // Opens a waveform database
$shm_probe("AS"); // Saves all signals to database
#260 $finish;
#300 $shm_close(); // Closes the waveform database
end
// Stimulate the Input Signals
initial
begin
#0 dprl=1'b1;left=1'b0;r=1'b0;l=1'b0;fb=1'b0;right=1'b0;qprl=1'b1;
#35 dprl =1'b0;right=1'b1;
#20 right=1'b0;
#85 left=1'b1;
end
endmodule // stimulus
OUTPUT FROM SIMVISION
SYNTHESIZED CIRCUITRY FROM RTL COMPILER
SYNTHESIZED SOURCE CODE // Generated by Cadence Encounter(R) RTL Compiler v12.10-s012_1
// Verification Directory fv/shifterfinal
module shifterfinal(dp, qp, r, l, dprl, right, left, clk, fb, qprl);
input [3:0] dp;
input r, l, dprl, right, left, clk, fb, qprl;
output [3:0] qp;
wire [3:0] dp;
wire r, l, dprl, right, left, clk, fb, qprl;
wire [3:0] qp;
wire [3:0] w;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
wire n_16, n_17, n_18, n_19, n_20, n_21, n_22, n_23;
wire n_24, n_25, n_26, n_27;
LATCH \w_reg[2] (.CLK (n_25), .D (n_27), .Q (w[2]));
OAI21X1 g422(.A (n_1), .B (n_23), .C (n_26), .Y (n_27));
AOI22X1 g423(.A (n_19), .B (w[3]), .C (n_17), .D (dp[2]), .Y (n_26));
LATCH \qp_reg[3] (.CLK (n_10), .D (w[3]), .Q (qp[3]));
LATCH \w_reg[0] (.CLK (n_25), .D (n_21), .Q (w[0]));
LATCH \w_reg[1] (.CLK (n_25), .D (n_24), .Q (w[1]));
LATCH \w_reg[3] (.CLK (n_25), .D (n_22), .Q (w[3]));
OAI21X1 g429(.A (n_2), .B (n_23), .C (n_18), .Y (n_24));
NAND2X1 g430(.A (n_20), .B (n_15), .Y (n_22));
OAI21X1 g428(.A (n_0), .B (n_23), .C (n_16), .Y (n_21));
AOI22X1 g434(.A (n_19), .B (r), .C (n_14), .D (w[2]), .Y (n_20));
AOI22X1 g432(.A (n_19), .B (w[2]), .C (n_17), .D (dp[1]), .Y (n_18));
AOI22X1 g433(.A (n_19), .B (w[1]), .C (n_17), .D (dp[0]), .Y (n_16));
NAND2X1 g435(.A (n_17), .B (dp[3]), .Y (n_15));
INVX1 g438(.A (n_23), .Y (n_14));
NOR2X1 g440(.A (n_13), .B (left), .Y (n_17));
OAI21X1 g431(.A (n_5), .B (n_9), .C (n_19), .Y (n_25));
NAND2X1 g439(.A (n_11), .B (left), .Y (n_23));
NAND2X1 g437(.A (n_12), .B (n_7), .Y (n_19));
NAND2X1 g441(.A (n_12), .B (dprl), .Y (n_13));
NOR2X1 g442(.A (n_8), .B (dprl), .Y (n_11));
LATCH \qp_reg[2] (.CLK (n_10), .D (w[2]), .Q (qp[2]));
NAND3X1 g436(.A (n_3), .B (right), .C (n_6), .Y (n_9));
LATCH \qp_reg[1] (.CLK (n_10), .D (w[1]), .Q (qp[1]));
INVX1 g443(.A (n_8), .Y (n_12));
LATCH \qp_reg[0] (.CLK (n_10), .D (w[0]), .Q (qp[0]));
NAND2X1 g444(.A (n_4), .B (clk), .Y (n_8));
AOI21X1 g445(.A (dprl), .B (left), .C (n_6), .Y (n_7));
AND2X1 g449(.A (n_5), .B (qprl), .Y (n_10));
NOR2X1 g450(.A (dprl), .B (left), .Y (n_6));
NOR2X1 g451(.A (right), .B (fb), .Y (n_4));
INVX1 g455(.A (fb), .Y (n_3));
INVX1 g452(.A (w[0]), .Y (n_2));
INVX1 g456(.A (clk), .Y (n_5));
INVX1 g453(.A (w[1]), .Y (n_1));
INVX1 g454(.A (l), .Y (n_0));
endmodule
LIMITATION
We lacked some of the resources in
order to reach the
completion of the top down
design process
We did not have and also could not find any resource or tutorial on
building standard cell libraries and
other configuration
files for layout.
Therefore, we had to halt our
top down design process
only after synthesizing
the gate level source code,
Nevertheless, the top down
design process would be a
very promising design
approach.
BOTTOM UP DESIGN APPROACH
For the bottom up design approach, a unit shifter sub-cell was designed so that this could be cascaded to create the 4 bit general purpose shift register.
In addition to that a general logic block and special logic block were designed in order to produce the clock synchronized and modified logic inputs to the shifter cell control inputs.
BOTTOM UP WORKFLOWFirst we created the basic and necessary cells required for our project and simulated the behavior of the schematic using ADE L
Then we built up the floorplan of our layout and accordingly, built up the layout of the sub-cells
We used the layout sub cells to create the final core circuit layout.
Next we added ESD protection circuitry both in schematic and layout
Then we extracted the final ESD protected, larger I/O padded circuit, simulated again, to see the post layout behavior and finally made a tape out
GENERAL LOGIC BLOCK SCHEMATIC
GENERAL LOGIC BLOCK LAYOUT
SPECIAL LOGIC BLOCK SCHEMATIC
SPECIAL LOGIC BLOCK LAYOUT
SINGLE BIT SHIFTER CELL SCHEMATIC
SINGLE BIT SHIFTER CELL LAYOUT
4 BIT GENERAL PURPOSE SHIFT REGISTER SCHEMATIC
4 BIT GENERAL PURPOSE SHIFT REGISTER LAYOUT
ESD PROTECTION CELL SCHEMATIC
ESD PROTECTION CELL LAYOUT
FINAL LAYOUT
AV_EXTRACTED VIEW
AV_EXTRACTED OUTPUT
PERFORMANCE OF THE CIRCUIT
Delay • 0.7214 ns Avera
ge Power:
• 17.23µW.
Transmission gate
Schematics
Transmission gate Layout
2 input NAND gate
schematics
3 input NAND gate
schematics
SOME OTHER CELLS USED
SPECIAL CONSIDERATIONS OF THE FLOOR PLAN
While doing the floor plan of the circuit, care was taken so that, the VDD and the Gnd rails as well as the Nwell are butted together. The floorplan was done in such a way that all the I/O pins stay at the outermost part of the design area.
Repeatedly, design was optimized in order to get the minimum area.
THANK YOU