BCD TO EXCESS-3 CODE CONVERTER 1

Chapter-1

INTRODUCTION

AIM OF THE PROJECT:

The aim of this project is to design a BCD TO EXCESS-3 code converter.

To draw the circuit layout using MICROWIND Software

To simulate the circuit in DSCH2 Software

SOFTWARES USED:

DSCH2 for simulation

MICROWIND for drawing layouts

1.1 GENERAL INTRODUCTION:

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining

thousands of transistors into a single chip. VLSI began in the 1970s when

complex semiconductor and communication technologies were being developed. Very-Large Scale

Integration usage number is between 1,000 and 10,000 transistors or thousands of gates and

perform computational operations such as processors, large memory arrays and programmable

logic devices.

The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a

limited set of functions they could perform. VLSI lets IC designers add all of these into one chip.

Structured VLSI design is a modular methodology originated by Carver Mead and Lynn

Conway for saving microchip area by minimizing the interconnect fabrics area. An example is

partitioning the layout of an adder into a row of equal bit slices cells. In complex designs this

structuring may be achieved by hierarchical nesting.

Structured VLSI design had been popular in the early 1980s, but lost its popularity later because of

the advent of placement and routing tools wasting a lot of area by routing, which is tolerated

because of the progress of Moore's Law. Moore's law is the observation that the number

of transistors in a dense integrated circuit doubles approximately every two years. 

Complementary metal-oxide–semiconductor (CMOS) is a technology for constructing

integratedcircuits.CMOStechnologyisused in microprocessors, microcontrollers, static RAM, and

other digital logic circuits. CMOS technology is also used for several analog circuits such as image

sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of

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communication. MOSFET’s are the basic building blocks. There are three main components to a

CMOS transistor. The Source and Drain can be interchanged at the silicon level and occasionally

at the device level. These are the main current carrying terminals. The Gate is separated from the

Composite (Silicon) by a thin layer of SiO2, which acts as an insulator or dielectric. In the CMOS

world you can create a Capacitor by shorting the Source and Drain together calling that one

terminal, and using the Gate for the other terminal.The CMOS technology provides two types of

transistors n-type transistors(nMOS),p-type transistors(pMOS). The difference between an NMOS

and a PMOS device depends on the type of WELL (base) the transistor is sitting in.

Two important characteristics of CMOS devices are high noise immunity and low static power

consumption.[3] Since one transistor of the pair is always off, the series combination draws

significant power only momentarily during switching between on and off states. Consequently,

CMOS devices do not produce as much waste heat as other forms of logic, for example transistor–

transistor logic (TTL) or NMOS logic, which normally have some standing current even when not

changing state. CMOS also allows a high density of logic functions on a chip. It was primarily for

this reason that CMOS became the most used technology to be implemented in VLSI chips.

1.2 INTRODUCTION TO SOFTWARES:

Dsch2 Software:

The DSCH program is a logic editor and simulator. DSCH is used to validate the architecture of the

logic circuit before the microelectronics design is started. DSCH provides a user-friendly

environment for hierarchical logic design, and fast simulation with delay analysis, which allows the

design and validation of complex logic structures. DSCH also features the symbols, models and

assembly support for 8051 and 16F84 controllers. Designers can create logic circuits for interfacing

with these controllers and verify software programs using DSCH.

Highlights

    User-friendly environment for rapid design of logic circuits.  

    Supports hierarchical logic design.  

    Added a tool on fault analysis at the gate level of digital. Faults: Stuck-1, stuck-at-0. The

technique allows injection of single stuck-at fault at the nodes of the circuit.

 

    Improved interface between DSCH and Winspice.  

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    Handles both conventional pattern-based logic simulation and intuitive on screen mouse-

driven simulation.

 

    Built-in extractor which generates a SPICE netlist from the schematic diagram

(Compatible with PSPICETM and WinSpiceTM).s

 

    Generates a VERILOG description of the schematic for layout conversion.  

    Immediate access to symbol properties (Delay, fanout).  

    Model and assembly support for 8051 and PIC 16F84 microcontrollers.  

    Sub-micron, deep-submicron, nanoscale technology support.  

    Supported by huge symbol library.

MICROWIND Software:

The MICROWIND software allows the designer to simulate and design an integrated circuit at

physical description level. Microwind3 unifies schematic entry, pattern based simulator, SPICE

extraction of schematic, Verilog extractor, layout compilation, on layout mix-signal circuit

simulation, cross sectional & 3D viewer, netlist extraction, BSIM4 tutorial on MOS devices and

sign-off correlation to deliver unmatched design performance and designer

productivity. MICROWIND is truly integrated EDA software encompassing IC designs from

concept to completion, enabling chip designers to design beyond their imagination. MICROWIND

integrates traditionally separated front-end and back-end chip design into an integrated flow,

accelerating the design cycle and reduced design complexities. It tightly integrates mixed-signal

implementation with digital implementation, circuit simulation, transistor-level extraction and

verification – providing an innovative education initiative to help individuals to develop the skills

needed for design positions in virtually every domain of IC industry.

The package contains a library of common logic and analog ICs to view and simulate.

Microwind3 includes all the commands for a mask editor as well as, you can gain access to Circuit

Simulation by pressing just one single key. The electric extraction of your circuit is automatically

performed and the analog simulator produces voltage and current curves immediately. The tool

features full editing facilities, various views, and an on-line analog simulator. The MICROWIND

software has following segments in it:  DSCH, nano Lambda, VirtualFab, PROthumb, PROtutor,

MEMsim. A specific command displays the characteristics of pMOS and nMOS, where the size of

the device and the process parameters can be very easily changed. Altering the MOS model

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parameters and, then, seeing the effects on the Vds and Ids curves constitutes a good interactive

tutorial on devices.

The Process Simulator shows the layout in a vertical perspective, as when fabrication has

been completed. This feature is a significant aid to supplement the descriptions of fabrication found

in most textbooks. The Logic Cell Compiler is a particularly sophisticated tool enabling the

automatic design of a CMOS circuit corresponding to your logic description in VERILOG.

Fig:1.1 Logic levels in dsch and microwind softwares

CHAPTER-2

PROJECT DESCRIPTION

2.1 PROJECT INTRODUCTION:

Code Converters

A code converter is a circuit that makes the two systems compatible even though each uses

a different binary code. Conversion of signals or groups of signals in one code into corresponding

signals or groups of signals in another code. The process of converting a code of some

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predetermined bit structure, such as 5, 7, or 14 bits per character interval, to another code with the

same or a different number of bits per character interval. Code converters, more specifically

encoders and decoders, have been used by children and adults alike to protect private information.

Indeed, code converters have proven to be so effective. In code conversion, alphabetical order is not

significant.

BCD to Excess-3 Converter

The term BCD refers to representing the ten decimal digits in binary forms which simply

means to count in binary. The Excess-3 BCD system is formed by adding 0011 to each BCD value

as in Table 2. For example, the decimal number 7, which is coded as 0111 in BCD, is coded as

0111+0011=1010 in Excess-3 BCD.

Decimal Numerals Binary Numerals Excess-3

0 0000 0011

1 0001 0100

2 0010 0101

3 0011 0110

4 0100 0111

5 0101 1000

6 0110 1001

7 0111 1010

8 1000 1011

9 1001 1100

Table 1: BCD Excess-3

K-map Simplification

Our BCD Excess-3 circuit will convert numbers from their binary representation to their

excess-3 representation.

A B C D W X Y Z

0 0 0 0 0 0 1 1

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0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

Table 2: Truth Table BCD to Excess-3

Our task now is to use the truth table to find four switching expressions: one for W, one for X, one

for Y, and one for Z. We have two choices: we can use Boolean algebraic manipulations, or we can

use Karnaugh Maps. In the four K-maps that follow, the x’s are referred to as “ don’t cares ”. These

don’t cares are available because if you look at the truth table in Table 3, no WXYZ valuations

exist for ABCD = 1010, ABCD = 1011, ABCD = 1100, ABCD = 1101, ABCD = 1110, and ABCD

= 1111. As such, we evaluate WXYZ = xxxx for each of these entries. And we are free to use these

x’s as we please (as 0s or as 1s where convenient) since we can’t really hurt anything.

For W:

Table 3: Karnaugh Map for W

W = A + BD + BC = A + B (D + C)

For X:

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Table 4: Karnaugh Map for X

X = BC’D’ + B’D + B’C = BC’D’ + B’ (D + C)

For Y:

Table 5: Karnaugh Map for Y

Y = C’D’ + CD

For Z:

Table 6: Karnaugh Map for Z

Z = D’

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Now we have all the four switching functions we need to build the Excess-3 circuit:

W = A + BD + BC = A + B (D + C)

X = BC’D’ + B’D + B’C

= BC’D’ + B’(D+C)

Y = C’D’ + CD

Z = D’

2.2 CONVERSION OF LOGIC LEVEL TO TRANSISTOR LEVEL

So far we have dealt largely with implementing logic circuits in terms of gates. In this

project we will explore implementing the gates themselves using CMOS technology. Primitive

logic gates can be implemented directly in terms of electronic elements called transistors. CMOS

implementation is important because we often design CMOS logic from Boolean equations directly

to the transistor level, skipping the logic gate level.

Switch Models for CMOS Transistors CMOS technology employs two types of transistor: n-

channel and p-channel. The two differ in the characteristics of the semiconductor materials used in

their implementation and in the mechanism governing the conduction of a current through them.

Most important to us, however, is the difference in behavior of the two types of transistor. We will

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model this behavior using switches controlled by voltages corresponding to logic 0 and logic 1.

Such a model ignores complex electronic devices and captures only logical behavior. The symbol

for an n-channel transistor is shown in Figure 1(a). The transistor has three terminals: the gate (G),

the source (S), and the drain (D), as shown in Figure 1(b). The voltage applied between G and S

determines whether a path for current to flow exists between D and S. If a path exists, we say that

the transistor is ON, and if a path does not exist, we say that the transistor is OFF. The n-channel

transistor is ON if the applied gate-to-source voltage is H and OFF if the applied voltage is L. Here

we will make the usual assumption that a 1 represents the H voltage range and a 0 represents the L

voltage range.

The CMOS technology consists of two types of networks. A pull up network and a pull

down network. The pullup network should be constructed from p-transistors only, and the pulldown

network should be constructed from n-transistors only.CMOS is purely composed of p-type and n-

type MOSFETs, with no need for resistors that would generate waste heat. There are only two rules

that must be followed to be electrically considered a CMOS circuit:

1. All PMOS transistors must either have an input from the voltage source or another

PMOStransistors.

2. All NMOS transistors must either have an input from ground or another NMOS transistor.

Using these two rules it is possible to build all the other gates. For example, the NOT gate simply

requires one NMOS and one PMOS. The PMOS is connected to the voltage source and the NMOS

to the ground. The gate for both is controlled by a single input, and the output current is also

connected together.

We can treat MOS transistors as simple on-off switches with a source (S), gate (G) (controls the

state of the switch) and drain (D). 1 represents high voltage, VDD (5V, 3.3V, 1.8V, 1.2V, <=1.0V

today, .....) 0 represent low voltage - GND or VSS. (0V for digital circuits)

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Signals such as 1 and 0 have strengths, measures ability to sink or source current VDD and GND

Rails are the strongest 1 and 0 Under the switch abstraction, G has complete control and S and D

have no effect. In reality, the gate can turn the switch on only if a potential difference of at least Vt

exists between the G and S. We will look at Vt in detail later on in the course. Thus signal strengths

are related to Vt and therefore p and n transistors produce signals with different strengths

Inverter:

The inverter is universally accepted as the most basic logic gate doing a Boolean operation on a

single input variable. Figure depicts the symbol, truth table and a general structure of a CMOS

inverter. As shown, the simple structure consists of a combination of an pMOS transistor at the top

and a nMOS transistor at the bottom.

The truth table shows a logic '1' output corresponding to a logic '0' in the input. This can be ensured

by the p-transistor whose source is connected to a logic '1' source ( VDD ) and gate is provided a

logic '0' stimulus. Similarly, a logic '0' output will result from a logic '1' input. The nMOS transistor

connected in the bottom realizes this when its gate is given a logic '1' input and its source is

connected to logic '0' or ground (VSS).

The inverter can best be considered as the central part of digital designs. A thorough understanding

of its operation and properties is required to design more complex structures like NAND and NOR

gates, adders and multipliers.

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Fig:2.4.1 Invertor in CMOS technology

XOR Gate implementation in CMOS technology:

The transistor level circuit is useful for simulation in DSCH2.Using MICROWIND the circuit

layout should be drawn this can be obtained from the stick diagram.The stick diagram can be drawn

froms the schematic diagram.

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2.3 STICK DIAGRAM AND LAYOUT REPRESENTATION

Stick diagrams and layout representation are used to convey layer information through the use of a

color code. The Stick diagrams and layout representation for CMOS are a logical extension of the

nMOS style. The exception is yellow is used to identify p-type transistors and wires as depletion

mode devices are not used.

STICK DIAGRAM:

A popular method of symbolic design is "Sticks" layout. In this, the designer draws a freehand

sketch of a layout, using colored lines to represent the various process layers such as diffusion,

metal and polysilicon .Where polysilicon crosses diffusion, transistors are created and where metal

wires join diffusion or polysilicon, contacts are formed. This notation indicates only the relative

positioning of the various design components. The absolute coordinates of these elements are

determined automatically by the editor using a compactor. The compactor translates the design

rules into a set of constraints on the component positions, and solve a constrained optimization

problem that attempts to minimize the area or cost function. The advantage of this symbolic

approach is that the designer does not have to worry about design rules, because the compactor

ensures that the final layout is physically correct. The disadvantage of the symbolic approach is that

the outcome of the compaction phase is often unpredictable. The resulting layout can be less dense

than what is obtained with the manual approach. In addition, it does not show exact placement,

transistor sizes, wire lengths, wire widths, tub boundaries.Some colour codings are required in

order to draw a stick diagram.

CMOS Joining rules:

wherever red cross green an n-transistors is formed and p-transistor is formed wherever red

cross yellow

When wires of the same type are crossed connection is made even if you don't use contact

or via.

Diffusions of the opposite types cannot cross and contact

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poly (red) cannot contact n-diff (green) and p-diff (yellow).

when you want to connect poly (red) to n-diff (green) or p-diff (yellow), you must first

connect poly (red) to metal1 (blue) and then metal1 (blue) to n-diff (green) or pdiff (yellow)

. Metal1 (blue) can contact ndiff (green), pdiff (yellow) and poly (red), but remember

contact is needed, otherwise no connection is made, even if the layers are crossed

Metal1 (blue) can contact metal2 (purple), but remember, via is needed, otherwise no

connection is made even if the layers are crossed.

Fig:2.3.1 Colour coding of stick diagram

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LAYOUT DESIGN RULES:

The physical mask layout of any circuit to be manufactured using a particular process must

conform to a set of geometric constraints or rules, which are generally called layout design rules.

These rules usually specify the minimum allowable line widths for physical objects on-chip such as

metal and polysilicon interconnects or diffusion areas, minimum feature dimensions, and minimum

allowable separations between two such features. If a metal line width is made too small, for

example, it is possible for the line to break during the fabrication process or afterwards, resulting in

an open circuit. If two lines are placed too close to each other in the layout, they may form an

unwanted short circuit by merging during or after the fabrication process. The main objective of

design rules is to achieve a high overall yield and reliability while using the smallest possible

silicon area, for any circuit to be manufactured with a particular process. Note that there is usually a

trade-off between higher yield which is obtained through conservative geometries, and better area

efficiency, which is obtained through aggressive, high- density placement of various features on the

chip. The layout design rules which are specified for a particular fabrication process normally

represent a reasonable optimum point in terms of yield and density. It must be emphasized,

however, that the design rules do not represent strict boundaries which separate "correct" designs

from "incorrect" ones. A layout which violates some of the specified design rules may still result in

an operational circuit with reasonable yield, whereas another layout observing all specified design

rules may result in a circuit which is not functional and/or has very low yield. To summarize, we

can say, in general, that observing the layout design rules significantly increases the probability of

fabricating a successful product with high yield.

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The design rules are usually described in two ways :

1) Micron rules, in which the layout constraints such as minimum feature sizes and minimum

allowable feature separations, are stated in terms of absolute dimensions in micrometers.

2) Lambda rules, which specify the layout constraints in terms of a single parameter (λ) and, thus,

allow linear, proportional scaling of all geometrical constraints. Lambda-based layout design

rules were originally devised to simplify the industry- standard micron-based design rules and to

allow scaling capability for various processes. It must be emphasized, however, that most of the

submicron CMOS process design rules do not lend themselves to straightforward linear scaling.

The use of lambdabased design rules must therefore be handled with caution in sub-micron

geometries. In the following, we present a sample set of the lambda-based layout design rules

devised for the MOSIS CMOS process and illustrate the implications of these rules on a section a

simple layout which includes two transistors

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CHAPTER-3

IMPLEMENTATION OF PROJECT USING DSCH2 SOFTWARE

3.1 CIRCUIT DESIGN IN DSCH2

Fig:3.1.1Circuit when no input is on

3.2 TIMING DIAGRAMS OF CIRCUIT:

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Fig:3.2.1 Timing wave form

CHAPTER-4

IMPLEMENTAION OF PROJECT USING MICROWIND

4.1 LAYOUT OF THE CIRCUIT:

Fig:4.1.1 Layout of bcd to excess-3 code converter

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4.2 OUTPUT WAVEFORMS:

Fig 4.2.1 Wave form for bcd to excess-3 code converter

CHAPTER-5

APPLICATIONS

1) The excess 3 code is a technique to represent numbers with a balance of positive and negative

numbers. When the sum of two of these excess 3 numbers exceed 9, the carry bit of adder will set

to high.

2) These codes are precisely used in electro optical switches and electrochemical signals.

3) It is mainly used for arithmetic operations. It can add two decimal numbers

even if their sum exceeds nine. It simplifies operations of arithmetic. 

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CHAPTER-6

CONCLUSION

This project represents the design, layout and simulation of BCD to Excess-3 code converter based

on XOR,OR,AND circuits configuration. An optimal design for XOR ,OR,AND,INVERTER base

code converter circuits has been proposed. The proposed implementation is simulated using

DSCH2 a simulator and MICROWIND a layout designer. This design is efficient in terms of area.

More over considering the less area and power consumption.

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\

CHAPTER-7

REFERENCES

1) Basic VLSI design by Pucknell

2)http://buzzingmyhead.blogspot.in/2012/08/application-of-gray-excess-3-and-ascii.html

3) http://www.nptel.ac.in/courses/117101058/downloads/Lec-13.pdf

4) https://en.wikipedia.org/wiki/Excess-3

5) http://mmumullana.org/downloads/files/n54744b3ccc08d.pdf

6) http://www.ece.ncsu.edu/muse/courses/ece546/lectures/ece546fall12_08.pdf

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