VLSI Design(Fabrication)
-
Upload
trijit-mallick -
Category
Engineering
-
view
97 -
download
1
Transcript of VLSI Design(Fabrication)
Soumita Datta
Ananga Paul
Bidisha Barman
Trijit Mallick
Very-large-scale integration (VLSI) is the process of creating an integrated circuit by combining thousands of transistors into a single chip.
What is VLSI?
HISTORYDuring the mid-1920s, inventors attempted devices that were
intended to control current in solid-state diodes and convert them into triodes.
With the invention of transistors at Bell Labs in 1947, the field of electronics shifted from vacuum tubes to solid-state devices.
Electrical engineers of the 1950s saw the possibilities of constructing far more advanced circuits.
Jack Kilby at Texas Instruments (in September 1958)discovered the first integrated circuit, where he combined all the components and the chip on the same block of semiconductor material.
Although the first integrated circuit was crude and had some problems, the idea was groundbreaking.
All these led to development in > SSI (early 1960s) > MSI (late 1960s) > LSI > VLSI (970s and 1980s).
STEPS FOR FABRICATION ON SI WAFER
Cleaning (Acid process, Dry cleaning)
OxidationPhotolithographyDiffusionMetallization
• It protects the junction from moisture, and also serves as an insulator on the wafer surface.
• It is extremely necessary for the designing and fabrication during diffusion and metallization.In oxidation:
• Wafer is exposed to oxygen & Oxygen molecules diffuse into the wafer.
• A chemical reaction occurs between oxygen and silicon & a layer of oxide grows on the wafer surface.
• Si(solid) + 2H2O SiO2 (Solid) +2 H2
OXIDATION
Photolithography, also termed optical lithography or UV lithography, is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate.
Materials used: Mask, Photo resist, Developer, 10% HF, Acetone
PHOTOLITHOGRAPHY
DIFFUSION
Requirements for diffusion:
• Temperature: 10000C• Gas : N2= 1 L/minute,
O2= 1L/minute.• Boron nitride• Time :
Pre-dip- 15 minutesDriving – 3 hours.
• 10%HF.
SiB
N2
O2
Nitrogen is blown over Si, forming a layer of B.
Now B layer is removed, and Oxygen is blown over the sample. Since Si reacts well with O2, so B penetrates.
1000 C
..
..
. .
.
.....
.
.
..
.
..
.
.
. .
.. ..
.
.
.
.. .
.
n-substrate
BSiO3(BORON GLASS)
[O2+Si+B] BSiO3
P
n-substrate
PBoron glass eached out with 10% HF
METALIZATION• Metallization is the final step in the wafer
processing sequence. Metallization is the process by which the components of IC’s are interconnected by aluminum conductor.
• Metalization is used to create contacts with the silicon and to make interconnections on the chip.
• Desired properties are– low resistivity
• in ohms/square– good adhesion to silicon and insulators– good coverage of steps in chip surface– immunity to corrosion– ductility (so temperature cycles don’t
cause failures)
• For metallization in case of p-type we choose Al and for n-type we choose Ag.
• The process by which metallization is done is known as vacuum evaporation system. We choose it for the following reasons:
• To avoid the oxide of the metal.• Mean path should be free.
Types of EVAPORATION
•Vacuum thermal evaporation system•Vacuum electron beam evaporation system•Vacuum radio frequency generator•Vacuum plasma system
CMOS FABRICATION PROCESS
P-type Substrate
Silicon WaferSi-O2 Layer
A Si-O2 Layer is created by oxidation on top of the wafer
P-type Substrate
Start with clean p-type substrate (p-type wafer)
CMOS FABRICATION PROCESS
P-substrateSi02
photoresist
A Photoresist is coated over the total thing
Opaque area
Transparent area
mask
P-substrate
UV Ray
Masking and exposure under UV light(E)Resist dissolved after developed (D)Pre-shape the well pattern at resist layer
PHOTOLITHOGRAPHY
P-substrate
Removing the unwanted pattern by wet etching
P-substrate
Resist clean
Desired pattern formed
DIFFUSION
P-substrate
Phosphorous ion
P-substrateN-Well
Ion bombardment by ion implantationSiO2 as mask, uncovered area will exposed to dopant ion
P-substrateN-Well
P-substrateN-Well
P-substrateN-Well
P-substrateN-Well
Deposit polisilicon layer
Grow very thin gate oxide
Photolithography and etching toform gate pattern
Arsenic ion
P-substrateN-Well
P-substrate N-Well
P-substrate N-Well
Boron ion
P-substrate N-Well
Ion implantation with Arsenic ion for n+ dopant.
Nmos’s Source and drain with VDD contact formation
Ion implantation with boron for p+ dopant
Pmos’s source and drain formation with GND contact
n+ type silicon P+ type silicon
P-substrate N-Well
P-substrate N-Well
P-substrate N-Well
Deposit CVD Oxide layerthrough out wafer surface
Photo and etching process to make contact
Metal deposition throughout wafer surface
n+ type silicon
P+ typesilicon
COMPLETE CMOS
Vin
P-substrate N-Well
GroundVout Vdd
Photo and etching processes to pattern interconnection
n+ type silicon
P+ typesilicon
Metal contact
SiO2Layer
Polysilicon
Complementary MOS (or CMOS)
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
How is it a digital inverter?
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
How is it a digital inverter?
CASE 1: Vin=0V
VGSN=0V<VT (NMOS IS OFF)
VSGP=VDD>VT (PMOS IS ON)
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
How is it a digital inverter?
CASE 1: Vin=0VVGSN=0V<VT (NMOS IS OFF)VSGP=VDD>VT (PMOS IS ON)
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
How is it a digital inverter?
CASE 1: Vin=0VVGSN=0V<VT (NMOS IS OFF)VSGP=VDD>VT (PMOS IS ON)
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
How is it a digital inverter?
CASE 1: Vin=0VVGSN=0V<VT (NMOS IS OFF)VSGP=VDD>VT (PMOS IS ON)
CASE 2: Vin= VDD
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
How is it a digital inverter?
CASE 1: Vin=0VVGSN=0V<VT (NMOS IS OFF)VSGP=VDD>VT (PMOS IS ON)
CASE 2: Vin= VDD VSGP= 0V<VT (PMOS IS OFF)
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
How is it a digital inverter?
CASE 1: Vin=0VVGSN=0V<VT (NMOS IS OFF)VSGP=VDD>VT (PMOS IS ON)
CASE 2: Vin= VDD VSGP= 0V<VT (PMOS IS OFF) VGSN= VDD>VT (NMOS IS ON)
BASIC CMOS INVERTER• For NMOS: VGSN= Vin
VDSN=Vout
• For PMOS: VGSP= Vin-VDD VDSP= Vout-VDD
How is it a digital inverter?
CASE 1: Vin=0VVGSN=0V<VT (NMOS IS OFF)VSGP=VDD>VT (PMOS IS ON)
CASE 2: Vin= VDDVSGP= 0V<VT (PMOS IS OFF)VGSN= VDD>VT (NMOS IS ON)
INPUT (Vin) PMOS NMOS
0 linear cut off
VTN linear saturation
VM saturation saturation
VDD-VTP saturation linear
VDD cut off linear
Voltage Transfer Characteristics
BY DUALITY & COMPLEMENTATION PROPERTIES
•By Duality: F’=(A’.B’)’ = A+B(PMOS)
•By Complementation: F’=AB (NMOS)
GATE REALISATION
BY DUALITY & COMPLEMENTATION PROPERTIES
•By Duality: F’=(A’.B’)’ = A+B(PMOS)
•By Complementation: F’=AB (NMOS)
GATE REALISATION
GATE REALISATIONBY SUTTON’S METHOD
NMOS: (Bubbled output)
PMOS: (Bubbled input)
GATE REALISATIONBY SUTTON’S METHOD
NMOS: (Bubbled output)
PMOS: (Bubbled input)
India’s Contribution to VLSI Designing:
Indian Institute of Technology and Intel together are working for bringing advancement on VLSI in India.
Lots of conferences on VLSI are going in India in every month and the organization named VLSI Society of India working with industry and upcoming engineer providing finance for their project on VLSI.
The Indian govt. has also took an initiation by launching a VLSI education program across 32 institutes to increase the availability of chip design talent.
Future of VLSI Technology is evolving everyday
and VLSI is the most progressing one it is moving to ULSI.
It has been predicted that VLSI will develop more in the coming decade.
Advantage of VLSI Designing: Compactness: Reduces the Size of
Circuits.
.
Reliability: higher reliability.
Mobility: Increases the Operating speed of circuits
Requires less power than discrete components.
Occupies a relatively smaller area.
Easily available productivity
Disadvantage of VLSI Designing
• Previously the cost was high.
• Still the basic things like mobile phone and other related products are cheaper but high end products are pocket eater.
• Advancement in Indian market is required.
• Lack of training institute, so affects on production in India.
Application of VLSI Designing
From a simple mobile phone to the server used in large companies.
Recent example is Intel’s new upcoming 45 nm integration processor.
Communications ,Microwave and RF
Cryptography. Consumer Electronics Automobiles Space Applications Robotics Health domain.....and list continues to grow.
CONCLUSION We have learnt the steps of Fabrication
on Si Wayfer. We have learnt the CMOS Fabrication
process. Learned about the CMOS inverter and
GATE Realisation. Also learned about the applications of
VLSI design, its advantages and disadvantages.
There is a tremendous scope and growth for those who choose VLSI design as a career.
THANK YOU….