VLSI & ASIC part2

8/13/2019 VLSI & ASIC part2

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1) Explain about setup time and hold time, what will happen if there is setup time and holdtine violation, how to overcome this?

Set up time is the amount of time before the clock edge that the input signal needs to be stable to

guarantee it is accepted properly on the clock edge.Hold time is the amount of time after the clock edge that same input signal has to be held beforechanging it to make sure it is sensed properly at the clock edge.Whenever there are setup and hold time violations in any flip-flop, it enters a state where its outputis unpredictable: this state is known as metastable state (uasi stable state!" at the end of metastablestate, the flip-flop settles down to either #$# or #%#. &his whole process is known as metastability

2) What is skew, what are problems associated with it and how to minimize it? 'n circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal(sent from the clock circuit! arrives at different components at different times.&his is typically due to two causes. &he first is a material flaw, which causes a signal to travel faster

or slower than epected. &he second is distance: if the signal has to travel the entire length of acircuit, it will likely (depending on the circuit#s si)e! arrive at different parts of the circuit atdifferent times. *lock skew can cause harm in two ways. Suppose that a logic path travels throughcombinational logic from a source flip-flop to a destination flip-flop. 'f the destination flip-flopreceives the clock tick later than the source flip-flop, and if the logic path delay is short enough,then the data signal might arrive at the destination flip-flop before the clock tick, destroying therethe previous data that should have been clocked through. &his is called a hold violation because theprevious data is not held long enough at the destination flip-flop to be properly clocked through. 'fthe destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signalhas that much less time to reach the destination flip-flop before the net clock tick. 'f it fails to doso, a setup violation occurs, so-called because the new data was not set up and stable before the netclock tick arrived. + hold violation is more serious than a setup violation because it cannot be fiedby increasing the clock period.*lock skew, if done right, can also benefit a circuit. 't can be intentionally introduced to decreasethe clock period at which the circuit will operate correctly, andor to increase the setup or holdsafety margins. &he optimal set of clock delays is determined by a linear program, in which a setupand a hold constraint appears for each logic path. 'n this linear program, )ero clock skew is merely afeasible point.*lock skew can be minimi)ed by proper routing of clock signal (clock distribution tree! or puttingvariable delay buffer so that all clock inputs arrive at the same time

3) What is slack?

#Slack# is the amount of time you have that is measured from when an event #actually happens# andwhen it #must happen.. &he term #actually happens# can also be taken as being a predicted time forwhen the event will #actually happen#.When something #must happen# can also be called a #deadline# so another definition of slack wouldbe the time from when something #actually happens# (call this &act! until the deadline (call this&dead!.Slack &dead - &act./egative slack implies that the #actually happen# time is later than the #deadline# time...in otherwords it#s too late and a timing violation....you have a timing problem that needs some attention.


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) What is !litch? What causes it "explain with waveform)? #ow to overcome it?

&he following figure shows a synchronous alternative to the gated clock using a data path. &heflip-flop is clocked at every clock cycle and the data path is controlled by an enable. When theenable is 0ow, the multipleer feeds the output of the register back on itself. When the enable isHigh, new data is fed to the flip-flop and the register changes its state


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$) %iven onl& two xor !ates one must function as buffer and another as inverter?

&ie one of or gates input to $ it will act as inverter.&ie one of or gates input to % it will act as buffer.

') What is difference between latch and flipflop?

&he main difference between latch and 11 is that latches are level sensitive while 11 are edgesensitive. &hey both reuire the use of clock signal and are used in seuential logic. 1or a latch, theoutput tracks the input when the clock signal is high, so as long as the clock is logic $, the outputcan change if the input also changes. 11 on the other hand, will store the input only when there is a

risingfalling edge of the clock.

() uild a *1 mux usin! onl& 2*1 mux?


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+ifference between heap and stack?

&he Stack is more or less responsible for keeping track of what#s eecuting in our code (or what#sbeen 2called2!. &he Heap is more or less responsible for keeping track of our ob3ects (our data,well... most of it - we#ll get to that later.!.&hink of the Stack as a series of boes stacked one on top of the net. We keep track of what#sgoing on in our application by stacking another bo on top every time we call a method (called a1rame!. We can only use what#s in the top bo on the stack. When we#re done with the top bo (themethod is done eecuting! we throw it away and proceed to use the stuff in the previous bo on thetop of the stack. &he Heap is similar ecept that its purpose is to hold information (not keep track ofeecution most of the time! so anything in our Heap can be accessed at any time. With the Heap,

there are no constraints as to what can be accessed like in the stack. &he Heap is like the heap ofclean laundry on our bed that we have not taken the time to put away yet - we can grab what weneed uickly. &he Stack is like the stack of shoe boes in the closet where we have to take off thetop one to get to the one underneath it.

) +ifference between meal& and moore state machine?

+! 4ealy and 4oore models are the basic models of state machines. + state machine which usesonly 5ntry +ctions, so that its output depends on the state, is called a 4oore model. + state machinewhich uses only 'nput +ctions, so that the output depends on the state and also on inputs, is called a4ealy model. &he models selected will influence a design but there are no general indications as to

which model is better. *hoice of a model depends on the application, eecution means (for instance,hardware systems are usually best reali)ed as 4oore models! and personal preferences of a designeror programmer

6! 4ealy machine has outputs that depend on the state and input (thus, the 1S4 has the outputwritten on edges!4oore machine has outputs that depend on state only (thus, the 1S4 has the output written in thestate itself.

+dv and 7isadv'n 4ealy as the output variable is a function both input and state, changes of state of the state

variables will be delayed with respect to changes of signal level in the input variables, there arepossibilities of glitches appearing in the output variables. 4oore overcomes glitches as outputdependent on only states and not the input signal level.


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+ll of the concepts can be applied to 4oore-model state machines because any 4oore statemachine can be implemented as a 4ealy state machine, although the converse is not true.4oore machine: the outputs are properties of states themselves... which means that you get theoutput after the machine reaches a particular state, or to get some output your machine has to betaken to a state which provides you the output.&he outputs are held until you go to some other state4ealy machine:

4ealy machines give you outputs instantly, that is immediately upon receiving input, but the outputis not held after that clock cycle.

1-) +ifference between onehot and binar& encodin!?

*ommon classifications used to describe the state encoding of an 1S4 are 6inary (or highlyencoded! and 8ne hot.+ binary-encoded 1S4 design only reuires as many flip-flops as are needed to uniuely encodethe number of states in the state machine. &he actual number of flip-flops reuired is eual to theceiling of the log-base-9 of the number of states in the 1S4.+ onehot 1S4 design reuires a flip-flop for each state in the design and only one flip-flop (the

flip-flop representing the current or 2hot2 state! is set at a time in a one hot 1S4 design. 1or a statemachine with - $; states, a binary 1S4 only reuires < flip-flops while a onehot 1S4 reuires aflip-flop for each state in the design1=>+ vendors freuently recommend using a onehot state encoding style because flip-flops areplentiful in an 1=>+ and the combinational logic reuired to implement a onehot 1S4 design istypically smaller than most binary encoding styles. Since 1=>+ performance is typically related tothe combinational logic si)e of the 1=>+ design, onehot 1S4s typically run faster than a binaryencoded 1S4 with larger combinational logic blocks

12) #ow to calculate maximum operatin! fre.uenc&?

13) #ow to find out lon!est path?

?ou can find answer to this in timing.ppt of presentations section on this site

1) +raw the state dia!ram to output a /1/ for one c&cle if the se.uence /-11-/ shows up "theleadin! -s cannot be used in more than one se.uence)?


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1$) #ow to achieve 10- de!ree exact phase shift?

/ever tell using invertera! dcms an inbuilt resource in most of fpga can be configured to get $@% degree phase shift.b! 6ufgds that is differential signaling buffers which are also inbuilt resource of most of 1=>+ can

be used.

1') What is si!nificance of ras and cas in +4?

S7A+4 receives its address command in two address words.'t uses a multiple scheme to save input pins. &he first address word is latched into the 7A+4 chipwith the row address strobe (A+S!.1ollowing the A+S command is the column address strobe (*+S! for latching the second addressword.Shortly after the A+S and *+S strobes, the stored data is valid for reading.

1() 5ell some of applications of buffer?

a!&hey are used to introduce small delaysb!&hey are used to eliminate cross talk caused due to inter electrode capacitance due to closerouting.c!&hey are used to support high fanout,eg:bufg

10) 6mplement an 7+ !ate usin! mux?

&his is the basic uestion that many interviewers ask. for and gate, give one input as selectline,incase if u r giving b as select line, connect one input to logic #%# and other input to a.

1) What will happen if contents of re!ister are shifter left, ri!ht?

't is well known that in left shift all bits will be shifted left and 0S6 will be appended with % and inright shift all bits will be shifted right and 4S6 will be appended with % this is a straightforwardanswer

What is epected is in a left shift value gets 4ultiplied by 9 eg:consider %%%%B$$$%$< a left shiftwill make it %%%$B$$%9@, it the same fashion right shift will 7ivide the value by 9.

2-)%iven the followin! 8689 and rules, how deep does the 8689 need to be to preventunderflow or overflow?

AC05S:$! freuency(clkB+! freuency(clkB6! ate 1i -] 4etal 1i -] 1'6 1i

1irst, let#s review fundementals. + standard-cell +S'* consists of at least 9 do)en manufacturedlayersmasks. 0ower layers conists of materialsmaking up the actual *48S transistors and gates ofthe design. &he upper E-; layers are metal layers used ti connect everything together. +S'*s, ofcourse, are not intended to be fleible like an 1=>+, however, important 2fies2 can be madeduring the manufacturing process. &he progression of possible fies in the manufacturing life cycleis as listed above.

+n A&0 fi means you change the KerilogKH70 code and you resynthesi)e. &his usually implies a

new =lance_Aoute. A&0 fies would also imply new masks, etc. etc. 'n other words - start fromscratch.

+ >ate 1i means that a select number of gates and their interconections may be added orsubtracted from the design (e.g. the netlist!. &his avoids resynthesis. >ate fies preserve theprevious synthesis effort and involve manually editing a gate-level netlist - adding gates, removinggates, etc. >ate level fies affect +00 layers of the chip and all masks.

+ 4etal 1i means that only the upper metal interconnect layers are affected. *onnections may bebroken or made, but new cells may not be added. + Sewing ìt is a means of adding a new gate intothe design while only affecting the metal layers. Sewing ìts are typically added into the initialdesign either at the A&0 level or during synthesis by the customer and are part of the netlist. +

4etal 1i affects only the top layers of the wafers and does not affect the 2base2 layers.Sewing ìts are modules that contain an unused mi of gates, flip-flops or any other cellsconsidered potentially useful for an unforseen metal fi. + Sewing ìt may be specified in A&0 byinstantiating the literal cells from the vendor library. &he cells in the kit are usually connected suchthat each cell#s output is unconnected and the inputs are tied to ground. *locks and resets may bewired into the larger design#s signals, or not.

+ 1'6 1i (1ocussed 'on 6eam! 1i is only performed on a completed chip. 1'6 is a somewhateotic technology where a particle beam is able to make and break connections on a completed die.1'6 fies are done on individual chips and would only be done as a last resort to repair an otherwisedefective prototype chip. 4asks are not affected since it is the final chip that is intrusively repaired.

*learly, these sorts of fies are tricky and risky. &hey are available to the +S'* developer, but mustbe negotiated and coordinated with the foundry. +S'* designers who have been through enough ofthese fies appreciate the value of adding test and fault-tolerant design features into the A&0 code


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so that Software 1ies can correct mior silicon problems


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Alock +omain Arossin!D D D

&he following section eplains clock domain interfacing

8ne of the biggest challenges of system-on-chip (S8*! designs is that different blocks operate onindependent clocks. 'ntegrating these blocks via the processor bus, memory ports, peripheral busses,and other interfaces can be troublesome because unpredictable behavior can result when theasynchronous interfaces are not properly synchroni)ed

+ very common and robust method for synchroni)ing multiple data signals is a handshaketechniue as shown in diagram below &his is popular because the handshake techniue can easilymanage changes in clock freuencies, while minimi)ing latency at the crossing. However,handshake logic is significantly more comple than standard synchroni)ation structures.

1S4$(&ransmitter! asserts the re (reuest! signal, asking the receiver to accept the data onthe data bus. 1S49(Aeceiver! generally a slow module asserts the ack (acknowledge!signal, signifying that it has accepted the data.

it has loop holes: when system Aeceiver samples the systems &ransmitter re line and&ransmitter samples system Aeceiver ack line, they have done it with respect to theirinternal clock, so there will be setup and hold time violation. &o avoid this we go for doubleor triple stage synchroni)ers, which increase the 4&61 and thus are immune tometastability to a good etent. &he figure below shows how this is done.


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6locking vs /on-6locking. . .

self triggering blocks -

module osc9 (clk!"output clk"reg clk"initial N$% clk %"always I(clk! N$% clk J clk"endmodule

+fter the first I(clk! trigger, the AHS epression of the nonblocking assignment is evaluated andthe 0HS value scheduled into the nonblocking assign updates event ueue.6efore the nonblocking assign updates event ueue is 2activated,2 the I(clk! trigger statement isencountered and the always block again becomes sensitive to changes on the clk signal. When thenonblocking 0HS value is updated later in the same time step, the I(clk! is again triggered.

module osc$ (clk!"output clk"reg clk"initial N$% clk %"always I(clk! N$% clk clk"

endmodule

6locking assignments evaluate their AHS epression and update their 0HS value without


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interruption. &he blocking assignment must complete before the I(clk! edge-trigger event can bescheduled. 6y the time the trigger event has been scheduled, the blocking clk assignment hascompleted" therefore, there is no trigger event from within the always block to trigger the I(clk!trigger.

6ad modeling: - (using blocking for se. logic!

always I(posedge clk! begin$ d"9 $"E 9"end

Aace *onditionalways I(posedge clk! $d"always I(posedge clk! 9$"always I(posedge clk! E9"

always I(posedge clk! 9$"always I(posedge clk! E9"always I(posedge clk! $d"

always I(posedge clk! beginE 9"9 $"$ d"end

6ad style but still works

>ood modeling: -

always I(posedge clk! begin$ J d"9 J $"E J 9"end

always I(posedge clk! beginE J 9"9 J $"

$ J d"end


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/o matter of seuence for /onblockingalways I(posedge clk! $Jd"always I(posedge clk! 9J$"always I(posedge clk! EJ9"

always I(posedge clk! 9J$"always I(posedge clk! EJ9"always I(posedge clk! $Jd"

>ood *ombinational logic :- (6locking!

always I(a or b or c or d! begintmp$ a _ b"tmp9 c _ d"y tmp$ tmp9"end6ad *ombinational logic :- (/onblocking!

always I(a or b or c or d! begin will simulate incorrectlytmp$ J a _ b" need tmp$, tmp9 insensitivitytmp9 J c _ d"y J tmp$ tmp9"end

4ied design: -

Cse /onblocking assignment.'n case on multiple non-blocking assignments last one will win.


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:erilo! 84

VLSI & ASIC part2

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