ANNA UNIVERSITY PRACTICAL EXAMINATION, APRIL 2011

SUB. CODE: EC2357 QUESTION PAPER SUB: VLSI DESIGN LAB

TIME DURATION: 3 HOURS MAXIMUM MARKS: 100

1. a. Simulate a serial adder using Xilinx ISE 9.1i b. Implement a 8:3 encoder using XC3S400 FPGA trainer kit.

2. a. Simulate a PRBS generator using Xilinx ISE 9.1i b. Implement a half adder using XC3S400 FPGA trainer kit.

3. a. Simulate an accumulator using Xilinx ISE 9.1i b. Implement a full adder using XC3S400 FPGA trainer kit.

4. a. Draw the schematics of a CMOS NAND gate . Generate the layout automatically and and simulate it. b. Implement a 3:8 decoder using XC3S400 FPGA trainer kit.

5. .a. Simulate a synchronous updown counter using Xilinx ISE 9.1i b. Implement a 4 bit multiplier using XC3S400 FPGA trainer kit.

6. a. Simulate a universal shift register using Xilinx ISE 9.1i b. Implement a half subtractor using XC3S400 FPGA trainer kit.

7. a. Simulate a 8 bit adder using Xilinx ISE 9.1i b. Implement a 1:8 demultiplexer using XC3S400 FPGA trainer kit.

8. a. Simulate a JK flip-flop using Xilinx ISE 9.1i b. Implement a full subtractor using XC3S400 FPGA trainer kit

9. a. Simulate a SR flip-flop using Xilinx ISE 9.1i b. Implement a 4:1 multiplexer using XC3S400 FPGA trainer kit

10. a. Generate the layout of a CMOS inverter and simulate .Measure the dissipated power. Find also the dissipated power after adding 0.01 pf capacitor at the output. b. Simulate a 8 bit multiplier using Xilinx ISE 9.1i

11. a. Draw the schematics of the function F= AB + C (A+B) and simulate it.. Generate the SPICE file. b. Simulate a T flip flop using Xilinx ISE 9.1i 12. a . Draw the schematics of the function F= (AB + C)D . Generate the layout automatically and and simulate it. b. Simulate a D flip flop using Xilinx ISE 9.1i

13. a. Simulate a serial adder using Xilinx ISE 9.1i b. Implement a 4 bit multiplier using XC3S400 FPGA trainer kit.

14 a. Simulate a PRBS generator using Xilinx ISE 9.1 b. Implement a half subtractor using XC3S400 FPGA trainer kit.

15. a. Simulate an accumulator using Xilinx ISE 9.1i b. Implement a full subtractor using XC3S400 FPGA trainer kit.

16 a. Draw the schematics of a CMOS NOR gate . Generate the layout automatically and and simulate it. b. Implement a 1:8 demultiplexer using XC3S400 FPGA trainer kit.

17. a. Simulate a synchronous updown counter using Xilinx ISE 9.1i b. Implement a 4:1 multiplexer using XC3S400 FPGA trainer kit.

18. a. Simulate a universal shift register using Xilinx ISE 9.1i b. Implement a half adder using XC3S400 FPGA trainer kit.

19 a. Simulate a 8 bit adder using Xilinx ISE 9.1i b. Implement a 8:3 encoder using XC3S400 FPGA trainer kit.

20. a. Simulate a JK flip-flop using Xilinx ISE 9.1i b. Implement a full adder using XC3S400 FPGA trainer kit.

21. a. Simulate a SR flip-flop using Xilinx ISE 9.1i b. Implement a 3:8 decoder using XC3S400 FPGA trainer kit.

22. a. Generate the layout of a CMOS inverter and simulate .Measure the dissipated power. Find also the dissipated power after adding 0.1 pf capacitor at the output. b. Simulate a 6 bit multiplier using Xilinx ISE 9.1i

23. a. Draw the schematics of the function F= AB +B C +AC and simulate it.. Generate the Spice file. b. Simulate a T flip flop using Xilinx ISE 9.1i

24. a. Draw the schematics of the function F= AB C +D . Generate the layout automatically and and simulate it. b. Simulate a D flip flop using Xilinx ISE 9.1i