Cadence® Virtuoso® Digital Implementation is a complete synthesis and place-and-route system. It enables small digital block implementation in the context of an advanced analog-driven methodology. Driven by unified design intent and abstraction, Virtuoso Digital Implementation automates synthesis and optimizes place-and-route to accelerate the mixed-signal design process and ensure the highest quality of silicon.

Virtuoso Digital ImplementationAutomatic implementation of digital blocks in mixed-signal designs

1 Virtuoso Digital Implementation enables an RTL-to-GDSII solution that is limited in capacity. Encounter RTL Compiler is limited to a final mapped instance count of 50k instances or 200k generic instances. Encounter Digital Implementation System is limited to a capacity of 50k instances. Two Virtuoso Digital Implementation licenses can be combined (“stacked”) to double the capacity limits. For users who require larger or unlimited capacity, other Encounter products are available.

Virtuoso Digital Implementation

Designed to complement the Virtuoso Layout Suite, Virtuoso Digital Implementation enables capacity-limited1 execution of a complete digital implementation solution from RTL-to-GDSII. Targeting mixed-signal designs that contain small digital blocks, Virtuoso Digital Implementation enables Cadence Encounter® RTL Compiler synthesis and Encounter® Digital Implementation System functionality. Encounter RTL Compiler provides a high-performance synthesis solution to help you efficiently develop smaller, faster, lower-power chips. Encounter Digital Implementation System uses extremely fast, integrated engines to optimize digital block implementation. Both technologies are based on the industry-leading Encounter digital IC design platform, proven to deliver high quality of silicon (Figure 1).

Benefits

• Enables automated digital implementation for small digital blocks, including synthesis and physical implementation

• Matches the functionality enabled by Encounter Digital Implementation System L

• Ensures the best quality of silicon for digital logic (speed, area, and power)

• Integrates with the Virtuoso platform through unified design intent and abstraction to enable a complete implementation solution2

• Significantly reduces the time to design closure

LEF/DEFOpenAccess

VIRTUOSO PLATFORM

Virtuoso Spec-Driven Environment

Virtuoso Spectre Circuit Simulator

Virtuoso UltraSimFull-Chip Simulator

Virtuoso XL Layout Editor

Virtuoso Chip Assembly Router

Assura Physical Verification

ENCOUNTER PLATFORM

Encounter RTL CompilerSoC Encounter L

Figure 1: Virtuoso Digital Implementation

www.cadence.com 2

Virtuoso Digital Implementation

• Enables Cadence First Encounter® silicon virtual prototyping

• Supports full-timing modeling of mixed-signal blocks with built-in physical optimization for rapid timing convergence

• Supports timing-driven implementation using a common timing engine with a signoff quality delay calculator

• Integrates power planning, power routing, and power analysis

• Supports multiple power domains

• Easy-to-use clock tree synthesis handles multiple and re-convergent clocks

• Includes clock gating for low-power design

• Seamlessly supports SDC

• Supports libraries and rules of multiple process technologies down to 28nm

• Supports rectilinear blocks

• Supports LEF/DEF data transfer via standard interfaces and OpenAccess3

Features

Rtl synthesis

• Read/write standard inputs/outputs

• Built-in high-performance data path

• Arithmetic optimizations

• Total negative slack (TNS) optimization

• Testability analysis and scan insertion

• Clock gating

• Multi-Vt leakage power optimization

Silicon virtual prototyping

• Based on proven First Encounter technology

• Full gate-level placement

• Fast detailed trial routing (10x faster than traditional detailed routers) – Higher correlation with the final implementation

• Fast analysis with 2.5-D parasitic extraction (10x faster than traditional extractors)

• Delay and timing analysis using industry-standard timing library and constraints formats

• Physical optimization technology for advanced timing closure

• In-place optimization (IPO) for cell resizing, buffer insertion, and load splitting – Leakage power optimization – Advanced logic restructuring option

Routing

• Industry-proven routers

• Support for advanced engineering change order (ECO) routing

• Wire editor environment for custom edits

Clock tree synthesis

• Ultra high-speed clock tree synthesis to minimize both clock skew and insertion delay

• Support for gated clocks and multiple clock domains

• Post-route clock tree optimization

• Useful skew analysis and optimization

Advanced power planning

• Quick power planning, including static and dynamic power consumption analysis

• Built-in power/IR drop analysis*

• Fine mesh routing supported with embedded macro blocks

• Power-grid design results in IR drop numbers within 10% of SPICE

• Interface to signoff power-grid verifi-cation requires an Encounter Power System license, which must be purchased separately.

Ease-of-use

• Easy-to-use, built-in signal and power wire editing functionality

• Tcl programming interface throughout the flow

• Intuitive and helpful commands

• Familiar use model

• Easy-to-learn system enables ramp up within a week

• Helpful reports for all steps

Specifications

Input

• HDL (to synthesis): Verilog, VHDL, SystemVerilog (directives, pragmas)

• Logical and timing library: library format (.alf), TLF, or .lib

• Physical library: LEF

• Mixed-language/mixed-level netlist: gate-level netlist in Verilog, gate-level EDIF netlist

• Timing constraints: SDC

• Floorplan information: PDEF

• Detailed floorplan information: DEF

• Delay information: SDF

• Interconnect parasitics: DSPF/RSPF, SPEF

2 Requires Virtuoso Layout Suite XL or Virtuoso Layout Suite GXL.

3 The loading/display/data handling of custom objects—including Pcells, RODs, multi-part paths, and fig groups—is enabled by the Encounter Mixed-Signal GXL Option, which must be purchased separately.

Virtuoso Digital Implementation

Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com

© 2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Encounter, First Encounter, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders.

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Output

• Optimized gate-level netlist (from synthesis)

• Netlist: DEF, Verilog

• Interconnect parasitics: DSPF, SPICE, SPEF

• Delay information: SDF

• Floorplan and placement: DEF, PDEF

• GDSII

Platforms

• Linux (32- and 64-bit)

• Solaris (64-bit)

• SOLX86 (64-bit)

• IBM AIX (64-bit)

Cadence Services and Support

• Cadence application engineers can answer your technical questions by telephone, email, or Internet—they can also provide technical assistance and custom training

• Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom

• More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet

• Cadence Online Support gives you 24x7 online access to a knowledgebase of the latest solutions, technical documen-tation, software downloads, and more