Virtual Reliability Qualification - Thierry LEQUEU · 2016-10-23 · knowledge-based Reliability...
Transcript of Virtual Reliability Qualification - Thierry LEQUEU · 2016-10-23 · knowledge-based Reliability...
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Eindhoven University of Technology
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Virtual Reliability Qualification
Prof. Kouchi (G.Q.) [email protected]
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1. Development trends
2. Consequences for reliability• Thermo-mechanical problems• Motivations
3. Virtual prototyping and qualification • The Methodology• Status Quo/challenges• Demonstrators
4. Conclusions
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1. Development trensd
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Telecommunication in 70sTelecommunication in 70s
1. Background (Development Trends)
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Computing in 70sComputing in 70s
1. Background (Development Trends)
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Consumer electronics Consumer electronics annoanno 20042004
1. Background (Development Trends)
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Consumer Electronics in near futureConsumer Electronics in near future
1. Background (Development Trends)
Soft and wearable electronics
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• Moving from a world of electronic “boxes” to the world of ambient intelligence where technology is built into our environment via connectivity and integration.
• Focus on function, not the devices that enable them.
•sensitive to people's needs•personalized to their requirements•anticipatory of their behavior and•responsive to their presence
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Consumers wishesSmaller, smarter, lighter, faster, cheaper, more flexible,
more convenient, more reliable and functionalities.
Development trends •Miniaturisation down to nano-scales•Increasing levels functionality & technology integration•Eco-designs
•Cost reduction•Short-time-to-market•Outsourcing
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1996 1999 2002 2005 2008 2011
Fea
ture
Siz
e (n
m)
500
350
250
180
130
100
70
50
35
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Dense Lines (DRAM Half-Pitch)1994
1997
1998 & 1999
2000
ITRS Roadmap History
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Process technology evolutionSystem-on-Chip: standardization
• Standard CMOS density will continue to grow exponentially, driving down the cost of digital data processing and storage– More Moore : System-on-Chip
• But realized digital design complexity increasingly lags behind the potential of new technologies, while investments soar– Decelerating long-term semiconductor market
growth to single digit
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Is the Roadmap Going to End?Let’s see some famous forecasts
“ I think there is a world market for maybe five computers ”
Thomas Watson, Chairman of IBM, 1943
“ Computers in the future may weigh no more than 1.5 tons ”
Popular Mechanics Magazine, 1949
“ 640K ought to be enough for anybody ” Bill Gates, 1981
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Alternative Switching Technologies
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Packaging & assembly
•Wire diameter < 10 microns•Interconnect pitch of NLWSP < 20 microns•Thickness of copper film/PCB < 10 microns•Microvia diameter < 20 microns
Not only the wafer technology, packaging and assembly are also going beyond visualization!
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Waferfab
Package System
Waferfab
Package System
Waferfab
Package System
IC – BoardTotal signalintegrity
IC – packageWLP, NSWLP
Package -boardEmbedded, MCM
•Total system performance•SiP•Nano-electronics
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More Moore and more than mooreComplementing, not competing
More Moore: SoC- Programmable monolithic IC • Advanced baseline CMOS, standard packaging• Maximize utilization of (expensive) mask sets• Diversification is in the software & embedded IP mix
More than Moore: SiP - Multi-technology module • Mature and advanced wafer processes, advanced packaging• Maximize utilization of dedicated option fabs• Diversification is in the components & technology mix
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• 3-D Stacking of ICS or Package Structures, Similar to PWB– Macro dimensions– Vertical stack up– Testable– System board to Complete
System
• 3 -D Build up, similar to IC Fabrication– Micro to Nano dimensions– Sequential build up and test
similar to MCM-D and IC– Wafer to IC concept for high
yield
SIP1 SIP3
M E M S Ga -As SIPSOC
SOCMEMS SIPGa-As
Examples of technology and function integration
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Generic sub-system
(digital) communication bus
storage radio
µP sensor
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System-in-Package domains – 3
SiP 3e.g., MOEMS
SiP 2e.g., Passive
Integration
SiP 1e.g., MCM
SoC…electron
ics…IC
process…one ICMore
than… →In
creasing
value p
rop
ositio
n
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Stacked BGA production (leading vendor)
2000 2001 2002 2003
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Eco-DesignDesigning environmentally compatible products/processeswhile maintaining price/performance and quality characteristics.
Key Focus Areas:•Energy Usage (Products & Manufacturing Processes)•End-of-Life Management•Product Packaging•Removing the boxes
Materials
Product Process
•Virtual prototyping & qualification
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Paradigm shift: From Yellow to Purple
Paradigm shift
2003
1993
19881983
1978
1973
1998
Qty$
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2. Consequences for reliability
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ReliabilityThe probability that a product in operation will survive under certain conditions during a certain period in time. IEC50 (191)
FAILURE RATE (FITS, FPM)
LOG TIME
EFR ( Early Failure Rate; Infant Mortality)
Onset of wearout
Intrinsic Failure
YEARS MONTHS
Conventionalbathtub curve
QualityThe totality of features and characteristics of a product or service
that bear on its ability to satisfy stated or implied need. ISO 8420
Our scopeFrom 0 hour to life time
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•Multi-scale in both time and geometric domains with scale factors going up to 109.
•Strong interactions among different§disciplines (electrical, thermal, mechanical, physics, chemical, material science, etc.) §technologies (IC, packaging, assembly, system, soft and hardware)§failure modes and failure mechanisms
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•Behaviour is strongly non-linear, stochastic, time andtemperature dependence.
•Greatly increased loading intensity/loading steps
•Strict demand on and challenges for ensuring quality, robustness and reliability to cover the totalvalue chain
•Greatly increased design complexity and shrinking of design margin to nano levels.
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Q&R= ???f1(b1, b2,.. b i..) f2(c1, c2,.. ci..) f3(t1, t2,.. ti..) db dc dt
b: Business variables c: Consumer variablest: Technical variables
f3(t1, t2,.. ti..)= ???F1(material) F2(process) F3(product)
Q&R is innovation and integration of innovations
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Example of various cracks emanating from the edge of bond pads.May be caused by interface defects
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Pattern shift (Power line) caused by packaging stresses
Warpage caused by wafer thinning:200mm wafer thinned to 50 um
Cracking as a result of electromigration
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crack inside die
substrate
die
Die cracking in flip chip
CrackDelamination
Chip
Die attach voidMold compound filler particle
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Wire failures
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Failure Mode (SnAg)
Crack within Solder
Solder
Crack within solder
Si
Solder
Si
Failure Mode (SnAgCu)
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Delamination
die
underfill
delaminationCrack
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Flip Chip Solder Joint Voiding
Voiding
Underfil Voiding
Chip on Board Globtop Voiding
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Voids caused by molding compound shrinkage
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BucklingMEMS processing challenges:
Buckling & postbuckling of membrane during CMOSmicromachning
Stress gradients between the top and the bottom layers of a film
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Releasing MEMS: Stiction problem
• Surface forces (van der Waals, hydrogen bonding, etc.) are much stronger than bulk forces (spring restoring forces, gravity)
• Consequence: MEMS stict upon contact
• Common for MEMS that are mechanically compliant or have small gaps
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4. Problems and Challenges(Problems)
Overstress- Cracks (die, plastic, wirebond, etc. )- Delamination- Pop-corn- Buckling- Yields (ball shear, pattern shift, etc.)- Warpage - Large deformation- Electro/thermal/stress migration- Voiding- …...
Wear out- Fatigues- Creep- Wear- …..
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• New and combined failure modes &mechanisms
• >65% of failures thermo-mechanical related!
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No appropriate thermo-mechanical design method•Experience and trial-error based design method•Empirical, phenomenological, case dependent, •Sub-optimal product/process•High development costs
No appropriate thermo-mechanical qualification method •Time and money consuming•Unclear correlation between application profiles with spec. and accelerated testing•No guarantee for extrapolating to outside of the spec. •No satisfied coverage for quality, robustness and reliability
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New Paradigm of Reliability
To meet the needs of tech. trends, a new & knowledge-based Reliability Paradigmis a must.
The scientific successes of many micro/nano-related technology developmentwould never lead to a business success without breakthroughs in the way that we are handling reliability through the whole value chain .
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3. Virtual prototyping and qualifications
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Reliable & efficient prediction models
Advanced simulation based optimization methods
Virtual Thermo-Mechanical Prototyping
Sustanable Profitability
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Conceptdevelopment Design
PrototypingQualification Redesign
Objectives and benefits• Short-time-to-market• Cost reduction• Product/process optimization• Quality, robustness and reliability insurance
Conceptdevelopment Design
Virtual prototyping
Qualification
Virtual qualification
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Computational methods Experimental
Methods
Product &processinputs
Material models
Damage models& failure criteria
Reliable & efficient simulation models
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• Process parameters (manufacturing, assembly, testing, reliability qualifications, field use)
• Product parameters (geometry,materials,tolerance design,interface design, defects, etc.)
Determining• loading and loading history; material behavior; initial stress;defects & damage initiation and evolution • life time and performance of product/process
!!!!!!!!! Inputs must be reliable !!!!!!!!!!!!
All statistic in nature
40C
for 21
days
140C for 3 minutes
Product &processinputs
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Material models
Damage models& failure criteria
- Constitutive law and damage models cannot be partitioned anymore
- Size effects* Microstructures and their evolutions* Gradient effect (chemical, electrical, thermal and mechanical)* Surface effect
- Strong process-dependence Temperature, time, constraint, stress, interfaces & reactions
- Multi-scale damage, initiation, failure criteria and process-dependent evolution
- Ultimate aim: Material design rules to tailor the properties for specific need
• Material & damage modelsLaws governing the behavior of materials & interfaces
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Computational methods Experimental
Mechanics
Deterministic
Stochastic
Combined computational &
experimental mechanics
Characterization
Verification
•Non-continuum; •Multi-scale (bridging gaps); •Multi-physics;•Multi-failure mode;•Multi-process; •Nonlinear;•3D applications;•Efficient & accurate•Advanced FEM tool (MARC)
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In principal, all the simulation results are wrong, unless you can prove they are right.
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Simulation based optimization
Optimization based on and integrated with advanced simulation models
• Maximum & minimum• Robust design
• Parameter sensitivityunder given bounds of design and response parameters
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Material ParametersGeometry
Boundary Conditions
Process parameters
DeformationStresses / Strains
Fatigue, Creep, Crack…...
Scatter
Uncertainty
1 How large is the scatter of the output parameters?
2 What is the probability that output parameters do not
fulfil design criteria (failure probability)?
3 How much does the scatter of the input parameters
contribute to the scatter of the output (sensitivities)?
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Sequential optimization
Optimum
Design spaceStep by step to optimum
Determine next point using
info from the path
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Compact-model optimization
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Simulation tool
DOE RSM
Design specification
Criteriasatisfied?
N
Y
Optimization-maximum & minimum-parameter sensitivity-robust design
Reliable &efficient parametric models
Responseparameter(s)
Design parametersand spaces
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ProblemExpensive for nonlinear responses
ObjectiveTo develop smart infill sampling strategy & criteria for efficient and reliable RSM development and global optimization
MethodEGO (Efficient Global Optimization): Expected Improvement (low objective function in optimal objective region & high uncertainty in larger error region)
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start
DOE(MLH)
RSM(Kriging)
Obj?EGO/EI ofObj+RSM
EGO/EI of RSM
EI<limit? EI<limit? Startoptim
Add multi-pointsOptimalachieved
Optimalachieved
Adding new multi DOE points smartly according to the results of EGO
yy
n n
Accurate RSMGlobal optimization
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Current IC stress design rules
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DelaminationPassivation crack
Pattern shift
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1 Wafer Models
2 Packaging Models
3 IC Models
Check & Improvement
Package stressesWafer stresses
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2D modelwith delaminationand crack
Delamination - Crack energy criteria
Aim: • Predict J-integral values• Determine effect of 2nd metal
level
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Deformation mechanism Tensile stresses distribution
• Delamination may lead to passivation cracks and pattern shift.
• Depending on metal layout.• Critical crack location is identified.
Influence of IC/compound delamination on passivation cracks/pattern shift
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Experimental and numerical results
• Special test samples designed for the carrier product.• Observations compared with simulations.• With the verified models a wide design space simulated.
Metal shift
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L_delam
a L2
w
0 0.01
0.02 0.03 0 0.02 0.04 0.06 0.08 0.1
0 0.01 0.02 0.03
J (N/mm)
a (mm)
W (mm)
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CompoundIC (Die)
LeadsLeadframe
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Stress Evolution for Nominal Design
Die Attach
Moulding
TCT -65ºC
TCT +150ºC
TCT -65ºC
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Results - Comparison with FEM
U-field X-direction
V-field Y-direction
W-field Z-directionW-field Z-direction
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Predicted responses in 3D
150 100 50 0
-50
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1t_lf 0.020.03
0.040.05
0.060.07
0.08
t_solder
-100-50
050
100150200
top1
Die Attach
solder t
hickness
leadframe thickness
Predicted responses in 3D
40 30 20 10 0
-10 -20 -30
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1t_lf 0.020.03
0.040.05
0.060.07
0.08
t_solder
-40-30-20-10
01020304050
top2
Moulding
Predicted responses in 3D
-460 -470 -480 -490 -500 -510 -520 -530 -540
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1t_lf 0.020.03
0.040.05
0.060.07
0.08
t_solder
-550-540-530-520-510-500-490-480-470-460-450
top3
TCT -65ºC
Predicted responses in 3D
-60 -70 -80 -90
-100
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1t_lf 0.020.03
0.040.05
0.060.07
0.08
t_solder
-110-100
-90-80-70-60-50
top4
TCT +150ºC
Predicted responses in 3D
-290 -300 -310 -320 -330
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1t_lf 0.020.03
0.040.05
0.060.07
0.08
t_solder
-340-330-320-310-300-290-280
top5
TCT -65ºC
Top Die Stress Evolution for Design Space
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0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
-600 -595 -590 -585 -580 -575
Pro
babi
lity
objective
Histogram Monte Carlo
Sensitivity to Solder Thickness
Stress
Pro
babi
lity
TCT -65ºC, Max. Top Die Stress Histogram
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Solder joint failure under thermal loading
Nickel Pad
Cu Pad
FR4 PCB
Silicon Chip
Solder Bump
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Finite Element Analysis on solder joint reliability
Geometricinputs
Models of material behavior(properties & damage
evolution)
Loading&boundary conditions
Failure modes
Given product/process design parameters & spaces
Reliability Prediction andQualification Models
Reliability Qualification
Computational methods
Characterisationand verification
Experiments
2. Methodologies
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Creep (?)•Time dependent inelastic strain under constant load and elevated temperature•Three phases: Primary (decrease SR); secondary constant(SR); tertiary(increase SR)
Homologous temperature (?)Thom=Tcurrent/Tmelting
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plcr
eq
el
eqεεεε &&&& ++=
plcrinel εεε &&& ==
plcrinel εεε &&& +=crinel εε && =plinel εε && =
Extended Maxwell
Maxwell
Elastic-plastic
Bingham
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)()()( 321 tfTffcr σε =&f1 (σ)=Aσn
f1 (σ)=B exp(ασ)f1 (σ)=C (exp(ασ)-1)f1 (σ)=Dsinh(βα)f1 (σ)={Dsinh(βα)}m
f2(T)=exp (-Q/RT)R:boltzmann constant; T absolute tem.; Q apparent activation energy
f3 (t)=a tn
f3 (t)=(1+bt1/3)exp(kt)
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Fatigue Life
Governing Parameter
Stress
Strain
Energy
Fracture
Damage
CN mf =σ
CN pmf =ε
( )[ ] CN pmkf =− εν 1
cp
cp
pc
pc
cc
cc
pp
pp
f NF
NF
NF
NF
N+++=
1
CWN pmf = cpe
tot WWWW ++=
( ) pm WJKYYCdNda
∆∆∆∆∆= ,,:,
D: E, σ, P, W
1910
Coffin-Manson 1953
Morrow1965
1970
Morrow 1964
Manson 1973
1980
CS
N pmf =
εσ λ
JPL, CIT 1994
Guo 1993
( )[ ] CWN pmkf =−1ν Solomon 1995
2. Methodologies
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Finite Element Model-7x7Matrix Array
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Equivalent Plastic Strain Distribution in Solder Joints at the End of 2nd Cycle
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Fatigue Life Model: Manson_Coffin Based Empirical Model
803B2390B7
711A41530A1
N50%(Test)
Case
0.015 0.02 0.025 0.030
500
1000
1500
2000
N50
%
∆εavN50%
Average InelasticStrain
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Fatigue Life Model: Manson_Coffin Based Empirical Model
0.015 0.02 0.025 0.030
500
1000
1500
2000N
50%
data1 develop verification
( ) 49.2um10448.0Life −ε∆=
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Sensitivity to N50%
What are the most sensitive parameters to N50%?
• Most sensitive parameters to N50%:– Substrate pad diameter (an increase in substrate value,
has a decreasing effect to the reliability N50%)– Solder volume– CTE of the PCB
• These parameters need a good income inspection
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Effects of component size (DNP)
0
200
400
600
800
1000
1200
1400
1600
1800
"1.25" "1.4" "1.6" "1.95" "2.1"
DNP(mm)
N50
%(c
ycle
s)
Modeling
Test
1.25mm 2.1mm
N50%=1410
N50%=652
54%
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Example: Optimizing wire loop design to prevent wire breakProblem: Interconnect wire break is the dominant failure in electronic packaging. Figs. 1 & 2 show the failure on the stitch and the ball side, respectively. There is urgent industrial need to design optimal wire loop in order to prevent possible wire breaks.Method: Due to the large scale difference, global-local method is used in developing reliable FEM models to simulate the stress levels in a wire, in combination with nonlinear material model of the wire. From the global package model, wire deformations are obtained and serve as the input for the local wire model.
Fig.1Fig. 2
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Correlation with Interferometry Measurements
Temp Measurements Modeltransparent black
175ºC
250ºC
20ºC
sensor side
text side
cool down
heat up
∆z top = 25µm
∆z top = 25µm
∆z bottom = 5µm
∆z bottom = 25µm
250ºC
∆z top = 23µm∆z bottom = 11µm
20ºC∆z top = 31µm
∆z bottom = 10µm
20ºC
∆z corner top = 12µm∆z corner bottom = 8µm
IC
ICIC
250ºC
∆z top = 8µm∆z bottom = 7µm
IC
gap
gap
gap
gap
gap
gap
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Wire fatigue - principle
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Result: Optimized wire shape
looppart
loopheight
stitchdisplacement
Optimized loop
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4. Conclusions
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• Future technology/business development trends demand virtual prototyping/virtual qualifications.
• The developed methodologies can generate high added business values.
• Not to replay physical prototyping/qualification, but to reduce their numbers and duration.
• Many challenges remain. Combined effort needed.