Virtual Memory Really this is in OS – but

We need to see how the OS will interact with the HW

Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

Read 4.10

Virtual Memory

• It’s just another level in the cache/memory hierarchy

• Virtual memory is the name of the technique that allows us to view main memory as a cache of a larger memory space (on disk).

cpu

$

cache

memory

disk

cacheing

cacheing

virtual memory

Add latencies

1-4 (L2 – 14)

40-60

150-300

10,000,000-80,000,000

Virtual Memory

• What happens if another program in the processor uses the same addresses that yours does?

• What happens if your program uses addresses that don’t exist in the machine?

• What happens to “holes” in the address space your program uses?

• Can someone else’s program touch your data (or vice versa)?

Virtual Memory

• is just a mapping function from virtual memory addresses to physical memory locations, which allows cacheing of virtual pages in physical memory. Required because main memory is fully associative.

Virtual Page Number

A zero valid bit means…

Virtual Memory mapping

physical addresses

virtual addresses

virtual addresses

disk

Address translation via the page table

virtual page number page offset

valid physical page numberpage table reg

physical page number page offset

virtual address

physical address

pagetable

• all page mappings are in the page table, so hit/miss is determined solely by the valid bit (i.e., no tag)

Virtual Memory

• Suppose you have 8 KB pages, a 64 bit byte address, and 512MB of RAM. How many bits are translated (from your virtual page number to your physical page number)?

Selection Virtual Page # Physical Page #

A 51 16

B 19 16

C 51 29

D 19 29

E None of the above

Address translation via the page table

virtual page number page offset

valid physical page numberpage table reg

physical page number page offset

virtual address

physical address

pagetable

8 KB pages, a 64 bit byte address, and 512MB of RAM

Virtual Memory

• So far – given what we know about VM, what is the fewest number of accesses to main memory possibly from a single MIPS lw instruction?

Write – NO TLBI Page Table lookupI MissD Page Table LookupD Miss

Selection Cache Miss

A 0

B 1

C 2

D 3

E 3+

Making Address Translation Fast

• A cache for address translations: translation lookaside buffer (TLB)

A zero valid bit means…

TLBs and caches

Block

32-bit virtual addresses, 8 KB pages, 2 GB of RAM. Your cache has 64 byte blocks and is 32 KB in size. You are considering 2-way or 4-way. Your boss says 4-way would have a better hit time – is he right?

Selection Right? Reason

A Yes 4-way caches always have better hit times

B Yes This 4-way cache could do more in parallel than a 2-way cache

C No 2-way caches always have better hit times

D No This 2-way cache could do more in parallel than a 4-way cache

E No A different reason from above

TLBs and caches

Block

8KB page, 2 GB RAM, 2-way vs. 4way64 byte blocks, 32KB8KB = 2^1332KB = 2^15

Walkthrough the FIRST memory access

TLB MissTLB exceptionFill TLBPage faultCall OS to replace the page and update page tableFill TLB with now valid entryRequest that physical addressCache missCache missMemory hitFillFill

Walkthrough a COMMON memory access

TLB hit/translateCache hitThese could potentiallyBe in parallel

Virtual Memory – Real Examples

• OS+Presenter+misc > 650MB

• 512MB of RAM

Mention WoW example

Virtual Memory Key Points

• How does virtual memory provide:– protection?

– sharing?

– performance?

– illusion of large main memory?

• Virtual Memory requires twice as many memory accesses, so we cache page table entries in the TLB.

• Three things can go wrong on a memory access: cache miss, TLB miss, page fault.