Virtual Memory

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Virtual Memory

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Outline

• Address translation• Accelerating translation

– with a TLB– Multilevel page tables

• Suggested reading: 10.6

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Address Translation

• V = {0, 1, . . . , N–1} virtual address space• P = {0, 1, . . . , M–1} physical address space• N > M• Address Translation• MAP: V P U {} address mapping

function• MAP(a) = a' if data at virtual address a is

present at physical address a' in P= if data at virtual address a is not present in P (invalid or on disk)(invalid or on disk)

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Address Translation

Processor

HardwareAddr TransMechanism

faulthandler

MainMemory

Secondary memorya

a'

page faultpage fault

physical addressOS performsthis transfer(only if miss)

virtual addresspart of the on-chipmemory mgmt unit (MMU(MMU)

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Address Translation

• Basic Parameters– N = 2n = Virtual address limit– M = 2m = Physical address limit– P = 2p = page size (bytes).

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Address Translation

virtual page number page offset virtual address

physical page number page offset physical address

0p–1

address translation

pm–1

n–1 0p–1p

Notice that the page offset bits don't change as a result of translation

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Address Translation

• Basic Parameters– N = 2n = Virtual address limit– M = 2m = Physical address limit– P = 2p = page size (bytes).

• Components of the virtual address (VA)– VPO: Virtual page offset – VPN: Virtual page number

• Components of the physical address (PA)– PPO: Physical page offset (same as VPO)– PPN: Physical page number

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Address Translation via Page Table

virtual page number (VPN) page offset

virtual address

physical page number (PPN) page offset

physical address

0p–1pm–1

n–1 0p–1p

page table base register(PTBRPTBR)

if validvalid=0then pagenot in memory

validvalid physical page number (PPN)accessaccess

VPN acts astable index

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Simple Memory System Example

• Addressing– 14-bit virtual addresses– 12-bit physical address– Page size = 64 bits (6-bit)

13 12 11 10 9 8 7 6 5 4 3 2 1 0

11 10 9 8 7 6 5 4 3 2 1 0

VPO

PPOPPN

VPN

(Virtual Page Number) (Virtual Page Offset)

(Physical Page Number) (Physical Page Offset)

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Simple Memory System Page Table

• Only show first 16 entries

VPN PPN Valid VPN PPN Valid

00 28 1 08 13 1

01 – 0 09 17 1

02 33 1 0A 09 1

03 02 1 0B – 0

04 – 0 0C – 0

05 16 1 0D 2D 1

06 – 0 0E 11 1

07 – 0 0F 0D 1

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Address Translation Example

Virtual Address: 0x03D4

VPN: VPO: Page Fault? d

PPN: PPO: PA:

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

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00101011110000

PPN: PPO: 0x14 PA:

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

VPN: 0x0f VPO: 0x14 Page Fault? d

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Simple Memory System Page Table

• Only show first 16 entries

VPN PPN Valid VPN PPN Valid

00 28 1 08 13 1

01 – 0 09 17 1

02 33 1 0A 09 1

03 02 1 0B – 0

04 – 0 0C – 0

05 16 1 0D 2D 1

06 – 0 0E 11 1

07 – 0 0F 0D 11

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00101011110000

PPN: 0x0D VPO: 0x14 PA: 0x

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

001010101100

VPN: 0x0f VPO: 0x14 Page Fault? No d

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00101011110000

PPN: 0x0D VPO: 0x14 PA: 0x354

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

001010101100

VPN: 0x0f VPO: 0x14 Page Fault? No d

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Page Hit

VA: virtual addressPTEA: page table entry address PTE: page table entry PA: physical address

MMUCache/MemoryPAPA

DataData

CPU VAVA

CPU Chip PTEAPTEA

PTEPTE1

2

3

4

5

1) Processor sends virtual address to MMU

2-3) MMU fetches PTE from page table in memory

4) MMU sends physical address to cache/memory

5) Cache/memory sends data word to processor

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Page Faults

MMU Cache/Memory

CPUVA

CPU Chip PTEA

PTE1

2

3

4

5

Disk

Page fault handler

Victim page

New page

Exception

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1) Processor sends virtual address to MMU

2-3) MMU fetches PTE from page table in memory

4) Valid bit is zero, so MMU triggers page fault exception

5) Handler identifies victim (and, if dirty, pages it out to disk)

6) Handler pages in new page and updates PTE in memory

7) Handler returns to original process, restarting faulting instruction

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Integrating Caches and VM

CPU Trans-lation

Cache MainMemory

VA PA miss

hit

data

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• Most Caches “Physically Addressed”– Accessed by physical addresses– Allows multiple processes to have blocks in

cache at same time– Allows multiple processes to share pages– Cache doesn’t need to be concerned with

protection issues• Access rights checked as part of address

translation

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• Perform Address Translation Before Cache Lookup– But this could involve a memory access itself

(of the PTE)– Of course, page table entries can also become

cached

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VACPU MMU

PTEA

PTE

PA

Data

MemoryPAPA

miss

PTEAPTEAmiss

PTEA hit

PA hit

Data

PTE

L1cache

CPU Chip


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Speeding up Translation with a TLB

• “Translation Lookaside Buffer” (TLB)– Small hardware cache in MMU– Maps virtual page numbers to physical page

numbers

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MMUCache/Memory

PA

Data

CPU VA

CPU Chip

PTE

1

2

4

5

TLB

VPN 3

TLB Hit

A TLB hit eliminates a memory access

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TLB Miss

MMUCache/MemoryPA

Data

CPU VA

CPU Chip

PTE

1

2

5

6

TLB

VPN

4

PTEA3

A TLB miss incurs an additional memory access (PTE)Fortunately, TLB misses are rare. Why?

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Address Translation

virtual page number page offset virtual address

physical page number page offset physical address

0p–1

address translation

pm–1

n–1 0p–1p

TLB tag TLB index

Cache tag Cache index Cache offset

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Address Translation

• Components of the virtual address (VA)– VPO: Virtual page offset – VPN: Virtual page number – TLBI: TLB index– TLBT: TLB tag

• Components of the physical address (PA)– PPO: Physical page offset (same as VPO)– PPN: Physical page number– CO: Byte offset within cache line– CI: Cache index– CT: Cache tag

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virtual addressvirtual page number page offsetn–1 0p–1p

valid physical page numbertag

valid tag data

data=

cache hit

tag index

=

TLB hit

TLB

Cache

. ..

physical addressphysical page number page offset

TLBI

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• TLB– 16 entries– 4-way associative (2-bit)

13 12 11 10 9 8 7 6 5 4 3 2 1 0

VPOVPN

TLBT

Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid

0 03 – 0 09 0D 1 00 – 0 07 02 1

1 03 2D 1 02 – 0 04 – 0 0A – 0

2 02 – 0 08 – 0 06 – 0 03 – 0

3 07 – 0 03 0D 1 0A 34 1 02 – 0

Simple Memory System TLB


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Virtual Address 0x03D413 12 11 10 9 8 7 6 5 4 3 2 1 0

VPOVPN

00101011110000

VPN: 0x0f TLBI: 0x03 TLBT: 0x03 TLB Hit? Page Fault? O

PPN: PPO: PA:

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

001010101100

TLBI

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• TLB– 16 entries– 4-way associative (2-bit)

13 12 11 10 9 8 7 6 5 4 3 2 1 0

VPOVPN

TLBT

Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid

0 03 – 0 09 0D 1 00 – 0 07 02 1

1 03 2D 1 02 – 0 04 – 0 0A – 0

2 02 – 0 08 – 0 06 – 0 03 – 0

3 07 – 0 03 0D 1 0A 34 1 02 – 0

Simple Memory System TLB


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Virtual Address 0x03D413 12 11 10 9 8 7 6 5 4 3 2 1 0

VPOVPN

00101011110000

VPN: 0x0f TLBI: 0x03 TLBT: 0x03 TLB Hit? Yes Page Fault?

No

PPN: 0x0D PPO: 0x14 PA: 0x354

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

001010101100

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Simple Memory System Cache

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

COCICT

Idx Tag Valid

B0 B1 B2 B3 Idx Tag Valid

B0 B1 B2 B3

0 19 1 99 11 23 11 8 24 1 3A 00 51 89

1 15 0 – – – – 9 2D 0 – – – –

2 1B 1 00 02 04 08 A 2D 1 93 15 DA 3B

3 36 0 – – – – B 0B 0 – – – –

4 32 1 43 6D 8F 09 C 12 0 – – – –

5 0D 1 36 72 F0 1D D 16 1 04 96 34 15

6 31 0 – – – – E 13 1 83 77 1B D3

7 16 1 11 C2 DF 03 F 14 0 – – – –

• Cache– 16 lines– 4-byte line size– Direct mapped

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PA: 0x354

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

COCICT

001010101100

Offset: 0x0 CI: 0x05 CT: 0x0D Hit? Byte: 0x 6

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Simple Memory System Cache

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

COCICT

Idx Tag Valid

B0 B1 B2 B3 Idx Tag Valid

B0 B1 B2 B3

0 19 1 99 11 23 11 8 24 1 3A 00 51 89

1 15 0 – – – – 9 2D 0 – – – –

2 1B 1 00 02 04 08 A 2D 1 93 15 DA 3B

3 36 0 – – – – B 0B 0 – – – –

4 32 1 43 6D 8F 09 C 12 0 – – – –

5 0D 1 36 72 F0 1D D 16 1 04 96 34 15

6 31 0 – – – – E 13 1 83 77 1B D3

7 16 1 11 C2 DF 03 F 14 0 – – – –

• Cache– 16 lines– 4-byte line size– Direct mapped

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PA: 0x354

11 10 9 8 7 6 5 4 3 2 1 0

PPOPPN

COCICT

001010101100

Offset: 0x0 CI: 0x05 CT: 0x0D Hit? Yes Byte: 0x36

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Multi-Level Page Tables

• Given:– X86: 32-bit address space

4KB (212) page size, 4-byte PTE – X86-64: 48-bit address space

4KB (212) page size, 8-byte PTE

• Problem:– X86: Would need a 4 MB page table!

• 220 *4 bytes (20bit = 32bit – 12bit)

– X86-64: Would need a 512 GB page table!• 230 *8 bytes (30bit = 48bit – 12bit)

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• Common solution

– multi-level page tables

– e.g., 2-level page table

• Level 1 tableLevel 1 table: 1024 entries,

each of which points to a

Level 2 page table.

• Level 2 tableLevel 2 table: 1024

entries, each of which

points to a page

Level 1

Table

...

Level 2

Tables

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Level 1page table

...

Level 2page tables VP 0

...

VP 1023

VP 1024

...

VP 2047

Gap

0

PTE 0

...

PTE 1023

PTE 0

...

PTE 1023

1023 nullPTEs

PTE 1023 1023 unallocated

pagesVP 9215

Virtual memory

(1K - 9)null PTEs

PTE 0

PTE 1

PTE 2 (null)

PTE 3 (null)

PTE 4 (null)

PTE 5 (null)

PTE 6 (null)

PTE 7 (null)

PTE 8

2K allocated VM pagesfor code and data

6K unallocated VM pages

1023 unallocated pages

1 allocated VM pagefor the stack32 bit addresses, 4KB pages, 4-byte PTEs

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Summary

• Programmer’s view of virtual memory– Each process has its own private linear address

space– Cannot be corrupted by other processes

• System view of virtual memory– Uses memory efficiently by caching virtual

memory pages• Efficient only because of locality

– Simplifies memory management and programming

– Simplifies protection by providing a convenient interpositioning point to check permissions

Virtual Memory

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