VIRGO 2K 2048 x 2048 SWIR HgCdTe · PDF fileTiming Diagram and Timing ... and operating manual...

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VIRGO-2K 2048 x 2048 SWIR HgCdTe IRFPA

Readout Model #: SB-301 User’s Guide and Operating Manual

CONTENTS

Section Page Chapter 1

Introduction: Design Goals and Features.......................................................................................................1 1.1 Background.......................................................................................................................................1 1.2 Design Features of VIRGO-2K......................................................................................................2

Chapter 2 VIRGO-2K Readout and Motherboard Pad Functions................................................................................3

2.1 Description of I/O Pad Functions....................................................................................................3 2.2 Clocks.................................................................................................................................................3 2.3 Control Lines......................................................................................................................................3 2.4 DC Biases and Returns...................................................................................................................3 2.5 Current Sources................................................................................................................................4 2.6 Outputs...............................................................................................................................................4

Chapter 3 VIRGO-2K Packaging.......................................................................................................................................9

Chapter 4 Timing Diagram and Timing Requirements.................................................................................................11

Chapter 5 Circuit Description and Theory of Operation................................................................................................13

5.1 Unit Cell Source Follower per Detector (SFD) Input Circuit .....................................................13 5.2 Column Circuitry and Output Source Follower...........................................................................15

Chapter 6 Operation...........................................................................................................................................................16

6.1 Integration and Reset Modes........................................................................................................16 6.2 Signal Processing: Correlated Double Sampling and Fowler Sampling...............................17 6.3 General Handling and Storage Procedures...............................................................................18 6.4 Operating Procedures....................................................................................................................18 6.4.1 Removal and Installation of Modules in Dewars......................................................................18 6.4.2 Room Temperature Functional Test..........................................................................................18

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FIGURES

Section Page Figure 2.1 Orientation for Numbering of Pads on SB-301 ROIC...........................................................................................................5 Figure 3.1 VIRGO-2K Pad Names and Locations....................................................................................................................................9 Figure 3.2. Motherboard (MB) used for the 2048 x 2048 VIRGO-2K FPA........................................................................................10 Figure 4.1. Timing Diagram for 16 Output Mode.......................................................................................................................................11 Figure 4.2. Timing Diagram for 4 Output Mode.........................................................................................................................................11 Figure 5.1. Readout and Detector Unit Cells..............................................................................................................................................13 Figure 5.2. Readout Column Circuitry and Output Source Follower....................................................................................................15 Figure 6.1. Fowler-2 Sampling.......................................................................................................................................................................17

TABLES

Section Page Table 1.1. VIRGO 2K Module Design and Performance Characteristics and Interface Specifications.......................................2 Table 2.1 VIRGO-2K Readout Pad and Module Connector Pin Description....................................................................................6 Table 2.2 VIRGO-2K Readout Test Pad Description..............................................................................................................................7 Table 2.3 ESD (Electrostatic Discharge) Protection.................................................................................................................................8

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Chapter 1

Introduction: Design Goals and Features 1.1 Background This manual serves as both a user’s guide and operating manual for the VIRGO-2K 2048 x 2048 SWIR HgCdTe Infrared Modules. The VIRGO-2K module is designed to be butted together to form a larger mosaic Focal Plane Array (FPA). A basic description of the theory and operation of the array circuitry is also presented. The VIRGO-2K Module is a hybrid structure consisting of a Silicon CMOS Readout Integrated Circuit (ROIC) indium bump bonded to a backside-illuminated p-on-n Photo-Voltaic (PV) HgCdTe photodetector. The matching arrays of indium bumps provide electrical interconnection of the detector unit cells to the corresponding readout unit cells. The indium bumps also provide part of the thermal and mechanical interface of the detector to the readout. The readout supports the SWIR HgCdTe detector and cooling of the detector to cryogenic temperatures occurs by thermal conduction across the detector/ROIC interface.

The VIRGO-2K readout consists of 2048 x 2048 unit cells that are read out in blocks of 128 or 512 columns each through 4 or 16 outputs. The number of outputs is electrically selectable through the control line reduceOut. Major features of the ROIC are summarized below. The unit cell size is 20 mm by 20 mm containing only 3 transistors that form a source follower per detector or SFD input circuit. At the bottom of each column in the array are two PMOS current sources that provide bias current to the source followers. Also each column includes switching logic to multiplex the columns into the output drivers.

The output stage for the VIRGO-2K consists of another source follower (SF) circuit. Like the unit cell, the source for the PMOS source follower driver is tied to it’s own well. However, unlike the unit cell SFDs, which are connected to an “active” MOSFET load transistor during readout (the load acts as a current source for the unit cell driver MOSFETs), the output source followers require an externally supplied “passive” load resistor or current source in series with a DC bias supply. Other features of the SB-301 ROIC include the ability to use either a global array reset or a row-by-row reset at the end of the integration time period and to allow the detector inputs to be read out without resetting the integrated charge. This is referred to as a non-destructive read.

Another significant improvement over previous readouts for Astronomy is the greatly simplified clock interface. The VIRGO readout requires only two input clocks for run the multiplexer. CMOS logic circuits in the readout generate all the clocks needed to operate the row and column shift registers and control the reset operations. After receipt of a FrameStart pulse, the row and column shift registers are started to sequentially readout the pixels through the 4 or 16 output drivers.

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1.2 Design Features of VIRGO-2K A summary of the key design features of the VIRGO-2K module is given in Table 1.1 below.

Table 1.1. VIRGO 2K Module Design and Performance Characteristics and Interface Specifications

Parameter Specification Pixel Size (pitch or unit cell size) 20 µm x 20 µm

Array Active Area 40.96 mm x 40.96 mm (15.8 cm2 total active area)

Die Size 43.48 ± 0.025 mm x 43.48 ± 0.025 mm

Array Configuration 2048 x 2048 or 4,194,304 elements

Detector Type SWIR HgCdTe (any p-on-n polarity detector)

Wavelength Range 0.9 µm to 2.5 µm

Effective Unit Cell Optical Fill Factor > 98 % (Aoptical > 3.98 x 10-6 cm2)

Quantum Efficiency > 70 % (1 – 2.4 µm)

Operating Temperature 80 K (nominal)

Dark Current < 1 electron/sec

Readout Type PMOS Source Follower per Detector (SFD) unit cell with “row enable” switch on source side of SFD

Low Glow CMOS multiplexer

Number of Outputs 4 or 16

Clocks 2

Bias/Current Supplies 13 Bias Supplies (all fixed voltages) 2 Current Sources

Maximum Frame Rate 16 Outputs: 1.456 Hz (685.75 msec) 4 Outputs: 0.377 Hz (2.655 sec)

Reset Options Global or Row-by-Row

Well Capacity > 4 x 105 electrons at 1.0 volt reverse bias

Transimpedance ~ 2.0 µV/electron at 1.0 volt reverse bias

Responsivity Uniformity < 10 % (sigma/mean)

Noise (input-referred) 5 to 15 electrons rms (depends on sampling technique and detector bias)

Operability Typically > 99.5 %

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Chapter 2

VIRGO-2K Readout and Motherboard Pad Functions 2.1 Description of I/O Pad Functions The following provides a description of the SB-301 ROIC and Motherboard (MB) Input/Output (I/O) pad functions and the appropriate bias levels associated with each. The iIdle and iSlew pads have a resistor in series with the bias supply.

2.2 Clocks • FrameStart: This clock starts each read frame. It is one master clock cycle wide and straddles the rising

edge of the master clock. The period of this clock is the read frame period.

• pmc: This clock is the master clock. It is a 200 kHz 50% duty cycle clock.

2.3 Control Lines The readout configuration is electrically controlled via three input control lines. The readout latches the state of these three signals on the next rising edge of the master clock after the frame start is received.

• reduceOut: This control line reduces the number of outputs the array uses. When reduceOut is low (0 V), 16 outputs are used (this is the default condition if the pad is floated). When reduceOut is high (4 V), 4 outputs are used.

• ucRstSel: This control line selects either global or row reset. When ucRstSel is low (0 V), Row-by-Row reset is used (this is the default condition if the pad is floated). When ucRstSel is high (4 V), Global reset is used.

• ucRstEn: This control line enables the unit cell reset for a frame. When ucRstEn is low (0 V), no reset is done in the current frame – non-destructive read. When ucRstEn is high (4 V), the unit cell inputs are reset after they are read. This pad must be driven – there is no pull-down or pull-up on this input.

2.4 DC Biases and Returns • vsub: This bias serves as analog ground reference for the SB-301 ROIC. The nominal bias is 0.0 V

(ground).

• vpUc: This bias is the analog supply lead for the column based current sources. The nominal voltage for vpUc is +3.5V.

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• vnUc: This bias is the unit cell analog return. The unit cell source follower drains are all connected to this bias. The nominal voltage for vnUc is +1.0V.

• vnOut: This bias is the output source follower analog return. The output source follower drains are all connected to this bias. The nominal voltage for vnOut is +2.5V (at room temperature, this bias should be reduced to +2.0V).

• vdetCom: This bias is detector common reference voltage. The nominal voltage is +1.0V. The detector bias is the difference of vrstUc and vdetcom. This bias should be held at the same voltage as vnUc. Adjustments to the detector bias should be done using vrstUc.

• vrstUc: This bias is the unit cell reset voltage. The nominal voltage is 0.0 V (which produces a -1.0 V detector bias when vdetCom is biased at 1.0V). Use this bias to adjust the detector reverse bias.

• vpD: This bias is the digital supply lead for the chip. The nominal voltage level is +4.0V.

• vnD: This bias is the digital return lead for the chip. The nominal voltage level is 0.0V.

• vCas: This bias is the digital cascode voltage for the chip. The nominal voltage level is +3.0V.

• vhiReset: This bias is the positive rail voltage for the on-chip generated unit cell reset clocks. The nominal voltage level is +4.0V.

• vloReset: This bias is the negative rail voltage for the on-chip generated unit cell reset clocks. The nominal voltage level is 0.0V. The chip can be held in reset continuously if this bias is set at +4.0V. For normal operation, it should be biased at the nominal 0.0V.

• vhiRowEn: This bias is the positive rail voltage for the on-chip generated unit cell row enable. The nominal voltage level is +5.0V. This supply is also the upper rail of the input static protection network. THIS VOLTAGE MUST BE THE MOST POSITIVE VOLTAGE IN THE CHIP.

• vloRowEn: This bias is the negative rail voltage for the on-chip generated unit cell row enable. The nominal voltage level is +1.0V. This bias may be set anywhere between 0.0 and +1.0 V.

2.5 Current Sources • iIdle: This bias provides the current reference for the iIdle current mirror on each of the 2,048 column bus

lines. The nominal input current should be 20 µA. The bias circuit divides the iIdle current by 200 to produce 100nA of trickle current for each column. A 200 kΩ series resistor is located on the module. An applied voltage of approximately –2.21 V will produce the required 20 µA current. Adjust this voltage to achieve the desired 20 µA current level.

• iSlew: This bias provides the current reference for the iSlew current mirror on each of the 2,048 column bus lines. The nominal input current should be 100 µA. The bias circuit divides the iIdle current by 10 to produce 10 µA of slew current for each column as it is addressed. A 50 kΩ series resistor is located on the module. An applied voltage of approximately –3.12 V will produce the required 20 µA current. Adjust this voltage to achieve the desired 100 µA current level.

2.6 Outputs • vout1 – vout16: The 16 video outputs are connected to the 16 PMOS output driver source followers (SF).

To function properly, each output requires a 200 µA current source load to drive an output load capacitance of about 100-150 pF. The source follower current should be adjusted as necessary to provide

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sufficient settling of the output waveform for the actual load. The output voltage range is from +3.0 V (minimum) to +4.6 V (maximum). The voltage swing from starvation to saturation will be approximately the difference between the vrstUc and vdetCom bias voltages. While the current source may be approximated by a 32.5 KΩ resistor to a voltage of approximately +10V, better linearity will be seen if a true current source is used. In four output mode, outputs 1, 5, 9, and 13 are active. The inputs of the other 12 outputs are tied to vnOut. These 12 outputs can safely be floated in 4 output mode to reduce power.

1 84

Figure 2.1 Orientation for Numbering of Pads on SB-301 ROIC. 84 pads are located along the bottom of the chip. Pad one is located in the lower left corner and pad 84 is located in the lower right corner. As is shown in table 2.1, many of the pads are repeated multiple times. While not shown in this figure, process control monitors (PCM) are located along the right edge of the chip.

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Table 2.1 VIRGO-2K Readout Pad and Module Connector Pin Description

MDM # /Con #

ROIC Pad #

Name (ROIC) Function Nominal

Level Pad Type

NC 26, 28, 29, 46, 48, 49, 66, 68, 69

NC Can be used as wire bond practice pads NC Control

1 4, 24, 44, 64 vhiReset Upper Rail for unit cell reset clock drivers 4.0 Bias

2 3, 23, 43, 63 vpD Digital Supply Voltage 4.0 Bias

3 NC Cable Shield 0.0

4 9 ucRstEn Control line for unit cell reset enable 0.0 or 4.0 Control

5 8 ucRstSel Control line for reset mode 0.0 or 4.0 Control w/Pulldown

6 6 reduceOut Control line for # of Outputs 0.0 or 4.0 Control w/Pulldown

7 NC Cable Shield 0.0

8 2 FrameStart Frame Start 0.0 / 4.0 Clock

9 1 pmc Master Clock 0.0 / 4.0 Clock

10 NC Cable Spare

11 NC Cable Spare

12 NC TS4+ Temp Sensor +

13 NC TS3+ Temp Sensor +

14 NC TS2- Temp Sensor -

15 NC TS1- Temp Sensor -

16 NC Cable Shield 0.0 V

17 84 iIdle Column Idle current source input 20 µA (~ -2.21V) Bias

18 83 iSlew Column Slew current source input 100 µA (~ -3.12V) Bias

19 7, 27, 47, 67 vCas Cascode supply for digital gates 3.0 Bias

20 12, 32, 52, 72 vnD Digital Return Voltage 0.0 Bias

21 14, 34, 54, 74 vhiRowEn Upper Rail for unit cell reset clock drivers; also upper rail for pad protection network 5.0 Bias

23 18, 38, 58, 78 vrstUc Detector/unit cell reset voltage 0.0 Bias

24 22, 42, 62, 82 vpUc Unit cell source follower current source voltage 3.5 Bias

27 5 vout1 Analog output for columns 1-128 (1-512 in 4 output mode) 3.0 to 4.6 Output

28 15 vout3 Analog output for columns 257-384 (unused in 4 output mode) 3.0 to 4.6 Output

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MDM # /Con #

ROIC Pad #

Name (ROIC) Function Nominal

Level Pad Type








36 11, 31, 51, 71 vloReset Lower Rail for unit cell reset clock drivers 0.0 Bias

37 13, 33, 53, 73 vloRowEn Lower Rail for unit cell row enable drivers 1.0 Bias

38 16, 36, 56, 76 vnOut Output source follower drain voltage 2.5 Bias

39 17, 37, 57, 77 vnUc Unit cell source follower drain voltage 1.0 Bias

40 19, 39, 59, 79 vdetCom Detector common (n-type base layer) 1.0 Bias










41, 42 21, 41, 61, 81 vsub Readout substrate voltage 0.0 Bias

Table 2.2 VIRGO-2K Readout Test Pad Description

ROIC Pad # Name (ROIC) Function Nominal Level

Pad Type

T1 addrBIT<3> Digital BIT address MSB 0.0 or 4.0 Input

T2 addrBIT<2> Digital BIT address bit 2 0.0 or 4.0 Input

T3 addrBIT<1> Digital BIT address bit 1 0.0 or 4.0 Input

T4 addrBIT<0> Digital BIT address LSB 0.0 or 4.0 Input

T5 oDBIT Digital BIT output 0.0 to 4.0 Output

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T6 sfDrain Test output source follower drain voltage 2.5 V Bias

T7 sfGate Test output source follower gate voltage 1.0 to 3.0 Bias

T8 sfSource Test output source follower source and body voltage 3.0 to 4.6 Bias

Table 2.3 ESD (Electrostatic Discharge) Protection

Pad Type Diode to Vsub

Diode to vhiRowEn

1KΩ Series Resistor

Clock √ √ √

Input √ √ √

Control √ √ √

Bias √ √

Output √ √

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Chapter 3

VIRGO-2K Packaging The VIRGO-2K SB-301 readout has a total of 84 flight I/O bond pads located along the bottom of the chip. Thirty-six of the 84 pads are unique and must be bonded for the chip to operate – 16 outputs, 2 clocks, 2 current sources, 3 control lines, and 13 bias lines. Thirty-nine additional signals are redundant and should be connected if possible but are not required. The remaining nine of the 84 flight pads are not used. The Motherboard (MB) has one 51 pin MDM style connector at the end of a cryo flex cable, which support the ROIC and the on-MB temperature sensor. Along the lower left edge of the chip are the 5 digital BIT test pads (4 address pads and o1 output). Along the lower right edge of the chip are three pads for a test output source follower (source/well, gate, and drain connections). Finally, the 240 pads (12 groups of 20 pads) along the right side are for process control monitor structures. The test pads along the right and left sides are unneeded to operate the readout and can be safely floated.

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addrBIT3addrBIT2addrBIT1addrBIT0

oDBIT

Figure 3.1 VIRGO-2K Pad Names and Locations

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Figure 3.2. Motherboard (MB) used for the 2048 x 2048 VIRGO-2K FPA. The HgCdTe detector active or photon-absorbing region is about 0.021” (TBR) above the top surface of the MB. The thickness of the MB between the back of the ROIC and the bottom of the MB is 0.200” ± 0.010” (TBR). Therefore the total height of the detector active region from the bottom of the MB is about 0.221” ± 0.010” (5.613 mm – TBR). If four side butting is desired, a much more compact MB can be made which allows the cable and connector to exit from the back surface of the pedestal. More information about four side butting can be obtained by contacting RVS.

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The externally supplied clocks are (Figures 4.1 and 4.2):

• FrameStart – Readout frame rate clock to start the read operation

• pmc – Master Clock from which all internal clocks are derived. The nominal frequency of this clock is 200 kHz and it’s duty cycle should be as close to 50% as possible. Pixel data is clocked out on each edge of the master clock.

To readout the full array, at least 2050 Rows must be readout. The first row output is a reference row where all pixels are held at reset. The second row contains image data from row 1 (Figure 5.1 and 5.2). Each row is 134 pixel periods (67 pmc periods) long in 16 output mode and 518 pixel periods (259 pmc periods) long in 4 output mode. In global reset mode, at least 100 µsec (TBR) must be added to the frame time required to read the pixel data to allow a complete reset of the array. More details about global reset are provided in Section 5.

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Chapter 5

Circuit Description and Theory of Operation 5.1 Unit Cell Source Follower per Detector (SFD) Input Circuit The unit cell of the VIRGO readout contains only three transistors (Figure 5.1). The heart of the unit cell Source Follower per Detector (SFD) input circuit consists of a single PMOS driver transistor that operates as a unity gain source follower. The SFD is ideally suited to very small unit cells and offers low noise with near-unity gain. The other two transistors in the unit cell function as switches that are controlled by on-chip clocks. Transistor M2 allows the input node to the detector to be reset to a large negative bias at the beginning of a new frame. The gate of M2 is connected to the prstUc (reset) clock, which is internally generated on-chip. Transistor M1, whose gate is controlled by the prowEn (row enable) clock, allows the source followers in all unit cells within the same row to turn on by connecting the source of the PMOS driver transistor in each unit cell to an active MOSFET load transistor at the bottom of each column that acts as a current source. The load current must be large enough to drive, or slew, the capacitance Cmux of the common output bus. Because the load MOSFET for the SFD is outside the unit cell, there is no power dissipation in the unit cell until it is “enabled” by the row MUX.

Unit Cell Output

vrstUc0 V

vnUc

prowEn

prstUc

Detector

Readout Unit Cell

vdetCom1 V

vinUc

0 Volts

1 Volts

1.2 Volts

2.2 Volts

1 V

M1

M2

Mdriver

Unit Cell Output

vrstUc0 V

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prstUc

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vdetCom1 V

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1 V

Unit Cell Output

vrstUc0 V

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Readout Unit Cell

vdetCom1 V

vinUc

0 Volts

1 Volts

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M1

M2

Mdriver

Figure 5.1. Readout and Detector Unit Cells. The initial detector bias is determined by the difference between vrstUc and vdetCom. The unit cell source follower driver transistors are off until the row enable switch turns on to select the row.

All unit cell source followers are off except for those in the row being currently addressed by the row shift register. During most of the signal integration period, all source followers are turned off. Photon-generated carriers produced by the detector, as well as any “dark” or “leakage” carriers thermally generated within the detector, cause

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the voltage on the input node to the source follower (the gate) to ramp from the nearly 0V reset voltage up toward forward bias. The input dynamic range is proportional to the voltage difference between the reset level and the detector zero bias point: larger dynamic range can be achieved by resetting the detectors further into reverse bias, but a practical limit is reached either when the detectors become too “leaky” (higher count rate of “dark” carriers) or when the detectors begin to break down. After the completion of the integration period, the source followers are turned on one row at a time. When row N is selected by the row shift register, all 2048 unit cells in row N are provided with a relatively low current Iidle that turns on the source follower driver transistors in each unit cell. Islew for the each unit cell is turned on one pixel period before it is multiplexed onto the output data lines. The source of each source follower then slews to a voltage level approximately one PMOS threshold voltage higher than the voltage attained on the gate at the end of integration (hence the term “source follower).

The small signal gain of the unit cell SFD is given by

A 1

1+ gg

volts rmssf1ds

m

(1)

where gm is the transconductance of the SFD driver MOSFET and gds is the drain-to-source transconductance of the active load MOSFET in amps/volt or mhos. The source-to-drain resistance of the load MOSFET is rds = 1/gds. For gm/gds » 1, the SFD gain becomes unity. The VIRGO source follower driver transistor is located in an isolated n-well that is tied to the source voltage. This eliminates the so-called body effect by holding the body-source voltage at zero bias.

Three different mechanisms generate noise in the SFD input circuit: 1) kTC noise which occurs during reset of the input node, 2) driver MOSFET 1/f noise, and 3) driver MOSFET channel thermal noise. The kTC or reset noise is given by

V k TC

volts rmsnoisein

(2)

Driver MOSFET 1/f noise is given by

Hzvolts

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(3)

where Kf is the process-dependent prefactor [volt2-F], Cox is the gate capacitance per unit area [F/cm2], and W and L are the gate width and length [cm].

Driver MOSFET channel thermal white noise is given by

i 8 k T g3

ampHz

noisem

(4)

where gm is the transconductance of the MOSFET in amps/volt or mhos. The input-referred noise voltage (input-referred to the MOSFET gate) is found by dividing inoise by gm

v 8 k T3 g

voltsHz

noisem

(5)

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5.2 Column Circuitry and Output Source Follower Figure 5.2 shows the SB-301 column circuitry and output source followers. The pslew/pslewN, pcolOn/pcolOnN clocks are generated internally by the readout fast shift register. The gate biases Vslew and Vidle on the active load MOSFETS for the unit cell SFD’s are also generated on-chip from the column current mirror circuits. The clamp circuit (one per column), controlled by pOverscan, acts like a 2,049th row and is automatically turned on when no other rows are enabled. The clamp is used to clamp the column output between frames so that the column buslines do not get “pulled up” to vpUc shutting down the column current sources. As mentioned earlier, Iidle current is always on. When a row is addressed all the source followers in the row are connected to its own Iidle current source. One pixel period prior to multiplexing a column to an output buffer, the column’s pslew/pslewN clocks activate its slew current. This allows the larger vertical busline capacitance to be precharged for one pixel period. The pcolOn/pcolOnN clock is enabled one pixel period later to allow the unit cell to drive all the way to the output source follower input gate. Islew is therefore active during two fast shift register cycles (column m and (m+1)). Since there are 16 outputs, 32 columns are sourcing the Islew current at a time.

SF Output

Mslew

pslew /pslewN

3.4 V

4.4 V

vrstUc vnUc

Midle

pcolOn/pcolOnN

vslew vIdle IslewRef 100 mA

Islew 10 mA

IidleRef 20 µ A Iidle

~ 100 nA

Iout 200

vpUc

Mclamp

Mout MSFout

vpOut

vnOut

Column Bus

pOverscan

SF Output

Mslew

pslew /pslewN

3.4 V

4.4 V

vrstUc vnUc

Midle

pcolOn/pcolOnN

vslew vIdle IslewRef 100 µA

Islew 10 µA

IidleRef 20 µ A Iidle

~ 100 nA

Iout 200 µA

vpUc

Mclamp

Mout MSFout

vpOut

vnOut

Column Bus

pOvers can Figure 5.2. Readout Column Circuitry and Output Source Follower. The pslew/pslewN,

pcolOn/pcolOnN and pOverscan clocks are generated internally by the readout row and column shift registers. The gate biases Vslew and Vidle on the active load MOSFETS for the unit cell SFD’s are also generated on-chip from the column current mirror circuits.

The Islew and Iidle currents are related to the applied Vref bias by

Iidle or Islew = (Vref – (vpUc + VGS))/Rseries

where Rseries is the external series resistance on the motherboard, Vref is the applied bias (negative), and VT is the current mirror PMOS threshold voltage. For Rseries = 200 kΩ, VGS = -1.7V (approx.), vpUc = +3.5V, and Vidle= -2.21 volts, a current of 20 µA is produced for Iidle. The Islew current should be 100 µA, which requires VslewRef to be about -3.12V (with Rseries = 50 kΩ and VGS = -1.62 V)

The output source follower driver FET requires an externally supplied load resistor or current source. A true current source load will provide better linearity than a simple resistor load. In 16-output mode, all of the outputs are active. In four-output mode, only outputs 1, 5, 9, and 13 are active. The other 12 outputs may be safely floated.

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Chapter 6

Operation 6.1 Integration and Reset Modes Two modes of operation are available for the VIRGO-2K. Both modes are “integrate–while–read”, in which pixel readout occurs during the signal integration process. Unlike a “snapshot” mode of operation, integration cannot be “stopped” in the “integrate–while–read” mode. Snapshot mode requires a sample/hold circuit in the unit cell, which can temporarily store the output from one frame and read the data out while signal from the next frame is being integrated. The first mode is a read-while-integrate mode in which the entire array is reset simultaneously and all pixels begin integration of photo-generated carriers simultaneously. Consequently, this mode is referred to as the “global” reset mode. Global reset is desirable when operating under low background flux levels with long integration times. Although all pixels begin integrating simultaneously, all pixels are not sampled or read out simultaneously. If a single signal “read” of each pixel was acquired, the last pixel to be read out would have a slightly longer integration time than the first pixel read out. The difference in integration times between the first and last pixels would be equal to the time it takes to read out the entire array, which is about 0.7 sec (for 16 output mode).

To operate in “global” reset mode, the ucRstSel control line is held high at the beginning of a frame. The readout latches the state of this control line once per frame. The latch occurs on the next master clock rising edge after the FrameStart is received. Since the array is typically read many times during a single integration time, the ucRstEn control line is used to identify when the frame in which the reset occurs. ucRstEn is also latched into the readout once per frame. Global reset is asserted at the end of the frame in which ucRstEn is asserted. The chip is held in global reset until the next FrameStart is received.

Sampling techniques in this mode include Correlated Double Sampling (CDS), in which two samples are acquired, a “pedestal” sample shortly after the start of the integration time period (just after first reset) and a “signal” sample shortly before the end of the integration time period (just prior to the next reset). Variations on standard CDS methods, including Fowler sampling, are also possible. With CDS or Fowler sampling, the actual integration time is the difference in time between the signal and pedestal samples. Since CDS and Fowler sampling require two or more samples or “reads” during pixel integration which are differenced, all pixels have the same integration time period even though all pixels are not sampled simultaneously. However, at high background flux levels, it is possible that the last pixels to be sampled near the end of a frame become saturated. To avoid this possibility, the integration time period must be kept short enough so that no pixels reach saturation.

The second mode of operation is a “rolling” integration mode or row-by-row reset. In this mode, after a row has been read, it is reset prior to advancing the next row. The “rolling” integration mode, since rows are reset individually, can be also referred to as “row” reset mode. Row reset is more suitable for high background flux levels and relatively short integration times. In this mode, all pixels do not integrate simultaneously, but since the integration time is determined by the time interval between successive samples, all pixels have the same integration time period. To operate in “row” reset mode, the ucRstSel control line is set to 0.0 volts at the beginning of the

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frame. In addition, the ucRstEn control line must also be set to +4.0 volts at the beginning of the frame. Sampling techniques available in this mode include 1) Acquiring a separate frame for the reset level, which is one type of Fowler sampling, and 2) single-sampling (non-CDS) by acquiring only a single sample immediately prior to resetting each row.

6.2 Signal Processing: Correlated Double Sampling and Fowler Sampling Correlated Double Sampling (CDS) and Fowler sampling can be used to reduce low frequency noise due to drift or 1/f noise at the expense of adding more noise at higher frequencies. CDS requires sampling twice as often as single-sample data, once at the beginning of the integration period, before significant photo-charge has been integrated, and again near the end of the integration period. One sample is therefore acquired immediately after reset and the second sample is acquired immediately before the next reset. Since any low frequency temporal noise or “DC” drift that varies slowly over time scales comparable to the difference in time between the two samples is “correlated” (unchanged), subtracting the first sample from the second sample removes the low frequency noise. However, high frequency noise (white noise, for example) is not correlated over time from the acquisition of the first sample to the acquisition of the second sample. Since sampling twice as often amounts to two independent samples of the high frequency noise, CDS leads to a Ö2 increase in high frequency noise. The increased high frequency noise when using CDS can be reduced by band-limiting the signal.

Fowler sampling is an extension of CDS in which multiple pairs of samples are acquired. One sample of each pair occurs near the beginning of the integration period and the other sample occurs near the end of the integration period. Each pair of samples is subtracted as in CDS. Figure 6.1 shows an example of “Fowler 2” sampling.

pedestal_1pedestal_2

signal_1signal_2

Time

Vsf_out

Tint

Fowler 2 Sampling

Figure 6.1. Fowler-2 Sampling. Two “pedestal” samples are acquired soon after reset, before significant photo-charge has been integrated. Before the next reset, two additional “signal” samples are acquired. The two signal samples are averaged, the two pedestal samples are averaged, and the average pedestal level is subtracted from the average signal level. The integration time Tint is the difference in time between the first (second) pedestal sample and the first (second) signal sample.

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6.3 General Handling and Storage Procedures Note: VIRGO-2K ModuleS ARE STATIC SENSITIVE. STATIC PROTECTION MUST BE USED DURING HANDLING. WEAR A GROUNDED WRIST STRAP AND A STATIC-SAFE SMOCK.

Because VIRGO-2K Modules are static sensitive, static-safe procedures must be used during handling and storage. While handling, a grounded wrist strap and a static-safe should be used to prevent build up of static charge. During temporary storage in a laboratory environment, the Module should be placed inside a “recloseable” static shielding bag such as the 3M 2110R bag. For long-term storage, one of the following methods should be used, in order of most preferable to least preferable:

1. Store Modules under vacuum. This method is preferred because it keeps all water vapor and particles off the device.

2. Store Modules in a hermetically sealed “dry” box that is continuously purged with a dry inert gas such as dry N2. This method is almost as good as storage under vacuum but allows easier access to the parts in storage.

3. Storage in a static-safe hermetic package with a desiccant to remove water vapor.

6.4 Operating Procedures 6.4.1 Removal and Installation of Modules in Dewars

1. Module Inspection: Using proper static-safe handling, inspect the Module under a microscope. Confirm that the wirebonds are not crushed, broken, or missing.

2. Module Installation: Place the Module, which should be mounted into the test adapter, onto the dewar cold plate. Insure that the Module assembly has the correct orientation on the cold plate. Connect the 51-pin connector to a mating connector on the dewar daughtercard. Mount the dewar cold shield but do not bolt it in yet. Before it is bolted in a Room Temperature Functional Test should be conducted.

6.4.2 Room Temperature Functional Test 1. Software Setup: Load and configure the software used to operate the Module (correct biases and

clocks). Load the timing file and zero all bias supplies.

2. Hardware Setup: Ensure that the operator is wearing a wrist strap and a static-safe smock. Remove the shorting plugs on the dewar feedthrough connectors. These should be used at all times other than during normal operation to prevent electrostatic damage to the Module. Connect the Bias and Clock supply cables to the appropriate dewar feedthrough connectors. .

3. Current/Voltage Readbacks: “Read Back” the bias and clock voltage and current levels and verify that all levels are within the expected range. If desired, calculate the power dissipation of the Module from the set bias levels and the measured currents (do not include the clocks in the power dissipation calculation). The power consumption of the Module should be 6-8 mW in 4 output mode and about 10-12 mW in 16 output mode. If it is much higher or lower than this, there is likely a problem. The current on vpUc should be negative and should be several hundred microamps. The current on vnUc should be positive and should be about the same size as the current on vpUc. The current on vnOut should be positive. Observe the outputs on an

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oscilloscope to verify that all outputs are working properly. Signal outputs should be at a positive voltage, typically 3.2 to 4.2 Volts.

4. Room Temperature Test Termination: Zero all bias supplies to the Module: If the readbacks or the outputs on the oscilloscope indicate a problem, contact one of the people listed in the Appendix. If these people are not easily accessible, document your observations and record the readback voltages and currents. If correct operation is observed, replace the shorting plugs on the dewar feedthrough connectors and proceed with pumping down the dewar.

VIRGO 2K 2048 x 2048 SWIR HgCdTe · PDF fileTiming Diagram and Timing ... and operating manual...

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