Vipul Patel

ASIC/FPGA Verification Engineer

eInfochips Pvt. Ltd. Ahmedabad Email:

ec.vipul@hotmail.com

Contact: 9099892780, 8690863887

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PROFILE

Professional Experience

• 3+ years of experience in ASIC/FPGA SoC and Block level IP verification using System Verilog and

VHDL, architecting a complex verification environment in OVM/UVM and creating verification

plan.

• Experience of leading whole project of complex DAL level-A FPGA devices used in commercial

avionics products.

• Experience of planning the project activities, milestones and achieving that through continuous

tracking.

• Experience on working with different stages of verifications like functional and gate level

verification.

• Experience of achieving 100% code and functional coverage. Good hands on writing functional

coverage.

• Familiar with DO-254 Hardware Design Life Cycle and AS9100C standard for AEH (Airborne

Electronics Hardware) devices.

• Good knowledge of ARINC 429 (Aeronautical Radio INC 429), ONFI Nand Flash Protocol (ONFI

3.1), AXI-4 (Advance Extensible Bus Interface - 4), APB (Advance Peripheral Bus), AHB (Advance

High Performance Bus), RS-232, I2C (Inter Integrated Circuit), SPI (Serial Peripheral Interface),

EMIF (External Memory Interface (DSP Interface)), McBSP (Multichannel Buffered Serial

Protocol), NOR Flash Interface, LTC2217 and LTC2194 ADC interface and ability to quickly learn

any protocols.

• Experience in developing constraint random, coverage driven, and assertion based verification

environment using System Verilog, OVM and UVM from scratch.

• Possesses strong test case debugging skill, hands on experience and knowledge of Questasim

and VCS stimulators and ability to quickly learn other tools.

• Familiar with Perl scripting, makefile utility of Linux.

• Possesses outstanding communication and problem solving skill.

Avionics Device Verification Background:

• DO-254 Expertise:

• Creating the DO-254 compliance formal (RTL + Gate Level) verification phase documents:

• Verification Case Document (VCD), Verification Procedure Document (VPD), Verification Results Document (VRD).

• Hardware Design Life Cycle Processes.

• Verification and Validation Processes.

• Configuration Management and Process Assurance activities.

• Played the active role in verification for Avionics based project executed with client (US-

client).

• Played the active role in peer reviews of Hardware Requirement Document (HRD), VCD, VPD and VRD.

Projects:

1. ONFI Nand Flash Memory Model VIP (eInfochips)

• Team Size: 4

• Duration: 6 Months (April’2012 to September’2012)

• Identified checkers & test scenarios to verify Nand Flash VIP Memory model.

• Created operational flow diagram (FSM) for memory model.

• Involved in architecture development for Nand Flash VIP using SVT technology (Synopsys Technology).

2. UVM Skeleton Generator Tool (eInfochips)

• Team Size: 2 • Duration: 6 Months (October’2012 to March’2013)

• Developed the verification test bench environment components in UVM methodology.

• Created the Perl script to create verification environment directory structure.

• Developed the simulation script to run test case and regression using makefile.

• Performed the basic level test cases simulation with developed environment.

• Implemented the error catcher and transaction recording utilities provided in UVM.

3. XLA (Translator) FPGA Verification. (AEH Device with Design Assurance Level - A)

• Team Size : 3

• Duration: 5 Months (April’2013 to August’2013)

• Involved in planning and development of verification test bench environment.

• Developed the timing checkers, System Verilog assertions and functional cover groups.

• Performed simulation, debugging of test case, analysis of code coverage.

• Prepared the VCD/VPD/VRD documents and created the traceability to requirements to

satisfy DO-254 objectives.

• Developed the verification test bench environment OVM components:

• ADC OVC agent: To provide the digital data on the input interface to DUT.

• Encoder OVC agent: To provide the encoder inputs to DUT.

• RS-232 OVC agent: To capture the transmitted data on the output interface of DUT.

• Developed the functional coverage validation script in Perl to validate functional coverage

collected by Questasim.

• Performed the RTL and gate-level simulation of DUT.

4. ARINC 429 Transmitter IP Verification. (AEH Device with DAL-A)

• Team Size: 1

• Duration: 8 Months (September’2013 to April’2014).

• Performed the formal verification of reusable ARINC 429 Transmitter IP. This IP is used in the

next generation 737-Max Display System FPGA (737-MDS FPGA).

• Created the AS9100 standard objective compliance documents and actively involved in

AS9100 audit for this project at eInfochips.

• Involved in planning and development of verification test bench environment.

• Developed the timing checkers, System Verilog assertions and functional cover groups.

• Performed simulation, debugging of test case, and analysis of DUT code coverage.

• Prepared the VCD/VPD/VRD documents and created the traceability to requirements to

satisfy DO-254 objectives.

• Developed the verification test bench environment components:

• AXI4 OVC agent: To provide the transactions (Configuration and ARINC data) on input

AXI4 interface of IP.

• ARINC 429 interface OVC monitor: To sample the ARINC 429 interface and capture the

transmitted data.

• Scoreboard model: To check end to end data integrity for input data and transmitted

data.

• Developed the Assertion snapshot Perl script to generate System Verilog Assertion

waveform snapshots, Assertion.wlf for verification results artifact.

5. Data Forwarding Function (DFF) IP Verification. (AEH Device with DAL-A)

• Team Size: 1

• Duration: 4 Months (May’2014 to August’2014)

• Performed the formal verification of the reusable DFF IP, used in 737-Max Display System

FPGA.

• Involved in planning and development of verification test bench environment.

• Developed the timing checkers, System Verilog assertions and functional cover groups.

• Performed simulation, debugging of test case, and analysis of DUT code coverage.

• Prepared the VCD/VPD/VRD documents and created the traceability to requirements to

satisfy DO-254 objectives.

• Developed the verification test bench environment components:

• AXI4 slave OVC agent: To provide the data for read transaction on the AXI4 master

interface of IP. It also used to store the data for write transaction send on the AXI4

master interface of IP.

• Scoreboard model: To check end-to-end data integrity for input data and transmitted

data.

6. MAMBA SoC FPGA Verification. (AEH Device with DAL-A)

• Team Size: 5

• Duration: 3 Months (September’2014 to November’2014)

• Performed the formal verification of MAMBA FPGA, used in 737-Max Display System FPGA.

• Developed the verification test bench environment OVM components:

• I2C master OVC agent: To provide the read and write transaction on I2C interface for

processor.

• SPI OVC agent: To provide the data for read operation performed by device on SPI

interface.

• Discrete OVC agent: To provide stimulus on discrete interface. Sample and capture the

transaction by monitoring interface activity.

• Developed the OVC agent components with transaction recording utilities provided in OVM

for easier and fast debugging.

7. GLU-2100 Atlas FPGA Verification (AEH device with DAL-A) (Current Project)

• Team Size: 1

• Duration: December’2014 to till date.

• Performing the formal verification of Atlas FPGA used in MMR (multi-mode receiver) in GLU-

2100 and CNG systems.

• Knowledge of Digital Down Converter – NCO, CIC filter, FIR filter.

• Developing the verification test bench in VHDL using client and server model.

• Developed below BFMs in VHDL.

• Developed LTC 2217(Linear Technology) and LTC2194 ADC converter BFM.

• Developed ARINC 429 Model BFM (ARINC Transmitter and ARINC Receiver).

• Developed NOR Flash Interface BFM.

• Developed the DSP server Model with EMIF interface and McBSP interface.

Languages and Tools:

• HDL Languages: Verilog and VHDL.

• Verification Methodologies: OVM, UVM, Client-Server Methodology in VHDL.

• HVL Languages: System Verilog.

• Tools: Questasim, VCS, NC-SIM, SVN, CVS, PREP, DOORs, ALM, JAMA.

• Scripting Language: Perl.

Trainings:

• DO-254/RTCA Design Assurance Guidance for Airborne Electronic Hardware at eInfochips Ltd,

Ahmedabad.

• ASIC Verification Training from eInfochips Training and Research Academy (eITRA), Ahmedabad.

Achievements:

• Submitted the article “Verification using Assertion and creating the automation script to capture

assertion results for DO-254” for next publication on Verification academy by Mentor Graphics.

• Published the article “FUNCTIONAL COVERAGE DEVELOPMENT TIPS: DO’s and DON’Ts” on

Verification academy by Mentor Graphics.

• Awarded by “Core Value-Embrace Impossible Challenges” from eInfochips.

• Awarded by “Pat on the Back” for “Resolving the technical issues of 737-Max Display System”.

• Awarded by “Pat on the Back” for “Issue free guidance & execution to other team member in

avionics client projects”.

EDUCATIONAL QUALIFICATION: B.E. Electronics and Communication (Year-2010), Vishwakarma Govt. Eng. College, Chandkheda, Gujarat.

Personal Information:

Name : Vipul Govindbhai Patel.

Date of Birth : 3rd September, 1988

Hobbies : Listening Music, Playing cricket.