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HDL lab manual 2013 BEARYS INSTITUTE OF TECHNOLOGY MANGALORE DEPARTMENT OF ELECTRONICS AND COMMUNICATION HARDWARE DESCRIPTION LANGUAGE (HDL) LAB MANUAL SUB CODE: 10ECL48 2013 DEPT of ECE Page 1
Transcript of electrobotss.files.wordpress.com · Web viewBEARYS INSTITUTE OF TECHNOLOGY. MANGALORE. DEPARTMENT...
HDL lab manual 2013
BEARYS INSTITUTE OF TECHNOLOGY
MANGALORE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
HARDWARE DESCRIPTION LANGUAGE (HDL)
LAB MANUAL
SUB CODE: 10ECL48
2013
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HDL lab manual 2013
INDEX
PART A
(Simulation and Interfacing)
Sl.No Name of the experiment
1 HDL code for all the gates
2 HDL codes for the combinational design
a. 2 to 4 decoder
b.(i) 8 to 3 encoder without priority
b.(ii) 8 to 3 encoder with priority
c. 8 to 1 multiplexer
d. (i) 4 bit binary to gray converter
d.(ii) 4 bit gray to binary converter
e. 4 to 1 Multiplexer
f. Comparator.
3HDL code for N-bit ALU
4 HDL code to describe the functions of a Full Adder Using three modeling styles
(i) Data flow modeling(ii) Behavioral Modeling(iii) Structural modeling
5 HDL code for the following flip-flops
(i) SR flipflop(ii) D flipflop(iii) JK flipflop(iv) T flipflop
6 HDL code for
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(i)4 bit binary counter with synchronous reset
(ii)4 bit counter with asynchronous reset
(iii) BCD counter
PART B
INTERFACING
Sl.No Name of the experiment
1 HDL code to display messages on the given seven segment display
and LCD and accepting Hex key pad input data.
2 HDL code to control speed, direction of DC motor.
3 HDL code to control speed, direction of Stepper motor.
4 HDL code to generate different waveforms using DAC change the frequency and amplitude.
(i) Square wave(ii) Triangular wave(iii) Ramp wave(iv) Sawtooth wave
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PART A
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OUTPUT 1
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Program1.
Write VHDL code to realize all gates
library IEEE;
use IEEE.STD_Logic_1164.ALL;
use IEEE.STD_Logic_ARITH . ALL;
use IEEE.STD_Logic_UNSIGNED.ALL;
entity gates is
Port (Ain :in std_logic;
Bin :in std_logic;
Op_not : out std_logic;
Op_or : out std_logic;
Op_and :out std_logic;
Op_nor :out std_logic;
Op_nand : out std_logic;
Op_xor : out std_logic;
Op_xnor: out std_logic);
end gates;
architecture Behavioral of gates is
begin
Op_not<= not Ain;
Op_or <= Ain or Bin;
Op_and <= Ain and Bin;
Op_nor <= Ain nor Bin;
Op_nand <= Ain nand Bin;
Op_xor <= Ain xor Bin;
Op_xnor <= Ain xnor Bin;
end Behavioral;
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Write verilog code to realize all gates
module allgates(A,B,not1, or2,and3, nor4,nand5,xor6, xnor7);
input A;
input B;
output not1;
output or2;
output and3;
output nor4;
output nand5;
output xor6;
output xnor7;
reg not1;
reg or2;
reg and3;
reg nor4;
reg nand5;
reg xor6;
reg xnor7;
always@(A or B)
begin
not1 = ~(A);
and3 = (A) & (B);
or2 = A|B;
nand5= ~((A) & (B));
nor4= ~((A) | (B));
xor6= (A) ^ (B);
xnor7= ~((A) ^ (B));
end
endmodule
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OUTPUT 2.a
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Program 2.a
Write VHDL code for 2 to 4 decoder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Decoder2_4 is
port(Enable: in STD_LOGIC;
D_IN: in STD_LOGIC_VECTOR(1downto 0);
D_OUT: out STD_LOGIC_VECTOR(3 downto 0));
end decoder2_4;
architecture Decoder_arc of Decoder2_4 is
begin
process (Enable,D_IN)
begin
if (Enable='1')then
D_OUT<="0000";
else
case D_IN is
when "00"=>D_OUT<="0001";
when "01"=>D_OUT<="0010";
when "10"=>D_OUT<="0100";
when "11"=>D_OUT<="1000";
when others=>NULL;
end case;
end if;
end process;
end Decoder_arc;
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Write verilog code for 2 to 4 decoder
module decoder(a, en,y);
input[1:0]a;
input en;
output[3:0]y;
reg[3:0]y;
always@(en or a)
begin
if(en= =1)
y=4'b0001;
else
case(a)
2'b00:y =4'b0001;
2'b01:y= 4'b0010;
2'b10:y= 4'b0100;
2'b11:y= 4'b1000;
default :y=4'b0000;
endcase
end
endmodule
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OUTPUT 2.b(i)
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Program 2.b(i)
Write VHDL code for 8 to 3 encoder without priority
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity code is
port(EN:in STD_LOGIC;
D_IN: in STD_LOGIC_VECTOR(7 downto 0);
D_OUT: out STD_LOGIC_VECTOR(2 downto 0));
end code;
architecture encoder_arch of code is
begin
process(EN,D_IN)
begin
if (EN='1')then
D_OUT<="000";
else
case D_IN is
when "00000001"=>D_OUT<="000";
when "00000010"=>D_OUT<="001";
when "00000100"=>D_OUT<="010";
when "00001000"=>D_OUT<="011";
when "00010000"=>D_OUT<="100";
when "00100000"=>D_OUT<="101";
When "01000000"=>D_OUT<="110";
when "10000000"=>D_OUT<="111";
when others=>NULL;
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end case;
end if;
end process;
end encoder_arch;
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Write verilog code for 8 to 3 encoder without priority
module encode(Ain, En,Yout);
input En;
input [7:0]Ain;
output[2:0]Yout;
reg [2:0]Yout;
always @ (En or Ain)
begin
if (en==1)
Yout=3'b0;
else
case (Ain)
8'b00000001:Yout=3'b000;
8'b00000010:Yout=3'b001;
8'b00000100:Yout=3'b010;
8'b00001000:Yout=3'b011;
8'b00010000:Yout=3'b100;
8'b00100000:Yout=3'b101;
8'b01000000:Yout=3'b110;
8'b10000000:Yout=3'b111;
default:Yout=3'b000;
endcase
end
endmodule
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OUTPUT 2.b(ii)
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Program 2.b(ii)
Write VHDL code for 8 to 3 encoder with priority
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prio is
Port (e :in std_logic;din :in std_logic_vector(7 downto 0);
dout : out std_logic_vector(2 downto 0));
end prio;
architecture Behavioral of prio is
begin
process(din,e)
begin
if(e='1')then
dout<="000";
elsif(din(0)='1')then
dout<="000";
elsif(din(1)='1')then
dout<="001";
elsif(din(2)='1')then
dout<="010";
elsif(din(3)='1')then
dout<="011";
elsif(din(4)='1')then
dout<="100";
elsif(din(5)='1')then
dout<="101";
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elsif(din(6)='1')then
dout<="110";
else dout<="111";
end if;
end process;
end Behavioral;
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Write verilog code for 8 to 3 encoder with priority
module prienco1(e,din,dout);
input[7:0]din;
input e;
output[2:0]dout;
reg[2:0]dout;
always@(din,e)
begin
if (e= =1)
dout=3'b000;
else if (din[0]==1)dout=3'b000;
else if(din[1]==1)dout=3'b001;
else if(din[2]==1)dout=3'b010;
else if(din[3]==1)dout=3'b011;
else if(din[4]==1)dout=3'b100;
else if(din[5]==1)dout=3'b101;
else if(din[6]==1)dout=3'b110;
else if(din[7]==1)dout=3'b111;
else
dout=3'b000;
end
endmodule
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OUTPUT 2.c
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Program 2.c
Write VHDL code for 8 to 1 multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity Mux8_1 is
port(SEL:in STD_LOGIC_VECTOR(2 downto 0);
A,B,C,D,E,F,G,H :in STD_LOGIC; MUX_OUT: out STD_LOGIC};
end Mux8_1;
architecture mux4_1_arch of Mux8_1 is
begin
process (SEL,A,B,C,D,E,F,G,H)
begin
case SEL is
when "000"=>MUX_OUT<=A;
when "001"=>MUX_OUT<=B;
when "010"=>MUX_OUT<=C;
when "011"=>MUX_OUT<=D;
when "100"=>MUX_OUT<=E;
when "101"=>MUX_OUT<=F;
when "110"=>MUX_OUT<=G;
when "111"=>MUX_OUT<=H;
when others =>null;
end case;
end process;
end mux4_1_arch;
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Write verilog code for 8 to 1 multiplexer
module mux(en, a, y,sel);
input en;
input[7:0]a;
input[2:0]sel;
output y;
reg y;
always@(en or a)
begin
if(!en)
y=1'b0;
else case(sel)
3'b000:y=a[7];
3'b001:y=a[6];
3'b010:y=a[5];
3'b011:y=a[4];
3'b100:y=a[3];
3'b101:y=a[2];
3'b110:y=a[1];
3'b111:y=a[0];
endcase
end
endmodule
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OUTPUT 2.d(i)
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Program 2.d(i)
Write VHDL code for 4 bit binary to gray converter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binary_Gray is
port( a:in std_logic_vector(3 downto 0);
b:out std_logic_vector(3 downto 0));
end binary_gray;
architecture behavioral of binary_gray is begin
b(3)<=a(3);
b(2)<=a(3)xor a(2);
b(1)<=a(2)xor a(1);
b(0)<=a(1)xor a(0);
end behavioral;
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Write verilog code for 4 bit binary to gray converter
module bintogrey(a,b)
Input [3:0]a;
Output [3:0]b;
Reg [3:0]b;
always@(a,b)
Begin
b[3]=a[3];
b[2]=a[3]^a[2];
b[1]=a[2]^a[1];
b[0]=a[1]^a[0];
end
endmodule
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OUTPUT 2.d(ii)
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Program 2.d(ii)
Write VHDL code for 4 bit gray to binary converter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gray_bin is
port( b:out std_logic_vector(3 downto 0);
g:in std_logic_vector(3 downto 0));
end gray_bin;
architecture behavioral of gray_bin is
begin
b(3)<=g(3);
b(2)<=g(3)xor g(2);
b(1)<=g(3) xor g(2)xor g(1);
b(0)<=g(3) xor g(2) xor g(1)xor g(0);
end behavioral;
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Write verilog code for 4 bit gray to binary converter
module graytbin(g,b);
input [3:0]g;
output [3:0]b;
reg [3:0]b;
always@(g)
begin
b[3]=g[3];
b[2]=g[3]^g[2];
b[1]=g[3]^g[2]^g[1];
b[0]=g[3]^g[2]^g[1]^g[0];
end
endmodule
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OUTPUT 2.e
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Program 2.e
Write VHDL code for 4 to 1 multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux is
Port(din: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(1 downto 0);dout:out std_logic);
end mux;
architecture Behavioral of mux is
begin
process(din,sel)
begin
case sel is
when "00"=>dout<=din(0);
when "01"=>dout<=din(1);
when "10"=>dout<=din(2);
when "11"=>dout<=din(3);
when others=>null;
end case;
end process;
end Behavioral;
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Write verilog code for 4 to 1 multiplexer
module mux(din,sel,dout);
input[3:0]din;
input[1:0]sel;
output dout;
reg dout;
always @(din,sel)
begin
case(sel)
2'b00:dout=din[0];
2'b01:dout=din[1];
2'b10:dout=din[2];
default:dout=din[3];
endcase
end
endmodule
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OUTPUT 2.e(ii)
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Program 2.e(ii)
Write VHDL module for n-bit comparator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Generic(N:integer:=3);
Port(A,B:in STD_LOGIC_VECTOR(N downto 0);
ALB,AGB,AEB:out STD_LOGIC);
end comparator;
architecture Comparator_arc of comparator is
begin
process(A,B)
begin
if (A<B) then ALB<='1';
else ALB<='0';
end if;
if (A>B) then AGB<='1';
else AGB<='0';
end if;
if (A=B) then AEB<='1';
else AEB<='0';
end if;
end process;
end Comparator_arc;
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Write verilog module for n- bit comparator
module comparator(A,B,alb,agb,aeb);
input [3:0]A,B;
output alb,agb,aeb;
reg alb,agb,aeb;
always@(A,B)
begin
if(A > B)
agb=1;
else
agb=0;
if(A==B)
aeb=1;
else
aeb=0;
if (A<B)
alb=1;
else
alb=0;
end
endmodule
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OUTPUT 3
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Program 3
Write VHDL module for n bit ALU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu1 is
Port(a,b :in std_logic_vector(2 downto 0);
e: in std_logic;
opcode : in std_logic_vector(2 downto 0);
y :out std_logic_vector(2 downto 0));
end alu1;
architecture Behavioral of alu1 is
begin
process(e,opcode)
begin
if(e='1')then
case opcode is
when "000"=>y<=a+b;
when "001"=>y<=a-b;
when "010"=>y<=not a;
when "011"=>y<=a and b;
when "100"=>y<=a nand b;
when "101"=>y<=a or b;
when "110"=>y<=a nor b;
when "111"=>y<=a xnor b;
when others=>null;
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end case;
else
y<=(others=>'0');
end if;
end process;
end Behavioral;
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Write verilog module for n bit ALU
module aluvlg(e,a,b,opcode,y);
input e;
input [2:0] a,b;
input [2:0] opcode;
output [2:0]y;
reg[2:0]y;
always@(a or b or opcode)
begin
if (e==1)
case(opcode)
3'd0:y=a+b;
3'd1:y=a-b;
3'd2:y= ~b;
3'd3:y=a&b;
3'd4:y=a|b;
3'd5:y= ~(a&b);
3'd6:y= ~(a|b);
3'd7:y= a^b;
endcase
else y=3'b000;
end
endmodule
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OUTPUT 4(i)
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Program 4(i)
Write VHDL module for full adder using dataflow styles
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladdr is
Port (a,b,c : in std_logic;
sum,carry:out std_logic);
end fulladdr;
architecture Behavioral of fulladdr is
begin
sum<=a xor b xor c;
carry<=(a and b)or(b and c)or( c and a);
end behavioral;
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Write verilog module for full adder using behavioral style
module fulldavl(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=(a&b)(b&c)(c&a);
endmodule
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OUTPUT 4(ii)
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Program 4(ii)
Write VHDL module for full adder using behavioral style
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder is
Port (a,b,c :in std_logic;
sum,carry:out std_logic);
end adder;
architecture Behavioral of adder is
begin
process(a,b,c)
begin
sum<=a xor b xor c; carry<=(a and b)or(b and c)or(c and a);
end process;
end Behavioral;
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Write verilog module for full adder using behavioral style
module fullbevl(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
reg sum,carry;
always @(a,b,c)
begin
sum=a^b^c;
carry=(a&b)(b&c)(c&a);
end
endmodule
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OUTPUT 4(iii)
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Program 4(iii)
Write VHDL module for full adder using structural style
STRUCTURAL MODEL
NOTE: STEP1: File->new project->VHDL module:-type or2 program and save. STEP2: Under same project,go to create new source ->VHDL module->type half adder program and save. STEP3: Under same project, go to create new source ->VHDL module->type full adder program and save.
STEP4:Create test bench wave and UCF for full adder
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stfa is Port (x,y,cin :in std_logic; s,c :out std_logic);end stfa;
architecture Behavioral of stfa is
component ha
port(a,b:in std_logic;
s,c:out std_logic);
end component;
component or1
port(a,b:in std_logic;
c: out std_logic);
end component
signal c0,c1,s0 : std_logic;
begin
ha0: ha portmap (y,cin,s0,c0);
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ha1: ha portmap (x,s0,s,c1);
x3: or1 portmap (c0,c1,c);
end behavioral;
subprogram1
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ha is Port (a,b :in std_logic; s,c :out std_logic);end ha;
architecture Behavioral of ha is
begin
s<= a xor b;
c<=a and b;
end behavioral;
subprogram 2
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or1 is Port (a,b :in std_logic; c :out std_logic);end or1;
architecture Behavioral of or1 is
begin
c<= a or b;
end behavioral;
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Write Verilog module for full adder using structural style
module full( a, b, c, sum, carry);input a , b, c;output sum , carry;wire c0,c1, s0;HA x0( b, c , s0, c0);HA x1( a, s0, sum, c1);or x2( carry, c0,c1);endmodule
subprogram
module HA( x, y, sum1, carry1);input x, y;output sum1, carry1;assign sum1=x^y;assign carry1=x & y;endmodule
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OUTPUT 5(i)
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Program 5(i)
Write VHDL code for SR flip flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRFF is
port(s:in std_logic;
r:in std_logic;
clk:in std_logic;
q:buffer std_logic);
end SRFF;
architecture s_r_ff_arch of SRFF is
begin
process(clk)
begin
if (clk='1'and clk'event) then
if(s='0' and r='1') then q<='0';
elsif(s='0' and r='1')then q<='0';
elsif(s='1' and r='0')then q<='1';
elsif(s='1' and r='1')then q<='Z';
end if;
end if;
end process;
end s_r_ff_arch;
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Write a verilog code for SR flip-flop
module sr1(sr,q,qnot,clk);
input [1:0] sr;
input clk;
output q,qnot;
reg q,qnot;
initial
begin
q=0;
qnot=1;
end
always@(posedge clk)
begin
case (sr)
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=1'bz;
endcase
qnot=~q;
end
endmodule
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OUTPUT 5(ii)
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Program 5(ii)
Write VHDL code for D flip flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFF is
port( clk:in STD_LOGIC;
d: in STD_LOGIC ;
q: out STD_LOGIC:='1');
end DFF;
architecture d_ff_arch of DFF is
begin
process(clk)
begin
if(clk'event and clk='1')then
q<=d;
end if;
end process;
end d_ff_arch;
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Write a verilog code for D flip-flop
module sync_dff(d,clk,reset,q);
input d,clk,reset;
output q;
reg q;
initial
q=1'b1;
always@(posedge clk)
if(~reset)
q=1'b0;
else
q=d;
endmodule
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HDL lab manual 2013
OUTPUT 5(iii)
DEPT of ECE Page 54
HDL lab manual 2013
Program 5(iii)
Write a VHDL code for JK flip-flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity JKFF is
port(clk, j, k :in std_logic;
q : buffer std_logic);
end JKFF;
architecture behavioral of JKFF is
begin
process(clk,j,k)
begin
if(clk'event and clk='1')then
if(j='0' and k='0') then
q<=q;
elsif(j='0' and k='1')then
q<='0';
elsif(j='1' and k='0')then
q<='1';
elsif(j='1' and k='1') then
q<=not q;
end if;
end if;
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end process;
end behavioral;
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HDL lab manual 2013
Write a verilog code for JK flip-flop
module jkff(clk,reset,jk,q);
input clk,reset;
input [1:0]jk;
output q;
reg q;
initial
q=1'b0;
always@(posedge clk)
begin
if(reset)
q=0;
else
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
end
endmodule
DEPT of ECE Page 57
HDL lab manual 2013
OUTPUT 5(iv)
DEPT of ECE Page 58
HDL lab manual 2013
Program 5 (iv)
Write a VHDL module for T flip-flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lit is
port(clk,t :in std_logic;
q : buffer std_logic);
end lit;
architecture Behavioral of lit is
begin
process( t,clk)
begin
if(rising_edge (clk)) then
q<= t xor q;
end if;
end process;
end Behavioral;
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HDL lab manual 2013
Write a verilog code for T flip-flop
module tffv(t,q,clk);
input t,clk;
output q;
reg q;
initial
q=1;
always@(posedge clk)
begin
case (t)
1'b0: q=q;
1'b1: q=~q;
endcase
end
endmodule
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HDL lab manual 2013
OUTPUT 6(i)
DEPT of ECE Page 61
HDL lab manual 2013
Program 6 (i)
Write a VHDL module for 4-bit binary counter with synchronous reset
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync is
port(clk,reset: in std_logic; count:out std_logic_vector( 3 downto 0):="0000");
end sync;
architecture behavioral of sync is
begin
process(clk, reset)
variable temp:std_logic_vector(3 downto 0):="1010";
begin
if(clk'event and clk='1') then
if (reset='1')then
temp:="0000";
else
temp:=temp+1;
end if;
count<=temp;
end if;
end process;
end behavioral;
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HDL lab manual 2013
Write a verilog code for 4-bit binary counter with synchronous reset
module syncrst(clk, reset, count);
input clk;
input reset;
output [3:0] count;
reg [3:0]count;
initial
count=4'b1010;
always@(posedge clk)
begin
if (reset==1)
count=4'b0000;
else
count=count+1;
end
endmodule
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HDL lab manual 2013
OUTPUT 6(ii)
DEPT of ECE Page 64
HDL lab manual 2013
Program 6(ii)
Write a vhdl code for 4 bit binary counter with asynchronous reset
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync is
port(clk,reset: in std_logic; count:out std_logic_vector( 3 downto 0));
end sync;
architecture behavioral of sync is
begin
process(clk, reset)
variable temp: std_logic_vector(3 downto 0):="0000";
begin
if (reset='1')then
temp:="0000";
elsif(clk='1')then
temp:=temp+1;
end if;
count<=temp;
end process;
end behavioral;
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HDL lab manual 2013
Write a verilog code for 4-bit binary counter with asynchronous reset
module asyncveri(clk, reset, count);
input clk;
input reset;
output [3:0] count;
reg [3:0] count;
initial
count=4'b0000;
always @ (posedge clk)
begin
if (reset==1)
count=4'b0000;
else
count=count+1;
end
endmodule
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HDL lab manual 2013
OUTPUT 6(iii)
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HDL lab manual 2013
Program 6(iii)
Write a VHDL code for BCD counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcdcnt is
port(clk,reset: in std_logic; count:inout std_logic_vector( 3 downto 0):="1001");
end bcdcnt;
architecture behavioral of bcdcnt is
begin
process(clk, reset)
begin
if(clk='1' and clk'event)then
if (reset='1')then
count<="0000";
elsif(count="1001")then
count<="0000";
else
count<=count+1;
end if;
end if;
end process;
end behavioral;
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HDL lab manual 2013
Write a verilog code for BCD counter
module bcdverilog(clk, reset, count);
input clk;
input reset;
output [3:0] count;
reg [3:0] count;
initial
begin
count=4'b1001;
end
always @(posedge clk)
begin
if(reset==1)
count=4'b0000;
else if (count==4'b1001)
count=4'b0000;
else
count=count+1;
end
endmodule
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HDL lab manual 2013
PART B
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HDL lab manual 2013
Program 1
Write a HDL code for displaying messages on seven segment display
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity key is
port (scan_l : out std_logic_vector (3 downto 0);
read_l_in : in std_logic_vector (3 downto 0); clk : in std_logic;
disp_cnt : out std_logic_vector (3 downto 0);
disp: out std_logic_vector (6 downto 0));
end key;
architecture behavioral of key is
signal disp1:std_logic_vector ( 6 downto 0);
signal scan_l_sig : std_logic_vector (3 downto 0);
signal clk_div :std_logic_vector (11 downto 0);
signal clk_4k : std_logic;
signal cnt_2bit :std_logic_vector( 1 downto 0);
signal read_l : std_logic_vector (3 downto 0);
begin
process (clk)
begin
if clk='1' and clk'event then
clk_div <= clk_div + '1';
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end if;
end process;
clk_4k<=clk_div(11);
process (clk_4k)
begin
if clk_4k='1' and clk_4k'event then
cnt_2bit <=cnt_2bit + '1';
end if;
end process;
process (cnt_2bit)
begin
case cnt_2bit is
when "00" => scan_l_sig <="0001";
when "01" => scan_l_sig <="0010";
when "10" => scan_l_sig <="0100";
when "11" => scan_l_sig <="1000";
when others => null;
end case;
end process;
read_l <=read_l_in;
scan_l <= scan_l_sig;
disp_cnt <="1110";
process (scan_l_sig, read_l)
begin
case scan_l_sig is
when "0001" => case read_l is
when "0001" => disp1<="1111110";
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when "0010" => disp1<="0110011";
when "0100" => disp1<="1111111";
when "1000" => disp1<="1001110";
when others=> disp1<="0000000";
end case;
when "0010" => case read_l is
when "0001" => disp1<="0110000";
when "0010" => disp1<="1011011";
when "0100" => disp1<="1111011";
when "1000" => disp1<="0111101";
when others=> disp1<="0000000";
end case;
when "0100" => case read_l is
when "0001" => disp1<="1101101";
when "0010" => disp1<="1011111";
when "0100" => disp1<="1110111";
when "1000" => disp1<="1001111";
when others=> disp1<="0000000";
end case;
when "1000" => case read_l is
when "0001" => disp1<="1111001";
when "0010" => disp1<="1110000";
when "0100" => disp1<="0011111";
when "1000" => disp1<="1000111";
when others=> disp1<="0000000";
end case;
when others =>null;
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end case;
end process;
disp<=disp1;
end behavioral;
UCF file ( user constraints)
NET “clk” LOC=”p52”;
NET “disp_cnt<0>” LOC=”p23”;
NET “disp_cnt<1>” LOC=”p24”;
NET “disp_cnt<2>” LOC=”p26”;
NET “disp_cnt<3>” LOC=”p27”;
NET “disp <0>” LOC=”p18”;
NET “disp <1>” LOC=”p17”;
NET “disp <2>” LOC=”p15”;
NET “disp <3>” LOC=”p14”;
NET “disp <4>” LOC=”p13”;
NET “disp <5>” LOC=”p12”;
NET “disp <6>” LOC=”p1”;
NET “read_l_in <0>” LOC=”p112”;
NET “read_l_in <1>” LOC=”p116”;
NET “read_l_in <2>” LOC=”p119”;
NET “read_l_in <3>” LOC=”p118”;
NET “scan_l <0>” LOC=”p123”;
NET “scan_l <1>” LOC=”p131”;
NET “scan_l <2>” LOC=”p130”;
NET “scan_l <3>” LOC=”p137”;
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Program 2 Write a HDL code to control speed, direction of DC motor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.vcomponents.All;
entity dcmtr is
generic (bits : integer :=8);
port (clk : in std_logic;reset,dir : in std_logic;
pwm : out std_logic_vector(1 downto 0);
rly : out std_logic ; row : in std_logic_vector(0 to 3));
end dcmtr;
architecture behavrioral of dcmtr is
signal counter : std_logic_vector(bits-1 downto 0):="11111110";
signal div_reg : std_logic_vector(16 downto 0);
signal dclk,ddclk,datain,tick : std_logic;
signal duty_cycle : integer range 0 to 255;
signal row1: std_logic_vector(0 to 3);
begin
clk_div : process (clk, div_reg)
begin
if(clk'event and clk='1') then
div_reg <= div_reg+1;
end if;
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end process;
ddclk <= div_reg(12);
tick <= row(0) and row(1) and row(2)and row(3);
process(tick)
begin
if falling_edge (tick) then
case row is
when "1110" => duty_cycle <=255;
when "1101" => duty_cycle <=200;
when "1011" => duty_cycle <=150;
when "0111" => duty_cycle <=100;
when others =>duty_cycle <= 100;
end case;
end if ;
end process;
process(ddclk,reset)
begin
if reset ='0' then
counter <= (others=>'0');
pwm <="01";
elsif ( ddclk'event and ddclk='1')then
counter <=counter+1;
if counter >= duty_cycle then
pwm(1)<='0';
else
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pwm(1)<='1';
end if ;
end if;
end process;
rly <= dir;
end behavrioral;
UCF file ( user constraints)
NET “clk” LOC=”p52”;
NET “dir” LOC=”p76”;
NET “pwm<0>” LOC=”p4”;
NET “pwm<1>” LOC=”p141”;
NET “reset” LOC=”p74”;
NET “rly” LOC=”p44”;
NET “row<0>” LOC=”p69”;
NET “row<1>” LOC=”p63”;
NET “row<2>” LOC=”p59”;
NET “row<3>” LOC=”p57”;
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HDL lab manual 2013
Program3
Write a HDL code to control speed,direction of stepper motor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stprmtr is
port(clk,reset:in std_logic;
dout : out std_logic_vector(3 downto 0);
row : in std_logic_vector(1 downto 0);
dir : in std_logic);
end stprmtr;
architecture behavioral of stprmtr is
signal clk_div :std_logic_vector (25 downto 0);
signal clk_int : std_logic;
signal shift_reg : std_logic_vector (3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <=clk_div + '1';
end if ;
end process;
clk_int<=clk_div(21) when row="00" else
clk_div(19) when row="01" else
clk_div(17) when row="10" else
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clk_div(15) ;
process(reset,clk_int,dir)
begin
if reset ='0' then
shift_reg<="1001";
elsif rising_edge(clk_int)then
if dir='0' then
shift_reg<=shift_reg(0)& shift_reg(3 downto 1);
else
shift_reg<=shift_reg(2 downto 0)& shift_reg (3);
end if;
end if;
end process;
dout<=shift_reg;
end behavioral;
UCF file( user constraints)
NET “clk” LOC=”p52”;
NET “dir” LOC=”p76”;
NET “dout<0>” LOC=”p141”;
NET “dout<1>” LOC=”p2”;
NET “dout<2>” LOC=”p4”;
NET “dout<3>” LOC=”p5”;
NET “reset” LOC=”p74”;
NET “row<0>” LOC=”p77”;
NET “row<1>” LOC=”p79”;
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Program 4 Write a HDL code to generate different waveforms
(i)Square wave
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sqwave is
port (clk : in std_logic; reset : in std_logic;
dac_out : out std_logic_vector (0 to 7));
end sqwave;
architecture behavioral of sqwave is
signal temp : std_logic_vector( 3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge (clk) then
temp <=temp+'1';
end if;
end process;
process(temp(3),reset)
begin
if reset='1' then
counter <= "00000000";
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elsif rising_edge (temp(3)) then
if counter<255 and en='0' then
counter <=counter + 1;
en <='0';
dac_out<="00000000";
elsif counter =0 then
en <='0';
else
en <='1';
counter <=counter -1;
dac_out <="11111111";
end if;
end if;
end process;
end behavioral;
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(ii)Triangular wave
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triwave is
port ( clk : in std_logic ; reset : in std_logic;
dac_out : out std_logic_vector (0 to 7));
end triwave;
architecture behavioral of triwave is
signal counter : std_logic_vector (0 to 8);
signal temp : std_logic_vector (3 downto 0);
signal en : std_logic;
begin
process (clk)
begin
if rising_edge (clk) then
temp <=temp + '1';
end if;
end process;
process(temp(3))
begin
if reset ='1' then
counter <="000000000";
elsif rising_edge (temp(3)) then
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counter <=counter + 1;
if counter(0)='1' then
dac_out <=counter (1 to 8);
else
dac_out <=not(counter (1 to 8));
end if;
end if;
end process;
end behavioral;
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(iii) RAMP WAVE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ramp is
port ( clk : in std_logic; reset : in std_logic;
dac_out : out std_logic_vector ( 0 to 7));
end ramp;
architecture behavioral of ramp is
signal temp : std_logic_vector (3 downto 0);
signal counter : std_logic_vector ( 0 to 7);
signal en : std_logic;
begin
process (clk)
begin
if rising_edge (clk) then
temp <=temp + '1';
end if;
end process;
process (temp(3))
begin
if reset = '1' then
counter <="00000000";
elsif rising_edge (temp (3)) then
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counter <=counter + '1';
end if;
end process;
dac_out <= counter;
end behavioral;
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(iv) SAWTOOTH WAVE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sawtooth is
port (clk : in std_logic ; reset : in std_logic;
dac_out : out std_logic_vector (0 to 7));
end sawtooth;
architecture behavioral of sawtooth is
signal temp: std_logic_vector( 3 downto 0);
signal counter : std_logic_vector( 0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge (clk) then
temp <=temp +'1';
end if;
end process;
process (temp(3))
begin
if (reset ='1') then
counter <= "00000000";
elsif rising_edge(temp(3)) then
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counter <=counter +8;
end if ;
end process;
dac_out <= counter;
end behavioral;
UCF file( user constraints)
NET “clk” LOC=”p52”;
NET “dac_out<0>” LOC=”p21”;
NET “dac_out<1>” LOC=”p18”;
NET “dac_out<2>” LOC=”p17”;
NET “dac_out<3>” LOC=”p15”;
NET “dac_out<4>” LOC=”p14”;
NET “dac_out<5>” LOC=”p13”;
NET “dac_out<6>” LOC=”p12”;
NET “dac_out<7>” LOC=”p1”;
NET “rst” LOC=”p74”;
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