vhdl.docx

DIGITAL CIRCUITS AND SYSTEMS II

VHDL LAB

Jyoti Kadian

254/CO/10

COE-1

INDEX

SI EXPERIMENTS SIGNATURE

1. Design of decoder (2 x 4), encoder (4 x 2), binary to gray code convertor.

2. Model flip-flop, register with asynchronous and synchronous reset.

3. Design of a divide by 5 FSM

4. Design of a traffic light controller

5. Binary and BCD counter

6. Data De-multiplexer

7. Serialinput and parallel output shift register

8. Arithmetic and logic unit

9. Huffman Decoder for 2 bit black and white pixel image

EXPERIMENT NO. 1 -- Module Name: DECODER (2X4) library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder is Port ( input : in STD_LOGIC_VECTOR (1 downto 0);enable : in STD_LOGIC;output : out STD_LOGIC_VECTOR (3 downto 0));end decoder; architecture Behavioral of decoder isbeginprocess(enable, input)beginif (enable='1') thenoutput(0)<= (not input(1)) and (not input(0));output(1)<= (not input(1)) and input(0);output(2)<= input(1) and (not input(0));output(3)<= input(1) and input(0);elseoutput<= "0000";end if;end process;end Behavioral;

SIMULATION

-- Module Name: ENCODER (4X2) library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder is Port ( input : in STD_LOGIC_VECTOR (3 downto 0);output : out STD_LOGIC_VECTOR (1 downto 0));end encoder; architecture Behavioral of encoder is beginoutput(1) <= input(3) or input(2);output(0) <= input(3) or input(1);end Behavioral;

SIMULATION

-- Module Name: BINARY TO GRAY CODE CONVERTOR library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entitybinary_gray isport ( binary : in STD_LOGIC_VECTOR(3 downto 0);gray : out STD_LOGIC_VECTOR(3 downto 0)); endbinary_gray; architectureBehavioral of binary_gray is begingray(3) <= binary(3);gray(2) <= binary(3) xor binary(2);gray(1) <= binary(2) xor binary(1);gray(0) <= binary(1) xor binary(0);end Behavioral;

SIMULATION

EXPERIMENT NO. 2 -- Module Name: FLIP FLOP WITH ASYNCH & SYNCH RESET library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entityflip_flop isport ( input,clock,synch_reset,asynch_reset : in STD_LOGIC;output : out STD_LOGIC);endflip_flop; architectureBehavioral of flip_flop isbeginprocess(clock,asynch_reset)beginif (asynch_reset='1') thenoutput<= '0';elsifrising_edge(clock) thenif (synch_reset='1') then

output<= '0';elseoutput<= input;end if;

end if;end process;end Behavioral;

SIMULATION

-- Module Name: REGISTER WITH ASYNCH & SYNCH RESET library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entity register_8 isport ( input : in STD_LOGIC_VECTOR(7 downto 0);rdbar, wrbar, asynch_reset, synch_reset, clock : in STD_LOGIC; output : out STD_LOGIC_VECTOR(7 downto 0):=(others=>'Z'));end register_8; architecture Behavioral of register_8 issignal load : STD_LOGIC_VECTOR(7 downto 0);beginprocess(asynch_reset, clock)beginif (asynch_reset='1') thenload<= (others=>'0');elsifrising_edge(clock) thenif (synch_reset='1') then

load<= (others=>'0');elsif (rdbar='0') thenoutput<= load;elsif (wrbar='0') thenload<= input;elsif (rdbar='1') thenoutput<= (others=>'Z');

end if;end if;end process;end Behavioral; SIMULATION

EXPERIMENT NO. 3 -- Module Name: DIVIDE BY 5 FSM library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entity divide_by_5 isport ( data_in, clock, reset : in STD_LOGIC;output : out STD_LOGIC); end divide_by_5; architecture Behavioral of divide_by_5 istypestate_type is (state0, state1, state2, state3, state4, state5);-- six states corresponds to reset and five remainders (i.e. 0,1,2,3,4 when any number is divided by 5)signal state, next_state : state_type;signal temp : STD_LOGIC;begin label_1:process(clock)--this process is used for assigning next state at every rising edge of clockbeginifrising_edge(clock) then

if (reset='1') thenstate<= state0;elsestate<= next_state;end if;

end if;end process; label_2: process (state)--this process is used only for assigning outputs to corresponding states.begin-- only state1 has a output '1' coz it denotes '0' remainder state.if (state = state1) then

temp<= '1'; elsetemp<= '0';end if;

end process;label_3: process (state, data_in, reset)--this process corresponds to "how the states change in the state diagram upon excitation"beginnext_state<= state;--declare default state for next_state

case (state) iswhen state0 =>if reset = '0' thennext_state<= state1;end if;when state1 =>ifdata_in = '0' thennext_state<= state1;

elsifdata_in = '1' thennext_state<= state2;

end if;when state2 =>ifdata_in = '0' thennext_state<= state3;


end if;when state3 =>

ifdata_in = '0' thennext_state<= state5;








end if;when others =>next_state<= state0;end case; end process; output<= temp;end Behavioral;SIMULATION

EXPERIMENT NO. 4 -- Module Name: TRAFFIC LIGHT CONTROLLER library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entitytraffic_light_controller isport ( clock, reset : in STD_LOGIC; red1, yellow1, green1 : out STD_LOGIC;

red2, yellow2, green2 : out STD_LOGIC; red3, yellow3, green3 : out STD_LOGIC; red4, yellow4, green4 : out STD_LOGIC);

endtraffic_light_controller; architectureBehavioral of traffic_light_controller istypestate_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8); -- nine states corresponds to reset and state for each "side traffic light" signal state : state_type;signal count : STD_LOGIC_VECTOR(2 downto 0);--count signal is used to keep track of time limit for each light.signal reds1, yellows1, greens1 : STD_LOGIC;signal reds2, yellows2, greens2 : STD_LOGIC;signal reds3, yellows3, greens3 : STD_LOGIC;signal reds4, yellows4, greens4 : STD_LOGIC;begin label_1: process(state) --this process is used only for assigning outputs to corresponding states.beginif (state = s0) then

reds4 <= '0'; reds3 <= '0'; reds2 <= '0'; reds1 <= '0'; greens4 <= '0'; greens3 <= '0'; greens2 <= '0'; greens1 <= '0'; yellows4 <= '0'; yellows3 <= '0'; yellows2 <= '0'; yellows1 <= '0';

elsif (state = s1) then reds4 <= '1';

reds3 <= '1'; reds2 <= '1'; reds1 <= '0'; greens4 <= '0'; greens3 <= '0'; greens2 <= '0'; greens1 <= '1';

yellows4 <= '0'; yellows3 <= '0'; yellows2 <= '0'; yellows1 <= '0';


reds3 <= '1'; reds2 <= '1'; reds1 <= '0'; greens4 <= '0'; greens3 <= '0'; greens2 <= '0'; greens1 <= '0'; yellows4 <= '0'; yellows3 <= '0'; yellows2 <= '0'; yellows1 <= '1';






reds3 <= '0'; reds2 <= '1'; reds1 <= '1'; greens4 <= '0'; greens3 <= '1'; greens2 <= '0'; greens1 <= '0'; yellows4 <= '0'; yellows3 <= '0'; yellows2 <= '0';

yellows1 <= '0';







end if;end process; label_2: process(clock, reset)beginif reset = '1' then state<= s0; count<= "000"; elsifrising_edge(clock) then case (state) is

when s0 =>if (reset='0') thenstate<= s1;end if;when s1 =>

if (count <= "101") then --to keep state1 active for "5 SEC"count<= count + 1;

elsecount<= "000";state<= s2;

end if;when s2 =>if (count <= "001") then --to keep state1 active for "1 SEC"

count<= count + 1;elsecount<= "000";state<= s3;



end if;when s4 =>

if (count <= "001") then --to keep state1 active for "1 SEC"count<= count + 1;

elsecount<= "000";state<= s5;









end if;when others =>state<= s0;

end case;end if;

end process;

red1 <= reds1;red2 <= reds2;red3 <= reds3;red4 <= reds4;green1 <= greens1;green2 <= greens2;green3 <= greens3;green4 <= greens4;yellow1 <= yellows1;yellow2 <= yellows2;yellow3 <= yellows3;yellow4 <= yellows4; end Behavioral; SIMULATION

EXPERIMENT NO. 5

-- Module Name: BINARY COUNTER library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entitybinary_counter isport ( reset,clock,clock_enable : in STD_LOGIC;count : out STD_LOGIC_VECTOR(4 downto 0));endbinary_counter; architectureBehavioral of binary_counter issignalcountt : STD_LOGIC_VECTOR(4 downto 0):=(others=>'0');beginprocess(reset,clock)begin if (reset='1') thencountt<= (others=>'0');elsifrising_edge(clock) thenif (clock_enable='1') then

countt<= countt + 1;end if;end if;end process; count<= countt;end Behavioral;

SIMULATION

-- Module Name: BCD COUNTER

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entitybcdcounter isport (reset,clock_enable,clock : in STD_LOGIC;bcd : out STD_LOGIC_VECTOR(3 downto 0));endbcdcounter; architectureBehavioral of bcdcounter issignal temp : STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); beginprocess(reset,clock)begin if (reset='1') thentemp<= (others=>'0');elsifrising_edge(clock) thenif (clock_enable='1') then

if (temp="1001") thentemp<= (others=>'0');

elsetemp<= temp + 1;end if;end if;

end if;

end process;bcd<= temp;end Behavioral;

SIMULATION

EXPERIMENT NO. 6

-- Module Name: DATA DEMULTIPLEXER

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entitydata_demux isport ( input : in STD_LOGIC_VECTOR(3 downto 0);clock : in STD_LOGIC; out_1, out_2, out_3 : out STD_LOGIC_VECTOR(3 downto 0));enddata_demux;architectureBehavioral of data_demux issignal out1, out2, out3 : STD_LOGIC_VECTOR(3 downto 0);signal var1 : STD_LOGIC:='0';signal var2 : STD_LOGIC:='1';signal var3 : STD_LOGIC:='1';beginprocess(clock)beginifrising_edge(clock) thenif (var1='0') then var1 <='1';

var2 <='0'; var3 <='1';

out1 <= input; out2 <= "ZZZZ"; out3 <= "ZZZZ";

elsif (var2='0') then var1 <='1'; var2 <='1'; var3 <='0';


elsif (var3='0') then var1 <='0';

var2 <='1'; var3 <='1';


end if;end if;end process;out_1 <= out1;out_2 <= out2;out_3 <= out3;end Behavioral;

SIMULATION

EXPERIMENT NO. 7

-- Module Name: SERIAL IN PARALLEL OUT SHIFT REGISTER

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entitysipo_req isport ( input,reset,clock,clock_enable : in STD_LOGIC;parallel_out : out STD_LOGIC_VECTOR(3 downto 0));endsipo_req; architectureBehavioral of sipo_req issignal temp : STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');beginprocess(reset,clock)beginif (reset='1') thentemp<= (others=>'0');elsifrising_edge(clock) thenif (clock_enable='1') then

temp<= temp(2 downto 0) & input;end if;

end if;

end process;parallel_out<= temp;end Behavioral;

SIMULATION

EXPERIMENT NO. 8

-- Module Name: ARITHMETIC LOGIC UNIT

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entityalu isport ( temp_reg, accumulator : in STD_LOGIC_VECTOR(7 downto 0);sel_line : in STD_LOGIC_VECTOR(3 downto 0);

out_reg : out STD_LOGIC_VECTOR(7 downto 0));

endalu; architectureBehavioral of alu issignalout_rg : STD_LOGIC_VECTOR(7 downto 0);beginprocess(temp_reg, accumulator, sel_line)begin case (sel_line) is

when "0000" =>out_rg<= temp_reg + accumulator; -- add operation

when "0001" =>out_rg<= temp_reg + accumulator + 1; -- add with carry

when "0010" =>out_rg<= temp_reg + (not accumulator); -- subtract with borrow

when "0011" =>out_rg<= temp_reg + (not accumulator) + 1; -- subtract

when "0100" =>out_rg<= accumulator; -- transfer accumulator

when "0101" =>out_rg<= accumulator + 1; -- increment accumulator

when "0110" =>out_rg<= accumulator - 1; -- decrement accumulator

when "0111" =>out_rg<= temp_reg xnor accumulator; -- logical xnor

when "1000" =>out_rg<= temp_reg or accumulator; -- logical or

when "1001" =>out_rg<= temp_reg and accumulator; -- logical and

when "1010" =>out_rg<= not accumulator; -- logical not

when "1011" =>out_rg<= temp_reg nand accumulator; -- logical nand

when "1100" =>out_rg<= temp_reg nor accumulator; -- logical nor

when "1101" =>out_rg<= temp_reg xor accumulator; -- logical xor

when "1110" =>out_rg<= accumulator(6 downto 0) & '0'; -- logical left shiftwhen "1111" =>out_rg<= '0' &accumulator(7 downto 1) ; -- logical right shift

when others =>out_rg<= (others=>'0');

end case;

end process; out_reg<= out_rg; end Behavioral;

SIMULATION

EXPERIMENT NO. 9

-- Module Name: HUFFMAN DECODER

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entityhuffman_decoder isport ( data_in, clock, reset : in STD_LOGIC;output : out STD_LOGIC_VECTOR(1 downto 0)); endhuffman_decoder;architectureBehavioral of huffman_decoder istypestate_type is (state0, state1, state2, state3, state4, state5, state6);signal state, next_state : state_type;signal temp : STD_LOGIC_VECTOR(1 downto 0);beginlabel_1:process(clock)--this process is used for assigning next state to present state at every rising edge of clockbeginifrising_edge(clock) then

if (reset='1') thenstate<= state0;elsestate<= next_state;end if;

end if;end process;label_2: process (state)--this process is used only for assigning outputs to corresponding states.beginif (state = state1) then

temp<= "00"; elsif (state = state3) thentemp<= "11";

elsif (state = state5) thentemp<= "01";

elsif (state = state6) thentemp<= "10";

elsetemp(1) <= 'Z';

temp(0) <= 'Z';end if;

end process;label_3: process (state, data_in, reset)--this process corresponds to "how the states change in the state diagram upon excitation"beginnext_state<= state;--declare default state for next_state

case (state) iswhen state0 =>if reset = '0' then

if (data_in='1') thennext_state<= state1;

elsif (data_in='0') then

next_state<= state2;end if;

















end if;when others =>next_state<= state0;end case; end process;output<= temp;end Behavioral;SIMULATION

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