VHDL Modelling - Describing Behaviour

VHDL Modelling - Describing Behaviour

Introduction:

This subject will explore how to design implement and test hardware digital systems by

focussing on the required "behaviour" and the system architecture, to enable computer

based tools to then generate the actual implementation for you.

So far you may have experienced designing simple digital systems using either digital

logic gates, or written a program using assembler or 'C'.

A third approach to designing a digital system however is by describing the required

"behaviour" using a hardware description language called VHDL. (Which as an acronym

for Very High Speed Integrated Circuit - Hardware Description Language)

Most of the development will be done using a computer and many of the technical terms and concepts will be similar to those found in other traditional computer languages - this similarity might help at the start, but most of the time, to create VHDL modules that translate into successful hardware that works as required, many of the concepts you will meet, and how you will have to think, will be new. From one view VHDL and Systems Design is easy - If you go about things in the right way, if you follow a set of simple rules, if you keep an attention to detail - then things should go smoothly. From another view VHDL and Systems Design may at first seem difficult - there are many new "rules" and concepts to understand and remember - and the way you need to think about and write VHDL is different from other computer languages you will have met. Overall, however, there is nothing really complex to master, and the rules are all relatively simple.

Aim of Studying this Subject: Your aim in studying this subject is to reach a level of understanding that allows you to design and implement digital systems through the use of VHDL behavioural modelling targeted at a programmable logic implementation. The goal is for you to do some real engineering development such that you have a skill for the future.


The Design Process: The design process for developing a VHDL model targeted at a programmable logic implementation, in summary, is as follows:

• Preliminary design on paper to define input and output signals and overview of the expected behaviour.

• Create the VHDL behavioural model.

• Run simulation and analyse results to prove correctness of expected behaviour.

• Synthesize and Implement Design using computer based tools.

• Download configuration file to the Programmable Logic Device.

When modelling the behaviour for hardware we are following an alternative route in the

design process in reaching a working solution.


Modelling Hardware: VHDL, because it is language based, has, like any other computer language, syntax rules and constraints that must be followed - For the greatest success however, VHDL should not be viewed as a programming language that gets "run" or "executed", but as a way of describing the architecture and behaviour of a hardware based system, that will be implemented using logic gates interconnected with wires.

Systems Design - Divide and Conquer:

A system, such that it fulfils the requirements of an original specification, is normally defined as a collection of simpler sub-systems, which together form an overall solution. The reasons for taking this approach is to "divide and conquer" the system into simpler sub-systems such that they can then each be defined, developed and tested as separate blocks and then integrated in a controlled way to arrive at the final solution. In this way the overall complexity in managed by reducing the system into a set of easy to understand building blocks each with its own defined behaviour. Trying to design a system as one large block will always hit problems due to having to cope with all the complexity at the same time – especially when undertaking the design process for the first time and therefore lacking experience.

Building Blocks: Within digital systems, despite their overall complexity and functionality, there are in reality a limited set of "standard" building blocks that make up such systems. The goal in systems design therefore is to break a problem down into simpler sections to the point where the lowest level blocks are the standard "Lego Bricks" that then easily fit together to make up the system. Systems design is therefore a mix of top-down and bottom-up approaches.


A first step in modelling behaviour:

Signals

Information within hardware moves around a system through wires.

With VHDL wires are represented as "signals".

To transfer the value of one signal to another in hardware - such as B to T and C to V - we would use wires

In VHDL we describe this transfer by the use of the "assignment operator" "<=" This gives a fixed assignment where B always feeds T; and C always feeds V. Within any hardware system there is generally more than one thing happening at the same time - called concurrency - which we therefore need some way of describing when we are designing a hardware based system in VHDL. Given that the two wires we have just described could have different values on them at any given instant - then the two assignment statements if they were within a VHDL model would be concurrent - and could therefore appear in any order. Logic Functions Often within a system, a set of input signals applied to a building block with particular values causes the outputs to generate a known set of values. Such building blocks normally implement Boolean logic functions through the use of combinational logic. When using the traditional circuit design technique - there is normally a process of logic minimisation that needs to take place by the application of Boolean algebra and Karnaugh Maps to achieve the minimum of logic gates for implementation. With VHDL any minimisation takes place later in the design process within the computer based tools - so at the Behavioural level then one only needs to ensure that the logical requirement is fully described without worrying about the actual implementation at this stage. The first step is to define the inputs and outputs for the building block to be modelled.


Functions can normally defined by a "Truth Table" showing the output that is required of each particular combination of inputs. For a simple function with two inputs for example: Here we describe the values that are assigned to the output W for each combination of the inputs R and T. We are simply encoding the truth table using a conditional signal assignment statement. The example given here - explicitly shows the output for ALL possible input combinations. It is possible to describe the required function however using less terms. The three ways shown above of describing the required behaviour are all equivalent and would result in the same implementation. The syntax for a conditional signal assignment is as follows: The key point to notice is the last value that is assigned if all the previous conditions are NOT true - This is the "Default Value" and must appear at the end of the statement. Because of this "rule" you will also notice that when specifying all input combinations as shown in the first description for the output W with all four input combinations of R and T above, five output values needed to given to fulfil the rule of having the unconditional value at the end of the statement. For a function with three inputs one simply includes more signals in each condition.


In the logic functions considered so far we have simple encoded the truth table using a conditional signal assignment statements. If the Boolean equation for a function is known then it is possible to describe the equation using built-in logic functions within VHDL. e.g. More complex building blocks can be described using a number of conditional signal assignment statements - for example a 2 to 4 Decoder…

…where four concurrent statements describe the behaviour of each output where only one output is high at any one time. If an active low output is required then one simply changes the assignment values…

Conditional Signal Assignment statements can be used to model other constructs found

in hardware. If one wanted control of the source of a signal that drives a particular

destination then one can have:

… and if we needed to drive another signal in a similar way:


We therefore have two behavioural statements: …where because these two actions take place at the same time - Then these statements are concurrent … and because the statements are concurrent then they can be written in any order. Within VHDL all signals must be given a data type to define the values that a signal can be assigned. For the selector… …then the signals could have the following data type - where "bit" tells us that these signals can only be given values of '0' and '1' (Note Bit Values must be in single quotes) If however the selector was required to switch a bundle of wires, often called a "bus", then the following signal declaration for a vector would be required: …and where, in this case, the bus is 8 bits wide. With the above declaration we would have the following VHDL statement to define the behaviour of the selector: Notice that the actual statement remains the same - and it is only the data type that defines what format the signal has - i.e. a single wire, or a vector.


Modelling Concurrency in VHDL To model concurrency - all statements within the model are evaluated - taking the signals that appear on the Right Hand Side (RHS) of an assignment operator "<=" to derive a value for the target signal that appears on the Left Hand Side (LHS) of an assignment operator. In general, only input signals from the "entity port list" have a known value (ie whatever value they are being driven with from the outside world). As statements are evaluated then values propagate through the system, and assuming that there is no feedback loop, a stable set of values appears on all signals including the outputs. At this point - if nothing changes value then no further statements are evaluated. However, if one or more input signals change value - then the statements where the signal(s) appear on the RHS will be evaluated - this generates a possible change to the target signal(s) on the LHS of a statement - where this activity continues until a new stable state is reached. Architectures and Entities So far we have only looked at statements that describe behaviour. To be able to make use of these statements for simulation (where we can check that we have described the behaviour correctly) and for synthesis (where the behaviour gets converted into real logic) - the statements need to appear with other VHDL constructs.

• All Behavioural statements need to appear within an architecture

• An architecture must be related to an entity that defines the inputs and outputs


Looking at an example system - we have

• Inputs R & T, S & V and Sel

• Output K

• Internal wires W & Z

• The overall circuit we shall call "system" The best way of introducing the required syntax is to show the complete entity below and to then highlight the key points.

• Entities must have a name - must start with a letter and then only contain letters, numbers or underscore '_' (all declared items must follow this rule)

• The entity name cannot be a keyword in VHDL and cannot be used for any other purpose within the entity (e.g. signal name, label etc.)

• The entity name appears in three places - after the keyword "entity" - at the "end" of the entity declaration, and, within the architecture definition to link the architecture body to the entity port list definition.

• All input and output signals are declared in order within the port list.

• Each signal declaration has a name, a mode (in, out, inout), and a type.

• Signals of the same mode and type can be (as shown in the example) be declared one signal at a time, or as a list -

e.g. R, T, S, V, Sel : in bit; k: out bit;

• The architecture must have a name - not used elsewhere for other purposes.

• Any internal signals (i.e. signals not previously declared in the entity port list) are declared within the declarative area - between the "architecture" definition and the "begin".

• Behavioural statements appear between the "begin" and "end" and because they are concurrent - can appear in any order.

• Unless otherwise stated VHDL is insensitive to case where keywords and identifiers may be in lower, upper or mixed case.


Modelling real hardware in VHDL In an ideal model digital logic values can only be '0' or '1' where signals are given a type of bit or bit_vector when they are declared. In reality to accurately model the behaviour of real hardware a range of values are required. The IEEE has therefore defined a multi value type to represent 'real life' signals The type std_logic has 9 values ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-')

'U' uninitialized 'X' unknown '0', '1' strong low and high 'Z' high impedance 'W' weak unknown 'L', 'H' weak low and high

i.e. low and high values that can be driven to a '0' or a '1' '-' Don't care

(Note only '0','1','Z','-' fully supported for synthesis) All values must be as shown - in Upper Case and in single quotes.

All signals within a model are given and initial value of 'U'. Subsequent evaluations then propagate different values around the system. If a signal is not filly driven with a strong '0' or '1' then an value of 'X' unknown will be assigned to a target signal. To use type std_logic library definitions must be included before any entity definition. Library std_logic_1164 defines the std_logic data types and functions. Std_logic_arith defines arithmetic operators. Other libraries may be required to access additional data types, functions and operators. On the next pages are further examples and summary slides.


Identifier Types in VHDL

Time for some definitions........

• VHDL is a strongly typed language(You cannot assign a signal of one type to a signal of another type)

Standard types within VHDL– BIT ('0','1')

– BIT_VECTOR (0 to 3) - BIT_VECTOR (3 downto 0)

– BOOLEAN (FALSE,TRUE)

– INTEGER (-2147483647 to 2147483647)

– Enumerated e.g. type colour is (none, red, blue, green);

signal lamp : colour;

– Other additional types are provided in packages

– 1076 1993 defines type REAL - not supported for synthesis

Time for some definitions........

• VHDL is a strongly typed language(You cannot assign a signal of one type to a signal of another type)

Standard types within VHDL– BIT ('0','1')

– BIT_VECTOR (0 to 3) - BIT_VECTOR (3 downto 0)

– BOOLEAN (FALSE,TRUE)

– INTEGER (-2147483647 to 2147483647)

– Enumerated e.g. type colour is (none, red, blue, green);

signal lamp : colour;

– Other additional types are provided in packages

– 1076 1993 defines type REAL - not supported for synthesis

Identifier Types in VHDL• The IEEE has defined a multi value type to represent 'real life' signals

• std_logic ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-')

– 'U' uninitialized

– 'X' unknown

– '0', '1' strong low and high

– 'Z' high impedance

– 'W' weak unknown

– 'L', 'H' weak low and high

– '-' Don't care (only '0','1','Z','-' fully supported for synthesis)

• std_logic_vector (range) e.g. ( 7 downto 0 ) or ( 0 to 7)

signal f : std_logic_vector ( 3 downto 0 );

gives a 'bundle' of 4 'wires' f(3), f(2), f(1) & f(0)

• The IEEE has defined a multi value type to represent 'real life' signals

• std_logic ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-')

– 'U' uninitialized

– 'X' unknown

– '0', '1' strong low and high

– 'Z' high impedance

– 'W' weak unknown

– 'L', 'H' weak low and high

– '-' Don't care (only '0','1','Z','-' fully supported for synthesis)

• std_logic_vector (range) e.g. ( 7 downto 0 ) or ( 0 to 7)

signal f : std_logic_vector ( 3 downto 0 );

gives a 'bundle' of 4 'wires' f(3), f(2), f(1) & f(0)

Design Entity - Two Parts

Entity Declaration

entity example is

port ( A, B : in BIT;

F : out BIT);

end example;

Each Signal in the port listhas an identifier name,

a mode (in, out, inout),

and a type

A

B

Fin

in

out

example

Symbol

architecture demo1 of example is

Begin -- Behavioural description area

F <= '1' when A = '0' and B = '0' else

'1' when A = '0' and B = '1' else

'1' when A = '1' and B = '0' else

'0' when A = '1' and B = '1' else

'0' ;

end demo1;

Modelling Behaviour

Architecture Body

Truth Table

entity example is

port ( A, B : in BIT;

F : out BIT);

end example;

architecture demo1 of example is

Begin -- Behavioural description area

F <= '1' when A = '0' and B = '0' else

'1' when A = '0' and B = '1' else

'1' when A = '1' and B = '0' else

'0' when A = '1' and B = '1' else

'0' ;

end demo1;

Complete Entity

Explaining the Syntax -

"Conditional Signal Assignment"

F <= '1' when A = '0' and B = '0' else

'1' when A = '0' and B = '1' else

'1' when A = '1' and B = '0' else

'0' when A = '1' and B = '1' else

'0' ;

Target

"Signal

Assignment

Operator"

Value

Condition ( TRUE or FALSE )

Alternative Value

Final Default Value - "Must have one" This Sta

tem

ent c

ould

be re-

writte

n in a

simpler

form

......

Design Entity - Example 2

architecture demo of example2 is

begin

S <= '0' when A = '0' and B = '0' and C = '0' else

'1' when A = '0' and B = '0' and C = '1' else







'0' ;

end demo;

entity example2 is

port ( A, B, C : in BIT;

S : out BIT);

end example2;

Another example - 2 to 4 decoder

What is a

2 to 4 Decoder ?

A

B

K

L

M

N


2 to 4 Decoder ...

Describing the required behaviour.....

entity decoder is

port ( a,b : in bit; K,L,M,N : out bit );

end decoder;

architecture inside of decoder is

begin

N <= '1' when a='0' and b='0' else '0' ;

M <= '1' when a='0' and b='1' else '0' ;

L <= '1' when a='1' and b='0' else '0' ;

K <= '1' when a='1' and b='1' else '0' ;

end inside; This architecture has 4 concurrent statements

VHDL Operators

• Logical: And, or, nand, nor, xor, xnor, not

• Relational: =, /=, <, <=, >, >=

• Arithmetic: +, -, *, /

( '/' Synthesis restriction - must be power of 2)

• Other operators exist for shift functions, MOD, REM...

• Logical: And, or, nand, nor, xor, xnor, not

• Relational: =, /=, <, <=, >, >=

• Arithmetic: +, -, *, /

( '/' Synthesis restriction - must be power of 2)

• Other operators exist for shift functions, MOD, REM...

• Extensions in data types and operators may be included

in an entity by the use of library packages e.g.

Library IEEE;

Use IEEE.Std_logic_1164.all;

Use IEEE.Std_logic_arith.all;

• Extensions in data types and operators may be included

in an entity by the use of library packages e.g.

Library IEEE;

Use IEEE.Std_logic_1164.all;

Use IEEE.Std_logic_arith.all;

VHDL Modelling - Describing Behaviour

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