2016 International Symposium on Quality Electronic DesignMarch 15-16, 2016, Santa Clara, CA USA

Low supply voltage test to screen resistive bridges in OTPsPeter Sarson, CMgr MCMI CEng MIET, ams AG | peter.sarson@ams.com | Paper ID: 11

1. Introduction

An issue was found with a product running in production that contained an OTP block. It was found that a few ppm failed read-ing the memory content at low temperature. In production these devices were originally tested at the spec supply voltage of 2.2 V. A way of screening had to be found preventing low temperature fails reaching the field. The initial step was to introduce a low tem-perature screen for this product with immediate success. However these low temperature failures needed to be removed at 35 de-grees. The following will show how a low voltage screen was devel-oped that ensured good product quality. After running a few lots one could see there was a large lot to lot variation of the low tem-perature, cold, probe failures. This is demonstrated in the regions indicated in Fig. 1, which gave rise to confidence issues in the qual-ity of the product delivered. After some research it was found that very low voltage testing was used to find resistive bridge faults in low geometry technologies, and that could be applicable to this problem.

4. Further Supply Voltage Correlation

After probing several wafers at cold, Fig. 3, and 35 degrees with voltage steps from 1.75 V to 2.2 V it was found that 1.8V, Fig. 4, gave the best coverage compared to the cold failures.

2. Experimenting with a low voltage screen

Experimenting with a very low supply voltage of 2 V for this tech-nology gave rise to a good correlation of failures at cold, however another issue was identified at the same time, Fig. 2, with respect to the step field.

3. Root Cause

The OTP cell in question works with oxide breakdown technology i.e. when a fuse is programmed the oxide is blown through causing a short or a higher leakage of 100x compared to the non-blown fuses. In the case of badly blown fuses or poor oxide breakdown the short looks more like a resistive bridge resulting in only 10x higher leakage compared to a non-blown fuse. At room tempera-ture with typical supply voltage the difference is still detectable and a programmed fuse can be seen as a blown fuse. However once the temperature is dropped to -40 degrees the leakage current of the blown fuse decreases hence if an oxide is not totally broken down it can be seen as a non-blown fuse resulting in bits being seen to flip from programmed to not programmed. By reducing the voltage to a lower value the leakage current is decreased and the possibility of detecting a badly blown fuse is significantly increased. The question is by how much does the supply voltage need to be dropped at 35 degrees to ensure all quality issues due to badly blown fuses are detected without affecting the normal operating conditions of the device.

5. Results of the layout modification

It was found that the nwell didn’t have a large enough process window to allow for marginal mask alignment issues in the fabri-cation process that led to the step field issues seen in production. This was causing issues with the oxide breakdown, causing resis-tive bridges rather than shorts for programmed fuses. By increas-ing the NWELL to ACTIVE AREA there is more tolerance for mask misalignment, thereby eliminating the issue.

Once wafers were received with the modified layout the wafers were subjected to the standard flow that was developed to iden-tify the issues at cold. Fig. 5 shows the results from the cold screen of a wafer with the modified process. It can be seen that all trace of a step field is gone and that the fails are randomly distributed as expected. Although the results from the cold screen are very good, it would be ideal if the cold screen could be skipped completely hence making a significant reduction in production costs. Exam-ining Fig. 6 shows that all the cold failures are covered by the very low supply voltage screen. These dice have been identified by a blue circle for ease of identification. From this it can be concluded that the cold screen can now be considered for complete removal as the very low supply voltage screen captures all the cold failures at 35 degrees. However this can only be done after multiple wafer lots have been tested with no failures during the cold screen.

Conclusion

It has been shown that by using a very low supply voltage screen for parameters sensitive to cold temperature, a reliable and most effective technique can be developed to remove such problem devices resulting either from process issues or from randomly expected defects; one can have a high degree of confidence in shipping high quality, in the sub ppm region, and have reliable dice even when suspect wafers have been produced.

Fig. III ppm fail at minus Fig. IV Captured at 1.8V

Fig. I Wafermap of -40 degree failures Fig. II OTP fails at 35 deg@2V–StepField

Fig V. Minus probe with new NWELL Fig VI. Minus fails caught at 35deg